Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I, Claims 1-13, in the reply filed May 4, 2026 is acknowledged. Claims 14-20 are withdrawn as they are directed to a nonelected invention.
Specification
The disclosure is objected to because of the following informalities:
Fig. 3C is referred to in ¶ 0055. However, the drawings do not contain Fig. 3C.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 3, 5, 6, 13 are rejected under 35 U.S.C. 103 as being unpatentable over Yamada et al. (“Yamada”), US 10,115,459, in view of Amando et al. (“Amando”), US 2022/0399232.
Regarding Claim 1, Yamada discloses a semiconductor structure (Figs. 12B-14, 17, 28; col. 3 lines 46-54), comprising:
a contact-level dielectric layer (73; Fig. 13A; col. 16 lines 41-44 “contact level dielectric layer 73…over the memory stack structures 55”) overlying semiconductor devices (55; Figs. 12B-13A; col. 16 lines 27-40, col. 21 lines 16-34);
contact-level metal structures (88; Fig. 13A; col. 22 lines 1-2 “contact via structures 88”) embedded in the contact-level dielectric layer (Fig. 13A; col. 22 lines 1-3 “contact via structures 88 can be formed through the contact level dielectric layer 73 on each drain region 63”) and electrically connected to a respective electrical node (63; Fig. 13A; col. 22 line 3 “drain region 63”) of the semiconductor devices (Fig. 13A);
a via-level dielectric layer (80; Fig. 14; col. 22 lines 21-22 “dielectric layer 80 can be formed over the contact level dielectric layer 73”) overlying the contact-level dielectric layer (Fig. 14);
an etch-stop dielectric layer overlying the via-level dielectric layer (not shown; col. 22 lines 23-27 “dielectric layer 80 can…incorporate a dielectric cap material layer such as nitrogen-doped organosilicate glass, silicon nitride, or silicon oxynitride”);
integrated line-and-via structures (122, 122A, 122B, 122C; Figs. 14, 16; col. 23 lines 42-44 “metal electrically conductive structure 122, which can be a line structure (such as a bit line of the three-dimensional memory device described above) or a via structure”) each comprising a metal line portion and at least one via portion (col. 23 lines 42-44 “metal electrically conductive structure 122, which can be a line structure (such as a bit line of the three-dimensional memory device described above) or a via structure”), wherein each via portion of the integrated line-and-via structures vertically extends through the etch-stop dielectric layer and the via-level dielectric layer and contacts a top surface of a respective one of the contact-level metal structures (Fig. 14; col. 22 line 65 to column 23 line 1 “A top surface of an intermediate level metal electrically conductive structures 98 can be physically exposed at the bottom of each opening in the first dielectric material layer 110.”, col. 22 lines 33-40 “The intermediate level metal electrically conductive structures 98 can include conductive via structures that provide vertically conductive paths (e.g., vertical electrical connections) and/or conductive line structures that provide laterally conductive paths in addition to vertical electrical connections to underlying conductive structures (such as the drain contact via structures 88) and/or overlying conductive structures to be subsequently formed.”, therefore via portion 122 (extends through 110 and) extends through the etch-stop dielectric layer and the via-level dielectric layer 80 and contacts a top surface of a respective one of the contact-level metal structures 88), and the metal line portions (122) are laterally spaced apart from each other along a first horizontal direction (Figs. 27-28; col. 30 lines 1-19) and laterally extend along a second horizontal direction (Figs. 27-28; col. 30 lines 1-19);
dielectric rails (140; Fig. 17; col. 24 line 61 “dielectric material layer 140”, col. 25 line 32-43) located between neighboring pairs of metal line portions of the metal line portions (Fig. 17; col 25 line 27 “dielectric material layer 140…physically contacts each of the second metallic liners 122C”); and
air gaps (139; Fig. 17; col. 25 lines 1-3 “dielectric material layer 140 can include at least one cavity (e.g., air gap) 139 filled with vacuum or a gas phase material”) located between neighboring pairs of the metal line portions (Fig. 17; col. 25 lines 25-27 “dielectric material layer 140, surrounds each of the at least one cavity 139, physically contacts each of the second metallic liners 122C”) and at least partially enclosed by the respective dielectric rails (Fig. 17; col. 25 lines 25-27 “dielectric material layer 140, surrounds each of the at least one cavity 139, physically contacts each of the second metallic liners 122C”).
Yamada does not disclose discrete etch-stop dielectric cap rails that overlie top surfaces of the respective metal line portions.
Amando discloses discrete etch-stop dielectric cap rails (130; Fig. 16C; ¶ 0153 “capping dielectric strips 130”) that overlie top surfaces (Fig. 16C; ¶ 0153 “Each of the bit lines 108 is contacted by a bottom surfaces of a respective capping dielectric strip 130.”) of the respective metal line portions (108; Figs. 15A, 16C; ¶ 0153 “bit lines 108”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Yamada to have discrete etch-stop dielectric cap rails that overlie top surfaces of the respective metal line portions, as taught by Amando, because “electrical shorts between the bit-line-contact via structure 168 and adjacent bit lines 108 can be reduced or prevented by increasing the vertical distance between the bit lines 108 and the bit-line-contact via structure 168 by inserting the etch stop dielectric layer 120 and the capping dielectric strips 130” (Amando ¶ 0180 and Fig. 17D) and “also decrease the bit line RC delay and leakage current” (Amando ¶ 0180) thereby improving the performance and reliability of the semiconductor structure.
Regarding Claim 2, Yamada discloses one of the metal line portions (122) comprises a pair of tapered metallic sidewalls (Figs. 14, 17: col. 23 lines 1-2 “sidewalls…can be…tapered”, col. 23 lines 3-7, col. 23 lines 23-24) that are contained within a pair of non-vertical Euclidean planes (Fig. 28) that laterally extend along the second horizontal direction (Figs. 27-28; col. 30 lines 1-13).
Yamada does not disclose one of the etch-stop dielectric cap rails contacts a top surface of said one of the metal line portions, and comprises a pair of tapered dielectric sidewalls that are contained within the pair of non-vertical Euclidean planes.
Amando discloses one of the etch-stop dielectric cap rails (130) contacts a top surface of said one of the metal line portions (Fig. 16C; ¶ 0153 “Each of the bit lines 108 is contacted by a bottom surfaces of a respective capping dielectric strip 130.”), and comprises a pair of tapered dielectric sidewalls (Figs. 4I, 16C; ¶ 0136 “bit-line trenches 107 may have a respective vertical cross-sectional profile of an inverted trapezoid”, ¶ 0143 “bit lines 108 can have an inverted trapezoidal vertical cross-sectional shape”, ¶ 0146 “an isotropic etch process” so that “top surfaces of the bit lines 108 can be recessed below the horizontal plane including the top surface of the etch stop dielectric layer 120”, ¶ 0151 “dielectric material is deposited in volumes of the bit-line trenches 107 that remain after formation of the bit lines 108”, ¶ 0151 “each of the capping dielectric strips 130 can have a top surface located within the horizontal plane including the top surface of the etch stop dielectric layer 120”, therefore one of the etch-stop dielectric cap rails comprises a pair of tapered dielectric sidewalls) that are contained within the pair of non-vertical Euclidean planes (Fig. 15D; ¶ 0143 “bit lines 108 can be formed as a one-dimensional periodic array of bit lines 108”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Yamada to have one of the etch-stop dielectric cap rails contacts a top surface of said one of the metal line portions, and comprises a pair of tapered dielectric sidewalls that are contained within the pair of non-vertical Euclidean planes, as taught by Amando, because “electrical shorts between the bit-line-contact via structure 168 and adjacent bit lines 108 can be reduced or prevented by increasing the vertical distance between the bit lines 108 and the bit-line-contact via structure 168 by inserting the etch stop dielectric layer 120 and the capping dielectric strips 130” (Amando ¶ 0180 and Fig. 17D) and “also decrease the bit line RC delay and leakage current” (Amando ¶ 0180) thereby improving the performance and reliability of the semiconductor structure.
Regarding Claim 3, Yamada discloses
the etch-stop dielectric layer comprises a silicon nitride or a silicon carbonitride layer (col. 22 lines 25-26 “dielectric cap material layer such as…silicon nitride”).
Yamada does not disclose
the discrete etch-stop dielectric cap rails comprise silicon nitride or a silicon carbonitride rails; and
the dielectric rails comprise silicon carbide or silicon oxycarbide rails.
Amando discloses
the discrete etch-stop dielectric cap rails comprise silicon nitride or a silicon carbonitride rails (¶ 0152 “130 may comprise a dielectric material selected from…silicon nitride”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Yamada to have the discrete etch-stop dielectric cap rails comprise silicon nitride or a silicon carbonitride rails, as taught by Amando, because the silicon nitride discrete etch-stop dielectric cap rails allow “electrical shorts between the bit-line-contact via structure 168 and adjacent bit lines 108 can be reduced or prevented by increasing the vertical distance between the bit lines 108 and the bit-line-contact via structure 168 by inserting the etch stop dielectric layer 120 and the capping dielectric strips 130” (Amando ¶ 0180 and Fig. 17D) and “also decrease the bit line RC delay and leakage current” (Amando ¶ 0180) thereby improving the performance and reliability of the semiconductor structure.
Yamada as modified by Amando lacks the dielectric rails comprise silicon carbide or silicon oxycarbide rails.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Yamada to include silicon carbide as at least a part of the rails because it is known to have a very high dielectric breakdown strength which will protect the semiconductor device of Yamada as modified from current leakage allowing the semiconductor device to be more efficient and have a longer lifespan.
Regarding Claim 5, Yamada discloses
one of the metal line portions (122) comprises a top surface (Figs. 14, 16, 17 a vertically top surface of 122) having a first width (Figs. 14, 16, 17 a horizontal width of the top surface) along the first horizontal direction (Figs. 14, 16, 17 left to right) and comprises a bottom surface (Figs. 14, 16, 17 a vertically bottom surface of 122) having a second width (Figs. 14, 16, 17 a horizontal width of the bottom surface) along the first horizontal direction; and
the second width is less than the first width (Figs. 14, 16, 17).
Regarding Claim 6, Yamada discloses
a first air gap (139; Fig. 17; col. 25 lines 1-3 “at least one cavity (e.g., air gap) 139 filled with vacuum or a gas phase material”) of the air gaps (Fig. 17) is located entirely within a respective one of the dielectric rails (Fig. 17; col. 25 lines 25-26 “dielectric material layer 140, surrounds each of the at least one cavity 139”);
an entirety of surfaces of the first air gap consists of inner dielectric surfaces of one of the dielectric rails (Fig. 17; col. 25 lines 25-26 “dielectric material layer 140, surrounds each of the at least one cavity 139”); and
the first air gap is completely enclosed (Fig. 17; col. 25 lines 25-26 “dielectric material layer 140, surrounds each of the at least one cavity 139”) by the respective one of the dielectric rails (Fig. 17; col. 25 lines 25-26 “dielectric material layer 140, surrounds each of the at least one cavity 139”).
Regarding Claim 13, Yamada discloses wherein the semiconductor devices (55) comprise three-dimensional memory devices (Fig. 6; col. 17 lines 45-47 “memory array region 100 comprises an array of monolithic three-dimensional NAND strings”) comprising an alternating stack (Fig. 12A; col. 21 line 27 “alternating stack (32, 46)”) of insulating layers (32; Fig. 12A; col. 20 line 60 “insulating layers 32”) and electrically conductive layers (46; Fig. 12A; col. 20 line 61 “electrically conductive layers 46”), and memory opening fill structures (11, 55, 62, 63; Figs. 5H, 6; col. 16 lines 19-20 “memory opening fill structures (11, 55, 62, 63)”) each comprising a memory film (50; Fig. 6; col. 16 line 29 “memory film 50”) and a vertical semiconductor channel (60, 601, 602; Fig. 6; col. 16 lines 27-29 “memory stack structure 55 includes a vertical semiconductor channel 60, which may comprise multiple semiconductor channel layers (601, 602)”) extending through the alternating stack (Fig. 6), wherein the metal line portions comprise bit lines (Figs. 13A, 14: col. 23 lines 42-44 “122, which can be a line structure (such as a bit line of the three-dimensional memory device”) of the three-dimensional memory devices (Figs. 13A, 14: col. 23 lines 42-44 “122, which can be a line structure (such as a bit line of the three-dimensional memory device”).
Claims 4, 9, 10 are rejected under 35 U.S.C. 103 as being unpatentable over Yamada et al. (“Yamada”), US 10,115,459, and Amando et al. (“Amando”), US 2022/0399232, as applied to Claim 1, and further in view of Matsuno et al. (“Matsuno”), US 11,387,142.
Regarding Claim 4, Yamada as modified by Amando does not disclose
one of the metal line portions comprises a top surface having a first width along the first horizontal direction and comprises a bottom surface having a second width along the first horizontal direction; and
the second width is greater than the first width.
Matsuno discloses
one of the metal line portions (118; Fig. 15D; col. 27 line 22 “bit lines 118”, col. 27 lines 29-30 “bit lines 118 can have a trapezoidal vertical cross-sectional shape”) comprises a top surface (Fig. 15D the top surface of 118) having a first width (Fig. 15D the width of the top surface of 118) along the first horizontal direction (Fig. 15D left to right) and comprises a bottom surface (Fig. 15D the bottom surface of 118) having a second width (Fig. 15 D the width of the bottom surface of 118) along the first horizontal direction; and
the second width is greater than the first width (Fig. 15D).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Yamada as modified to have one of the metal line portions comprises a top surface having a first width along the first horizontal direction and comprises a bottom surface having a second width along the first horizontal direction; and the second width is greater than the first width, as taught by Matsuno, so that “inter-bit-line trenches 117 may be relatively narrow, such that the bit lines 118 are relatively closely spaced” (Matsuno col. 27 lines 55-56), thereby providing a more compact semiconductor structure.
Regarding Claim 9, Yamada as modified by Amando does not disclose
a first air gap of the air gaps is located entirely below a respective one of the dielectric rails;
an upper surface of the first air gap comprises a lower dielectric surface of the respective one of the dielectric rails;
a lower surface of the first air gap comprises an upper dielectric surface of the etch-stop dielectric layer; and
the first air gap is partially enclosed by the respective one of the dielectric rails.
Matsuno discloses
a first air gap (217, 229; Fig. 21B; col. 32 lines 16-18 “cavity (i.e., air gap) 229 that is adjoined to a top portion of the multi-level cavity (i.e., air gap) 217”) of the air gaps (Fig. 21A) is located entirely below (Fig. 21B; col. 32 lines 20-23 “the top end of the continuous air gap (e.g., the top end of the via-level cavity 229) does not extend above the bottom surface of capping-level material layer 126”) a respective one of the dielectric rails (126; Fig. 21B; col. 31 line 51 “layer 126 may include silicon oxide, silicon nitride”);
an upper surface of the first air gap (Fig. 21B; col. 32 lines 21-22 “top end of the via-level cavity 229”) comprises a lower dielectric surface (Fig. 21B; col. 32 lines 31-32 in this instance the lower dielectric surface of “downward-protruding portion 126P of the capping-level material layer 126”) of the respective one of the dielectric rails (Fig. 21B);
a lower surface (Fig. 21B; col. 32 line 62-63 “surfaces of the dielectric liner 108”) of the first air gap comprises an upper dielectric surface (106; Figs. 20B, 21B; col. 32 line 63 to col. 33 line 1 “an array of discrete dielectric material portions 106 having a same material composition as the capping-level material layer 126 can be located below the conduit openings 127. The discrete dielectric material portions 106 can have a respective bottom surface within the second horizontal plane HP2A”) of the etch-stop dielectric layer (108; Fig. 21B; col. 33 lines 16-19 “dielectric liner 108 that overlie the recessed horizontal surfaces of the of the connection-level dielectric layer 90 are located within the second horizontal plane HP2A”); and
the first air gap is partially enclosed (Fig. 21B; col. 32 lines 13-18 “each volume of the cavity-containing openings that is not filled with a respective downward-protruding portion 126P of the capping-level material layer 126 comprises a respective via-level cavity (i.e., air gap) 229 that is adjoined to a top portion of the multi-level cavity (i.e., air gap) 217”) by the respective one of the dielectric rails (126).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Yamada as modified to have a first air gap of the air gaps is located entirely below a respective one of the dielectric rails; an upper surface of the first air gap comprises a lower dielectric surface of the respective one of the dielectric rails; a lower surface of the first air gap comprises an upper dielectric surface of the etch-stop dielectric layer; and the first air gap is partially enclosed by the respective one of the dielectric rails, as taught by Matsuno, so that “inter-bit-line trenches 117 may be relatively narrow, such that the bit lines 118 are relatively closely spaced” (Matsuno col. 27 lines 55-56), thereby providing a more compact semiconductor structure.
Regarding Claim 10, Yamada as modified by Matsuno does not disclose
the dielectric rails have planar top surfaces that are contained within a horizontal plane including top surfaces of the etch-stop dielectric cap rails; and
a vertical cross-sectional profile of one of the air gaps along a vertical plane that is perpendicular to the second horizontal direction has a pointed tip portion having a decreasing width as a function of an increasing distance from a horizontal plane including a bottom surface of the etch-stop dielectric layer.
Matsuno discloses
the dielectric rails (106; Figs. 20B, 21B; col. 32 lines 63-66 “an array of discrete dielectric material portions 106 having a same material composition as the capping-level material layer 126 can be located below the conduit openings 127”) have planar top surfaces (Fig. 21B; col. 31 line 66 to col. 33 line 1 “discrete dielectric material portions 106 can have a respective bottom surface within the second horizontal plane HP2A” in this instance the planar bottom surface within the second horizontal plane HP2A) that are contained within a horizontal plane (HP2A; Fig. 21B; col. 33 line 1 “horizontal plane HP2A”) including top surfaces (col. 33 lines 15-19 “top surfaces of horizontally-extending portions of the dielectric liner 108…located within the second horizontal plane HP2A”) of the etch-stop dielectric cap rails (108; Fig. 21B; col. 33 line 11 “dielectric liner 108”); and
a vertical cross-sectional profile of one of the air gaps (217, 229; Fig. 21B; col. 32 lines 33-36 “a respective via-level cavity 229 (i.e., an upper air gap comprising an unfilled volume of a conduit opening) that is adjoined to a top portion of the multi-level cavity (i.e., a lower air gap) 217”) along a vertical plane (Fig. 21B; col. 3 line 61 “FIG. 21B is a vertical cross-sectional view”) that is perpendicular to the second horizontal direction (hd1; Fig. 21A) has a pointed tip portion (col. 32 lines 36-39 “each via-level cavity 229 has a variable horizontal cross-sectional area that increases with a vertical distance from a horizontal plane including a planar bottom surface of the capping-level material layer 126”) having a decreasing width as a function of an increasing distance (Fig. 21B; col. 32 lines 6-7 “The thickness of the downward-protruding portions 126P becomes thinner toward their bottom sides.”, col. 32 lines 36-39 “each via-level cavity 229 has a variable horizontal cross-sectional area that increases with a vertical distance from a horizontal plane including a planar bottom surface of the capping-level material layer 126”) from a horizontal plane (recessed surfaces of the connection-level dielectric layer 90; Fig. 21B; col. 28 lines 43-46) including a bottom surface (Fig. 21B; col. 28 lines 43-46 “dielectric liner 108 comprising a dielectric material can be deposited over…recessed surfaces of the connection-level dielectric layer 90”, in this instance a bottom surface of etch stop dielectric layer 108 is a horizontal plane including a bottom surface of etch stop dielectric layer 108) of the etch-stop dielectric layer (Fig. 21B).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Yamada as modified to have the dielectric rails have planar top surfaces that are contained within a horizontal plane including top surfaces of the etch-stop dielectric cap rails; and a vertical cross-sectional profile of one of the air gaps along a vertical plane that is perpendicular to the second horizontal direction has a pointed tip portion having a decreasing width as a function of an increasing distance from a horizontal plane including a bottom surface of the etch-stop dielectric layer, as taught by Matsuno, so that “inter-bit-line trenches 117 may be relatively narrow, such that the bit lines 118 are relatively closely spaced” (Matsuno col. 27 lines 55-56), thereby providing a more compact semiconductor structure.
Claims 7, 8 are rejected under 35 U.S.C. 103 as being unpatentable over Yamada et al. (“Yamada”), US 10,115,459, and Amando et al. (“Amando”), US 2022/0399232, as applied to Claim 1, and further in view of Scarbrough et al. (“Scarbrough”), US 2023/0207458.
Regarding Claim 7, Yamada as modified by Amando does not disclose wherein the dielectric rails have planar bottom surfaces that are contained between a horizontal plane including a top surface of the etch-stop dielectric layer and a horizontal plane including a bottom surface of the etch-stop dielectric layer.
Scarbrough discloses wherein the dielectric rails (128; Fig. 4K; ¶ 0051 “subconformal dielectric material 128 to form air gaps 438”) have planar bottom surfaces (Figs. 4G-4H; ¶ 0051) that are contained between a horizontal plane including a top surface of the etch-stop dielectric layer (top surface of lower 434; Fig. 4K; ¶ 0049 in this instance the top surface of “lower nitride material 434” that is within “electrically insulating material 424”) and a horizontal plane including a bottom surface of the etch-stop dielectric layer (bottom surface of lower 434; Fig. 4K; ¶ 0049 in this instance the bottom surface of “lower nitride material 434” that is within “electrically insulating material 424”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Yamada as modified to have wherein the dielectric rails have planar bottom surfaces that are contained between a horizontal plane including a top surface of the etch-stop dielectric layer and a horizontal plane including a bottom surface of the etch-stop dielectric layer, as taught by Scarbrough, because “the subconformality of the subconformal dielectric material 128 may be adjusted to increase or decrease the size of the air gaps 438 defined by the subconformal dielectric material 128” (Scarbrough¶ 0051) thereby optimizing the performance of the semiconductor structure, and “since the bit lines 102a-102g are separated from the air gaps 438 by…the subconformal dielectric material 128, shorting between the bit lines, such as between copper portions of the bit lines, may be prevented” (Scarborough ¶ 0057) thereby optimizing the performance and reliability of the semiconductor structure.
Regarding Claim 8, Yamada as modified by Amando does not disclose wherein one of the dielectric rails comprises:
a bottom surface contacting a recessed horizontal surface of the etch-stop dielectric layer;
a pair of lower tapered sidewalls contacting sidewalls of the etch-stop dielectric layer; and
a pair of upper tapered sidewalls contacting sidewalls of a pair of metal line portions of the integrated line-and-via structures.
Scarborough discloses wherein one of the dielectric rails (128) comprises:
a bottom surface (Fig. 4K a bottom surface of 128) contacting (Fig. 4K in this instance indirectly contacting) a recessed horizontal surface of the etch-stop dielectric layer (Fig. 4K a recessed horizontal surface of lower 434);
a pair of lower tapered sidewalls (Fig. 4K two lower tapered sidewalls of 128) contacting (Fig. 4K in this instance indirectly contacting) sidewalls of the etch-stop dielectric layer (Fig. 4K sidewalls of lower 434); and
a pair of upper tapered sidewalls (Fig. 4K two upper tapered sidewalls of 128) contacting (Fig. 4K in this instance indirectly contacting) sidewalls of a pair of metal line portions (Fig. 4K sidewalls of adjacent metal line portions 114; ¶ 0056 “electrically conductive material 114”) of the integrated line-and-via structures (¶ 0056 “first electrically conductive material 112 and the second electrically conductive material 114, in combination, form the bit lines 102a-102g”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Yamada as modified to have wherein one of the dielectric rails comprises: a bottom surface contacting a recessed horizontal surface of the etch-stop dielectric layer; a pair of lower tapered sidewalls contacting sidewalls of the etch-stop dielectric layer; and a pair of upper tapered sidewalls contacting sidewalls of a pair of metal line portions of the integrated line-and-via structures, as taught by Scarbrough, because “the subconformality of the subconformal dielectric material 128 may be adjusted to increase or decrease the size of the air gaps 438 defined by the subconformal dielectric material 128” (Scarbrough¶ 0051) thereby optimizing the performance of the semiconductor structure, and “since the bit lines 102a-102g are separated from the air gaps 438 by…the subconformal dielectric material 128, shorting between the bit lines, such as between copper portions of the bit lines, may be prevented” (Scarborough ¶ 0057) thereby optimizing the performance and reliability of the semiconductor structure.
Allowable Subject Matter
Claims 11-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding Claim 11, the prior art does not teach or render obvious wherein: one of the integrated line-and-via structures comprises a metallic barrier liner comprising a conductive metal nitride material and a metal fill material portion; interfaces between the one of the integrated line-and-via structures and a pair of dielectric rails of the dielectric rails comprises interfaces between the metal fill material portion and the pair of dielectric rails; and the metallic barrier liner contacts lower portions of sidewalls of the pair of dielectric rails. Therefore, the combination of the features of Claims 1 and 11 is considered allowable.
Regarding Claim 12, the prior art does not teach or render obvious wherein: one of the integrated line-and-via structures comprises a metallic barrier liner comprising a conductive metal nitride material and a metal fill material portion; interfaces between the one of the integrated line-and-via structures and a pair of dielectric rails of the dielectric rails consist of interfaces between the metallic barrier liner and the pair of dielectric rails; and the metallic barrier liner contacts peripheral portions of a bottom surface of one of the etch-stop dielectric cap rails. Therefore, the combination of the features of Claims 1 and 12 is considered allowable.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Titus et al., US 2022/0246517, discloses a three-dimensional memory device having field effect transistors and via cavities. Said et al., US 2022/0059462 discloses a three-dimensional memory device having contact-level metal structures and integrated line-and-via structures. Said et al., US 2021/0193585, discloses a three-dimensional memory device having drain contact via structures. Lu et al., US 9,530,790, discloses a three-dimensional memory device having drain contact via structures and integrated line-and-via structures.
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/R.K./Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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