DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 9 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 9 recites “the conductive member extends across the first surface.” However, the first surface is a surface of the conductive member. It is unclear how the conductive member “extends across” it’s own surface.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5-7 and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Saito (U.S. Publication No. 2019/0139873).
Regarding claim 1, Saito teaches a semiconductor device comprising:
a first lead (Fig. 6, lead 20);
a semiconductor element (element 30) provided with a first electrode (electrode 31, see Fig. 5-6);
a conductive member (conductive member 40) electrically connecting the first lead and the first electrode to each other (Fig. 6);
a first conductive joining layer (joining layer 73) conductively joining the first lead and the conductive member to each other (Fig. 6); and
a second conductive joining layer (joining layer 72) conductively joining the first electrode and the conductive member to each other (Fig. 6),
wherein the conductive member includes a first surface (bottom surface facing down toward 20) facing the first lead in a thickness direction of the semiconductor element, and a second surface (right surface facing lead 20) facing the first lead in a first direction orthogonal to the thickness direction,
the first lead includes a third surface facing the first surface (top surface at recess 23 in lead), and a fourth surface facing the second surface (sidewall surface 23a is pointed in Fig. 6), and
the first conductive joining layer is in contact with the first surface and the third surface (Fig. 6, located in entire notch).
Regarding claim 2, Saito teaches the semiconductor device according to claim 1, wherein the third surface faces toward a same side as an outer surface of the first electrode in the thickness direction (faces up, which is thickness direction of electrode which is on top surface of chip 30, see Fig. 5-6).
Regarding claim 3, Saito teaches the semiconductor device according to claim 2, wherein the first conductive joining layer is in contact with the second surface and the fourth surface (Fig. 6).
Regarding claim 5, Saito teaches the semiconductor device according to claim 3, wherein a largest value of a first interval from the first surface to the third surface is smaller than a largest value of a second interval from the second surface to the fourth surface (see Fig. 7 and 18).
Regarding claim 6, Saito teaches the semiconductor device according to claim 3, wherein the first lead includes a first obverse surface facing toward the same side as the third surface in the thickness direction (top surface outside of notch), and
the first obverse surface is located on a side of the fourth surface opposite to the third surface in the thickness direction (Fig. 5-6).
Regarding claim 7, Saito teaches the semiconductor device according to claim 6, wherein the fourth surface faces toward a side on which the semiconductor element is located in the first direction (Fig. 6).
Regarding claim 10, Saito teaches the semiconductor device according to claim 7, wherein the first lead includes a first mounting surface facing toward a side opposite to the third surface in the thickness direction (bottom surface), and a fifth surface facing toward the same side as the fourth surface in the first direction (sidewall between bottom surface and “third surface”),
the third surface overlaps with the first mounting surface as viewed in the thickness direction (Fig. 6), and
the fifth surface is located between the first mounting surface and the third surface in the thickness direction and is located on a side of the third surface opposite to the fourth surface in the first direction (Fig. 6).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Saito in view of Choi (U.S. Publication No. 2017/0207150)
Regarding claim 4, Saito teaches the semiconductor device according to claim 3, but does not teach wherein the first surface is a curved surface recessed in the thickness direction.
However, Choi teaches that a first surface of a similar connection member can be recessed in a thickness direction (Choi Fig. 3a). It would have been obvious to a person of skill in the art at the time of the effective filing date that the end of the connection member of Saito could have been recessed because this allows for greater surface area for the connection between member and solder to be made.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Saito in view of Von Koblinski et al. (U.S. Publication No. 2021/0305198).
Regarding claim 11, Saito teaches the semiconductor device according to claim 10, but does not teach wherein the conductive member includes a restricting surface facing the fifth surface.
However, Von Koblinski teaches a conductive member includes a restricting surface (Fig. 7A, restricting surface coming down from portion 60B), facing the fifth surface (see Fig. 5, restricting surface not shown, but comes down from 52B, and would therefore rest against/face the right sidewall of 50b). It would have been obvious to a person of skill in the art at the time of the effective filing date that the conductive member of Von Koblinski could have replaced the conductive member of Saito because this allows for more surfaces to be in contact between the lead and member, reducing resistance and increasing the bond strength.
Claims 13-18 are rejected under 35 U.S.C. 103 as being unpatentable over Saito in view of Xiaochun et al. (U.S. Publication No. 2008/0164590).
Regarding claim 13, Saito teaches the semiconductor device according to claim 10, but does not teach wherein the first conductive joining layer and the second conductive joining layer contain tin.
However, Xiaochun teaches that a solder layer for a similar device can be a tin solder (paragraph [0068]). It would have been obvious to a person of skill in the art at the time of the effective filing date that the solder of Saito could have also contained tin because it would have been a simple substitution of the unknown solder of Saito for the known solder of Xiaochun.
Regarding claim 14, Saito in view of Xiaochun teaches the semiconductor device according to claim 13, further comprising:
a die pad (Saito Fig. 6, die pad 11) spaced apart from the first lead (Fig. 6); and
a joining layer (layer 71) joining the die pad and the semiconductor element to each other,
wherein the joining layer contains tin (see Xiaochun paragraph [0068] and discussion in claim 13).
Regarding claim 15, Saito in view of Xiaochun teaches the semiconductor device according to claim 14, wherein the semiconductor element is provided with a second electrode located on a side opposite to the first electrode in the thickness direction (Saito paragraph [0038]), and
the joining layer is in contact with the second electrode (paragraph [0038]).
Regarding claim 16, Saito in view of Xiaochun teaches the semiconductor device according to claim 15, further comprising
a second lead (Saito Fig. 22, second lead 20b) spaced apart from the first lead in a second direction orthogonal to the thickness direction and the first direction (Fig. 22),
wherein the semiconductor element is provided with a gate electrode (gate electrode 31b, not specifically labeled as gate, but see paragraph [0105], this is an additional electrode for a transistor instead of a diode, i.e. a gate electrode) located on a same side as the first electrode in the thickness direction (top surface), and
the second lead is electrically connected to the gate electrode (Fig. 22, connected with 45b).
Regarding claim 17, Saito in view of Xiaochun teaches the semiconductor device according to claim 14, further comprising:
a sealing resin (Saito Fig. 6, resin 50) covering the semiconductor element, the conductive member, and portions of the first lead and the die pad (Fig. 6),
wherein the die pad includes a reverse surface facing toward a side opposite to the side on which the semiconductor element is located in the thickness direction (bottom surface), and
the first mounting surface and the reverse surface are exposed from the sealing resin (see Fig. 6).
Regarding claim 18, Saito in view of Xiaochun teaches the semiconductor device according to claim 17, wherein the first lead includes a first side surface (right side surface in Fig. 6) facing toward a side opposite to the side on which the semiconductor element is located in the first direction, and
the first side surface is exposed from the sealing resin (Fig. 6).
Allowable Subject Matter
Claims 8 and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 8, the prior art, alone or in combination, fails to teach or suggest wherein the first conductive joining layer is in contact with the first obverse surface.
Regarding claim 12, the prior art, alone or in combination, fails to teach or suggest wherein a portion of the first conductive joining layer is located between the fifth surface and the restricting surface.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Evan G Clinton whose telephone number is (571)270-0525. The examiner can normally be reached Monday-Friday at 8:30am to 5:30pm.
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/EVAN G CLINTON/Primary Examiner, Art Unit 2899