DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 2, 4-13, 15 and 16 have been considered but are moot on grounds of new rejection.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2 and 4-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Okumura et al. (Okumura) (WO 2010087432 A1) in view of KOGA (US 2016/0365299 A1) as evidenced by or in view of Schuderer et al. (Schuderer) (WO 2015086184 A1).
In regards to claim 1, Okumura (Figs. 1, 3, 10, 11 and associated text) discloses a semiconductor device (Figs. 1, 3, 10, 11) comprising: a substrate (items 21 or 31 plus 21 plus 32) including an obverse surface (top surface of items 21 or 31 plus 21 plus 32) facing one side in a thickness direction; a plurality of semiconductor elements (not shown, but mentioned, electronic device section, lines 422-433 which would reside on item 51) located on the one side in the thickness direction with respect to the substrate (items 21 or 31 plus 21 plus 32), each of the plurality of semiconductor elements (not shown, but mentioned, electronic device section, lines 422-433 which would reside on item 51) having a switching function (lines 422-433, IGBT, MOSFET), and each of the plurality of semiconductor elements (not shown, but mentioned, electronic device section, lines 422-433 which would reside on item 51) being arranged in parallel to each other; a first layer (item 41) located between the obverse surface (top surface of items 21 or 31 plus 21 plus 32) and the plurality of semiconductor elements (not shown, but mentioned, electronic device section, lines 422-433 which would reside on item 51) in the thickness direction and having electrical conductivity; a second layer (item 61, lines 250-285 discloses that although not shown, that items 61, 62 can be between items 41, 42 and items 31, 32 as well) conductively bonding the obverse surface (top surface of items 21 or 31 plus 21 plus 32) and the first layer (item 41) to each other; and a third layer (items 51 or 51 plus upper item 61) conductively bonding the first layer (item 41) and the plurality of semiconductor elements (not shown, but mentioned, electronic device section, lines 422-433 which would reside on item 51) to each other, third layer (items 51 or 51 plus 61) containing sintered metal, wherein the first layer (item 41) comprises a plurality of blocks (item 41) individually separated from each other, the plurality of blocks (item 41) being disposed corresponding to the plurality of semiconductor elements (not shown, but mentioned, electronic device section, lines 422-433 which would reside on item 51), respectfully, suppress mutual thermal interface between adjacent ones of the plurality of semiconductor elements (not shown, but mentioned, electronic device section, lines 422-433 which would reside on item 51).
The method of forming a device is not germane to the issue of patentability of the device itself. Therefore, the limitation “sintered metal” has not been given patentable weight.
Okumura does not specifically disclose wherein the first layer comprises a plurality of metal blocks.
KOGA (Figs. 5, 9, 10 and associated text) discloses wherein the first layer (item 220) comprises a plurality of blocks (items 221, 222) individually separated from each other, the plurality of blocks (items 221, 222) being disposed corresponding to the plurality of semiconductor elements (item 420) which are arranged in parallel to each other (paragraph 85).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of KOGA for the purpose of conductive paths (paragraph 73) and heat dissipation.
As evidence by Schuderer (Figs. 1-14 and associated text), layers can be sintered metals (Ag sintering).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Schuderer for the purpose of reliable bonds/bonding.
In regards to claim 2, Okumura (Figs. 1, 3, 10, 11 and associated text) discloses wherein the substrate (items 21 or 31 plus 21 plus 32) includes a first metal layer (item 31) including the obverse surface, a second metal layer (item 32) located on an opposite side in the thickness direction with respect to the first metal layer (item 31), and an insulating layer (item 21) interposed between the first metal layer (item 31) and the second metal layer (item 32).
In regards to claim 4, Okumura (Figs. 1, 3, 10, 11 and associated text) as modified by KOGA (Figs. 5, 9, 10 and associated text) discloses wherein each of the plurality of semiconductor elements (not shown, but mentioned, electronic device section, lines 422-433 which would reside on item 51) is supported on one of the plurality of individual metal blocks (item 41, Okumura, items 221, 222, KOGA).
In regards to claim 5, Okumura (Figs. 1, 3, 10, 11 and associated text) as modified by KOGA (Figs. 5, 9, 10 and associated text) discloses wherein the plurality of semiconductor elements (not shown, but mentioned, electronic device section, lines 422-433 which would reside on item 51) are arranged at predetermined intervals in a first direction orthogonal to the thickness direction, and each of the plurality of metal blocks (item 41, Okumura, items 221, 222, KOGA) is larger in dimension in a second direction orthogonal to the thickness direction and the first direction than in the first direction.
In regards to claim 6, Okumura (Figs. 1, 3, 10, 11 and associated text) discloses wherein the first layer (item 41) contains copper.
In regards to claim 7, Okumura (Figs. 1, 3, 10, 11 and associated text) discloses wherein a thickness of the first layer (item 41) is larger than a thickness of the second metal layer (item 32).
In regards to claim 8, Okumura (Figs. 1, 3, 10, 11 and associated text) discloses wherein the thickness of the first layer (item 41) is ten times or less than the thickness of the second metal layer (item 32).
In regards to claim 9, Okumura (Figs. 1, 3, 10, 11 and associated text) discloses wherein the thickness of the first layer (item 41) is 2 mm to 3 mm.
In regards to claim 10, Okumura (Figs. 1, 3, 10, 11 and associated text) discloses wherein the thickness of the second metal layer (item 32) is 0.3 mm to 2.0 mm.
In regards to claim 11, Okumura (Figs. 1, 3, 10, 11 and associated text) discloses wherein the thickness of the first metal layer (item 41) is 0.1 mm to 2.0 mm.
In regards to claim 12, Okumura (Figs. 1, 3, 10, 11 and associated text) discloses wherein the first layer (item 41) is made of a material having a same thermal conductivity as the second metal layer (item 32) or a material having a greater thermal conductivity than the second metal layer (item 32).
In regards to claim 13, Okumura (Figs. 1, 3, 10, 11 and associated text) discloses wherein the third layer (items 51 or 51 plus 61) contains silver.
Claim(s) 15 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Okumura et al. (Okumura) (WO 2010087432 A1) in view of KOGA (US 2016/0365299 A1) as evidenced by or in view of Schuderer et al. (Schuderer) (WO 2015086184 A1) as applied to the claims above, and further in view of Hayashi et al. (Hayashi) (JP 2018182330 A).
In regards to claim 15, Okumura does not specifically disclose wherein each of the plurality of semiconductor elements (transistors not shown, but mentioned, electronic device section, lines 422-433 which would reside on item 51) includes a semiconductor layer containing SiC.
Hayashi (Fig. 3 and associated text) discloses wherein each of the plurality of semiconductor elements (item 31, MOSFET) includes a semiconductor layer containing SiC.
It would have been obvious to modify the invention to include a plurality of semiconductor elements that includes a semiconductor layer containing SiC, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use (In re Leshin, 125 USPQ 416).
In regards to claim 16, Okumura (Figs. 1, 3, 10, 11 and associated text) as modified by KOGA, Schuderer and Hayashi (Figs. 3, 15, 16 and associated text) discloses wherein each of the plurality of semiconductor elements (not shown, Okumura, item 31, Hayashi) includes a gate electrode (item 313, Hayashi), a source electrode (item 311, Hayashi), and a drain electrode (item 312, Hayashi), and the drain electrode (item 312, Hayashi) and the first layer (item 41, Okumura, item 211, Hayashi) are conductively bonded by the third layer (items 51 or 51 plus 61, Okumura).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TELLY D GREEN whose telephone number is (571)270-3204. The examiner can normally be reached M-F 8am-5pm.
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TELLY D. GREEN
Examiner
Art Unit 2898
/TELLY D GREEN/Primary Examiner, Art Unit 2898 May 1, 2026
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