DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions Acknowledged
Applicant’s election without traverse of Species I-2 directed to a method shown in Figs. 3-9, cancellation of device Claims 11-14, and addition of method Claims 21-24 in the Response to Restriction Requirements filed 04/03/26 has been acknowledged.
Applicant stated that all Claims 1-14 and 15-24 are directed to the method species shown in Figs. 3-9.
Status of Claims
Claims 1-10 and 15-24 are examined on merits herein.
Specification and Abstract
Abstract of the application is objected to because of its recitation: “forming of islands in the first layer”. The objection is based on a same ground that is explained below in the objection to the specification with respect to relations between islands and a first layer – the islands are not formed in the first layer, they are formed from portions of the first layer.
Appropriate correction is required.
The specification is objected to because of the following informalities:
Specification is unclear with respect to relations between islands and a first layer. As such, paragraph 0011 recites that islands are islands of the first layer; paragraph 0020 states that islands are formed in a first layer; paragraphs 0052 and 0083 teach that islands 47 are formed from portions the 49 and 51 (of a first layer).
Paragraph 0057 of the published application US 2024/0147737 has a recitation: “layer 49 forms an emitter region of transistor T2, layer 49 and layer 13 form a base region”. It looks like instead of a second “49” – a number 51 shall be shown.
Paragraph 0066 of the published application has two different identifications for a memory area: “Zl” and “Zm”, however, the memory area everywhere else is identified as Zm, while Zl is assigned for a logic area.
Paragraphs 0014 and 0111of the published application recite that trenches are formed in layers 13 and 15 between islands 47. The recitations of paragraphs 0014 and 0111 are not clear, since islands 47 are formed from portions of layer 63 created on layers 13 and 15; accordingly, trenches in layers 13 and 15 cannot be formed between islands 47 – they can be formed only between projections of the islands on layers 13 and 15. The objection is mainly made because a similar statement is repeated by the claims.
Appropriate corrections are required.
Claim Objections
Claims 1 and 15 are objected to because of the following informalities:
Three last lines of Clam 1 recite: “forming memory cells based on a phase-change material on the islands of the first layer, the second layer, the third layer, and the second sub-layer of the first layer forming a bipolar transistor.”. In order to better distinguish between different elements of a created structure, Examiner suggests changing the recitation to: “forming memory cells based on a phase-change material - on the islands of the first layer, while the second layer, the third layer, and the second sub-layer of the first layer form a bipolar transistor.”
Lines 2 and 3 of Claim 15 recites: “a first doped layer of semiconductor material” and “a second doped layer of semiconductor material”, respectively; Line 12 has a similar recitation. Examiner suggests citing “semiconductor material” in each line with an article “a”.
Appropriate corrections are required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-10, 17, and 20-24 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor regards as the invention.
In re Claim 1: Line 7 of Claim 1 recites: “forming islands in the first layer”. The recitation is unclear, since conflicts with paragraphs 0052 and 0083, teaching that islands are formed from portions of the first layer.
Appropriate correction is required to clarify the claim language.
For this Office Action, instead of interpreted the cited limitation as: “forming islands from portions of the first layer”, the limitation was interpreted as filed.
In re Claim 1: Lines 7-8 of Claim 1 recite: “at the surface of the second layer”. There is a lack of antecedent basis for citing “surface” with an article “the”, since an article “a” was not used earlier with a word: “surface”.
Appropriate correction is required.
In re Claim 5: Claim 5 recites: “trenches are formed in the second and third layers, between the islands”. The recitation is unclear, since Claim 5 depends on Claim 1, and Claim 1 teaches that islands are formed from (in) a first layer, which is disposed on the second and third layers.
Appropriate correction is required to clarify the claim language.
For this Office Action, the cited limitation was interpreted as: “trenches are formed in the second and third layers, between projections of the islands on the second and third layers”.
In re Claim 6: Claim 6 recites: “a memory cell is formed in front of each island”. The recitation is unclear, since leads to a question: Is a same memory cell formed in front of each island or a memory cell is formed in front of a corresponding single island? In addition, “in front” could be a disposition when both the island and the memory cell are formed having bottoms abutting the same layer or they can be deposited such (as in the current application) that a memory cell is over the island.
Appropriate correction is required to clarify the claim language.
For this Office Action, the cited limitation was interpreted in accordance with the specification of the application as: “a memory cell is formed over a corresponding island”.
In re Claim 8: Claim 8 recites: “The method according to claim 7, wherein the first layer is made of polysilicon”. The recitation is unclear due to dependency on Claim 7, since Claim 7 recites: “the first layer is made of polysilicon”.
Appropriate correction is required to clarify the claim language.
For this Office Action, Claim 8 was interpreted as: “The method according to claim 1, wherein the first layer is made of polysilicon”.
In re Claim 9: Claim 9 recites: “forming islands includes forming gates of MOS transistors of a logic circuit”. The recitation is unclear, since conflicts with the specification of the application, not teaching that formation of islands in a memory region includes formation of gates in a logic region, but teaching that islands and gates can be formed at a same time.
In accordance with MPEP 2173.03 Correspondence Between Specification and Claims [R-07.2022] inconsistence of the claim with the specification makes the claim indefinite, even though the terms of a claim may appear to be definite: see In re Cohn 438 F.2d 989, 169 USPQ 95 (CCPA 1971).
Appropriate correction is required to clarify the claim language.
For this Office Action, the cited limitation was interpreted in accordance with the specification as: “forming islands of a memory region are conducted at a same time as forming gates of MOS transistors of a logic circuit”.
In re Claims 2-4, 7, and 10: Claims 2-4, 7, and 10 are rejected under 35 U.S.C. 112(b) due to dependency on Claim 1.
In re Claim 17: Claim 17 recites: “doping an area of the layer of semiconductor material with the first conductivity type”. The recitation is unclear for a few reasons.
Initially, Claim 17 is unclear due to its dependency on Claim 15 that recites “semiconductor material” three times, and each time, it refers to a different semiconductor material, while Claim 17 does not clarify which semiconductor material of Claim 15 it refers to.
In addition, a doping area (27 of semiconductor material 23 of the current application) has a same conductivity type (N) as “a second doped layer... of a second conductivity type”, as Claim 15 recites. Accordingly, the doping area 27 also shall be doped to have the second conductivity.
Appropriate correction is required to clarify the claim language.
For this Office Action, the cited recitation is interpreted as: “doping an area of the layer of semiconductor material disposed between the islands with the second conductivity type”.
In re Claim 20: Claim 20 has a same issue as Claim 5, and, for this Office Action, it is interpreted in a similar manner.
In re Claim 21: Claim 21 recites (line 5): “forming islands organized in an array of rows and columns on the surface of the second doped semiconductor layer”. There is a lack of antecedent basis for using “surface” with article “the”. Appropriate correction is required.
In re Claims 22-24: Claims 22-24 are rejected under 35 U.S.C. 112(b) due to dependency on Claim 21.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
As far as the claims are understood, Claims 1, 6, and 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cho et al.(US 2006/0186483).
In re Claim 1, Cho teaches a method, comprising:
forming (Figs. 9-10, paragraphs 0071, 0107) a first layer 7, 9, 11 (when 13 is not needed, paragraph 0075) on top of and in contact with a second doped semiconductor layer 5 of a first conductivity type (such as N-type, paragraph 0067), the second layer 5 being on top of and in contact with a third doped semiconductor layer 2, 1 of a second conductivity type – such as P-type (paragraph 0101) opposite to the first conductivity type (N-type);
doping (Figs. 10, paragraph 0111) the first layer 7 to form, on the second layer 5, a first doped sub-layer – comprised portions 9 - of the first conductivity type (N-type) and a second doped sub-layer – comprised portions 11 - of the second conductivity type (P-type);
forming (Figs. 9-10, paragraph 0109) islands (each comprised a stack of two elements 9 and 11) in the first layer 7 organized in an array of rows and columns (to correspond an array of Fig. 4, paragraphs 0042-0053) at the surface of the second layer 5; and
forming (Figs. 11) memory cells – comprised elements 19, 21, 23 (paragraph 0115) based on a phase-change material 21 on the islands of the first layer (9, 11), the second layer 5, the third layer 2, 1, and the second sub-layer 11 of the first layer 7 forming a bipolar transistor (as identified in Fig. 5A, paragraph 0078).
In re Claim 6, Cho teaches the method according to Claim 1, wherein (as Figs. 10 show) a memory cell 19/21/23 is formed in front of each island 9//11.
In re Claim 21, Cho teaches a method, comprising:
forming (Figs. 8-9, paragraphs 0100-0101) a first doped semiconductor layer 1, 2 of a first conductivity type (which is a P-type);
forming (Figs. 9, paragraph 0101) a second doped semiconductor layer 5 of a second conductivity type – such as an N-type - opposite the first conductivity type (which is the P-type) on top of and in contact with the first doped semiconductor layer 1, 2;
forming (Figs. 9-10, paragraphs 0108-0109, 0111) islands organized in an array of rows and of columns (corresponding to rows and columns of Fig. 4, paragraph 0092) on the surface of the second doped semiconductor layer 5, each island including a first doped sub-layer 9 of the second conductivity type (N-type) on the second doped semiconductor layer 5 and a second doped sub-layer 11 of the first conductivity type (P-type) on the first doped sub-layer 9;
forming (Figs. 11, paragraph 0115) a plurality of memory cells 19/21/23 based on a phase-change material 21 each on top of a respective island; and silicon
forming a bipolar transistor from the first doped semiconductor layer 1, 2, the second doped semiconductor layer 5, and the second doped sub-layer 11 of the islands (as identified in Fig. 5A, paragraph 0078).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
As far as claims are understood, Claims 5, 7-10, and 22-23 are rejected under 35 U.S.C. 103 as being unpatentable over Cho in view of Lung et al. (US 2010/0181649).
In re Claim 5, Cho teaches the method according to Claim 1 as cited above, but does not teach that trenches are formed in the second and third layers, between the islands, in a direction of the rows (e.g., “between projections of the island”, in accordance with the claim interpretation).
Lung teaches (Fig. 2A) trenches 230 (paragraph 0038) formed in doped second 130 (paragraph 0027) and third 205 (paragraph 0038) semiconductor layers between projections of islands 220 (paragraph 0039) in a direction of a row.
Cho and Lung teach analogous arts directed to methods of formation memory-related devices comprised semiconductor islands, and one of ordinary skill in the art before the effective date of filing the application would have had a reasonable expectation of success in modifying the Cho device and method in view of the Lung teaching, since they are from the same field of endeavor, and Lung created a successfully operated device.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Cho device and method per Lung by creating trenches in the second and third doped semiconductor layers between projections of the islands, wherein such modification is desirable for providing better electrical separations between parts related to different memory cells.
In re Claim 7, Cho teaches the method according to Claim 1 as shown above, but does not teach that the first layer (in which islands are created) is made of silicon – only portions 9 and 11 of layer 7, 9, 11 are made from silicon (paragraph 0108), while portion 7 is formed from a dielectric (paragraph 0107).
Lung teaches (Figs. 7A-10; see also Fig. 12 A) forming islands 220 (paragraph 0039) from a first layer 700 (0072).
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Cho method by creating the first layer from silicon, per Lung, when the Lung’ method steps of creating islands are preferable.
In re Claim 8, Cho teaches the method according to Claim 7 (e.g., Claim 1, in accordance with the claim interpretation) as cited above, including the first layer (from which the islands are created), but does not teach that the first layer is made of polysilicon and is formed by deposition – Cho teaches that only parts 9 and 11 of layer 7, 9, 11 are formed from silicon (paragraph 0108), while portion 7 is formed from an insulator (paragraph 0107).
Lung teaches (Figs. 7A-10; see also Fig. 12 A) forming islands 220 (paragraph 0039) from a first layer 700 being polysilicon (0072).
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Cho method by creating the first layer from polysilicon, per Lung, when the Lung’ method steps of creating islands are preferable and when such material for the first layer is desirable: See MPEP 2144.07 Art Recognized Suitability for an Intended Purpose: The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945) See also Ryco, Inc. v. Ag-Bag Corp., 857 F.2d 1418, 8 USPQ2d 1323 (Fed. Cir. 1988).
In re Claim 9, Cho/Lung teaches the method according to Claim 8 as cited above.
Cho further teaches (Figs. 6-9) that forming the islands 9, 11 includes (as shown in Figs. 7-8) forming gates of MOS transistors of a logic circuit 285 (paragraphs 0037, 0073) wherein the islands and memory cells are formed in a memory area 280 of the chip (paragraph 0037), the chip further including a logic area 285.
In re Claim 10, Cho/Lung teaches the method according to Claim 7, wherein the first layer is made of single-crystal silicon (as shown for Claim 7) and is formed by epitaxy (paragraph 0108).
In re Claim 22, Cho teaches the method of Claim 21, including islands, but does not teach that each island is laterally surrounded with electrically-insulating spacers.
Lung teaches (Fig. 2A) islands 220 (paragraph 0039), each surrounded with corresponding electrically-insulating spacers 260 (paragraphs 0042, 0053).
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Cho device and method by substituting each of the island without a spacer with a similar constructed island, but being surrounded with a corresponding spacer, if such modification is desired by the manufacturer: See MPEP 2144.05 and MPEP 2143 on a Conclusion of Obviousness: KSR Rational (B): Simple Substitution of One Known Element for Another to Obtain Predictable Results.
In re Claim 23, Cho teaches the method of Claim 21 as cited above and wherein the first 9 and second 11 doped sub-layers (Figs. 10) are made of a crystalline semiconductor (paragraph 0073). Cho does not teach that the fist and second doped sub-layers are made from polysilicon.
Lung teaches that his doped pillar 220 (Fig. 2A) is made from polysilicon (paragraph 0039.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Cho device and the method of Claim 21 by creating the first and second doped sub-layers from polysilicon (per Lung), if such material is preferred for the manufacturer: See MPEP 2144.07 Art Recognized Suitability for an Intended Purpose: The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945) See also Ryco, Inc. v. Ag-Bag Corp., 857 F.2d 1418, 8 USPQ2d 1323 (Fed. Cir. 1988).
As far as claims are understood, Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Cho in view of Weber et al. (US 2017/0271325).
In re Claim 24, Cho teaches the method of Claim 21 as cited above and further teaches that the first 9 and second 11 (Figs. 10) doped sub-layers are made of single-crystal semiconductor (paragraph 0109). Cho does not teach that this single-crystal material is silicon.
Weber teaches (Fig. 11, paragraphs 0044-0045) that first 114 and second 116 doped sublayers are made from crystalline (due to epitaxial growth) silicon.
Cho and Weber teach analogous arts directed to method of manufacturing memory devices comprised doped sub-layers, and one of ordinary skill in the art before the effective date of filing the application would have had a reasonable expectation of success in modifying the Cho device and method in view of the Weber device and method, since they are from the same field of endeavor, and Weber created a successfully operated device.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Cho device and method by choosing as its single crystal semiconductors for the first and second sub-layers – silicon – per Weber, in order to enable creation of the first and second sub-layers. In addition, see MPEP 2144.07 Art Recognized Suitability for an Intended Purpose: The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945) See also Ryco, Inc. v. Ag-Bag Corp., 857 F.2d 1418, 8 USPQ2d 1323 (Fed. Cir. 1988).
Allowable Subject Matter
Claims 15, 16, 18, and 19 are allowed.
Claim 2, as interpreted, contains allowable subject matter, while Claims 3-4 depend on Claim 2.
Reason for Identification Allowable Subject Matter
Re Claim 15: Such combination of prior arts of record as earlier cited Cho and Lung make obvious most limitations of Claim 15, except for limitation: “forming a layer of semiconductor material between the islands after forming the electrically insulating spacers”. Other prior arts of record, including the earlier cited Weber, as well as Lung et al. (US 2010/0176362), Yi et al. (US 2006/0118913), Hebert et al. (US 6,365447), Boivin et al. (US 2019/0312088), Zanderighi et al. (US 2011/0001114), or Chang (KR 20100036450) – do not compensate for the above deficiency.
Re Claims 16, 18, and 19: Claims 16, 18, and 19 are allowed due to dependency on Claim 15.
Re Claim 2. The prior arts of record, alone or in combination, fail(s) to anticipate or render obvious such limitation of Claim 2 as: “forming a fourth semiconductor layer between the islands of the first layer with an epitaxial growth process”, in combination with all limitations of Claim 1, on which Claim 2 depends.
Conclusion
Any inquiry concerning this communication should be directed to GALINA G YUSHINA whose telephone number is 571-270-7440. The Examiner can normally be reached between 8 AM - 7 PM Pacific Time (Flexible). Examiner interviews are available. To schedule an interview, Applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s Supervisor, Lynne Gurley can be reached on 571-272-1670.
The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300; a fax phone number of Galina Yushina is 571-270-8440.
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/GALINA G YUSHINA/Primary Patent Examiner, Art Unit 2811, TC 2800,
United States Patent and Trademark Office
E-mail: galina.yushina@USPTO.gov
Phone: 571-270-7440
Date: 04/10/26
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