DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character “d1” has been used to designate both “a first distance d1 in the second direction Dy between the first opening end portion 17e1 and the first end portion 3e1” and “a first distance d1 is defined as a distance in the second direction Dy between a first opening end portion 20e1 of the opening 20 and a first end portion 3e1”.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character “d2” has been used to designate both “a second distance d2 in the second direction Dy between the second opening end portion 17e2 and the second end portion 3e2” and “a second distance d2 is defined as a distance in the second direction Dy between a second opening end portion 20e2 of the opening 20 and a second end portion 3e2”.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
In ¶ [0006]: “on an other end side” should read --on another end side--.
In ¶ [0007]: “on an other end side” should read --on another end side--.
Appropriate correction is required.
Claim Objections
Claim 1 is objected to because of the following informalities:
In line 15: “on an other end side” should read --on another end side--.
Claim 3 is objected to because of the following informalities:
In line 15: “on an other end side” should read --on another end side--.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6-8, 14-16, and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Kurokawa et al. (US 20190172773 A1) herein after “Kurokawa773” in view of Kurokawa et al. (US 20190267479 A1) herein after “Kurokawa479”.
Regarding claim 1, Figs. 1, 3, and 9 of Kurokawa773 disclose a semiconductor device (Fig. 9, semiconductor chip 70, ¶ [0117]) comprising:
a semiconductor substrate (Fig. 3, substrate 30, ¶ [0057]);
at least one first transistor (Fig. 1, plural unit transistors 60, ¶ [0052]) that is on the semiconductor substrate (30) and has a mesa structure (Fig. 3, “Each mesa is constituted by the collector layer 32, the base layer 33, and the emitter layer 34 stacked on each other”, ¶ [0058]) including one or more semiconductor layers;
a wire layer (Fig. 3, wiring E1, ¶ [0054]) that covers the mesa structure (32-34);
an insulating film (Fig. 3, insulating film 52, ¶ [0066]) that covers the wire layer (E1) and has an opening (Fig. 3, cavities 45, ¶ [0055]) in a region that overlaps at least the mesa structure (32-34);
a first bump (Fig. 3, pillar bump 40, ¶ [0055]) that overlaps the at least one first transistor (60), is electrically connected to the wire layer (E1) through the opening (45) (Fig. 3, “The pillar bump 40 is electrically connected to the second-layer emitter wiring E2 via plural cavities 45”, “The second-layer emitter wiring E2 is connected to the first-layer emitter wiring E1”, ¶ [0055] and [0065], and extends in a first direction (X) parallel with the semiconductor substrate (30) (shown in Figs. 2 and 4A); and
a second bump (Fig. 9 shows pillar bumps 81 and 82, which correspond to the first and second bumps respectively) that is in a second direction (Y) orthogonal to the first direction (X) and extends in the first direction (X),
wherein
the mesa structure (32-34) has a first end portion (right side of 32-34 in Fig. 3) on one end side in the second direction (Y) and a second end portion (left side of 32-34 in Fig. 3) on an other end side in the second direction (Y), and the first end portion (right side of 32-34 in Fig. 3) is closer to the second bump (82) than the second end portion (left side of 32-34 in Fig. 3) in the second direction (Y),
the opening (45) has a first opening end portion (right side of 45 in Fig. 3, top of 45 in Fig. 10A) and a second opening end portion (left side of 45 in Fig. 3, bottom of 45 in Fig. 10A) that are adjacent in the second direction (Y), and in plan view in a direction perpendicular to the semiconductor substrate (30), the first opening end portion (right side of 45 in Fig. 3, top of 45 in Fig. 10A) is closer to the second bump (82) than the second opening end portion (left side of 45 in Fig. 3, bottom of 45 in Fig. 10A).
Kurokawa773 fails to disclose the first end portion and the second end portion of the mesa structure are between the first opening end portion and the second opening end portion, and
a first distance in the second direction between the first opening end portion and the first end portion of the mesa structure is larger than a second distance in the second direction between the second opening end portion and the second end portion of the mesa structure in plan view in the direction perpendicular to the semiconductor substrate.
In the similar field of endeavor of semiconductor devices, Fig. 16 of Kurokawa479 discloses the first end portion (see Annotation 1, Fig. 16 of Kurokawa479, P1) and the second end portion (see Annotation 1, Fig. 16 of Kurokawa479, P2) of the mesa structure (Fig. 16, collector layers 33, base layers 34, emitter layers 35, ¶ [0032]) are between the first opening end portion (see Annotation 1, Fig. 16 of Kurokawa479, OP1) and the second opening end portion (see Annotation 1, Fig. 16 of Kurokawa479, OP2), and
a first distance (see Annotation 1, Fig. 16 of Kurokawa479, d1) in the second direction between the first opening end portion (OP1) and the first end portion (P1) of the mesa structure (33-35) is larger than a second distance (see Annotation 1, Fig. 16 of Kurokawa479, d2) in the second direction between the second opening end portion (OP2) and the second end portion (P2) of the mesa structure (33-35) in plan view in the direction perpendicular to the semiconductor substrate (Fig. 16, semiconductor substrate 31, ¶ [0031]).
PNG
media_image1.png
674
746
media_image1.png
Greyscale
Annotation 1, Fig. 16 of Kurokawa479
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the semiconductor device of Kurokawa773 with the arrangement as disclosed by Kurokawa479, to improve reliability (see Kurokawa, ¶ [0123]).
Regarding claim 2, Kurokawa773 and Kurokawa479 together disclose the semiconductor device according to claim 1 as applied above, and Figs. 3, 9, and 10A of Kurokawa773 further disclose wherein
in plan view in the direction perpendicular to the semiconductor substrate (30), an outer circumference of the first bump (81) has a first side (top of 81 in Fig. 9) and a second side (left side of 45 in Fig. 3, bottom of 45 in Fig. 10A) that extend in the first direction (X) and are adjacent in the second direction (Y), and the first side (top of 81 in Fig. 9) is closer to the second bump (82) than the second side (left side of 45 in Fig. 3, bottom of 45 in Fig. 10A) in the second direction (Y), and
a distance between an end portion (bottom of 30 in Fig. 9) closer to the first bump (81) than the second bump (82) among end portions of the semiconductor substrate (30) in the second direction (Y) and the first side (top of 81 in Fig. 9) is larger than a distance between the end portion (bottom of 30 in Fig. 9) and the second side (left side of 45 in Fig. 3, bottom of 45 in Fig. 10A).
Regarding claim 3, Figs. 1, 3, and 9 of Kurokawa773 disclose a semiconductor device (70) comprising:
a semiconductor substrate (30);
at least one transistor (60) that is on the semiconductor substrate (30) and has a mesa structure (32-34) including one or more semiconductor layers (32, 33);
a wire layer (E1) that covers the mesa structure (32-34);
an insulating film (52) that covers the wire layer (E1) and has an opening (45) in a region that overlaps at least the mesa structure (32-34),
a first bump (81) that overlaps the at least one transistor (60), is electrically connected to the wire layer (E1) through the opening (45), and extends in a first direction (X) parallel to the semiconductor substrate (30); and
a second bump (82) that is at a position opposite to the first bump (81) across a centroid (CE) of the semiconductor substrate (30),
wherein
the mesa structure (32-34) has a first end portion (right side of 32-34 in Fig. 3) on one end side in a second direction (Y) orthogonal to the first direction (X) and a second end portion (left side of 32-34 in Fig. 3) on an other end side in the second direction (Y), and the first end portion (right side of 32-34 in Fig. 3) is closer to the centroid (CE) of the semiconductor substrate (30) than the second end portion (left side of 32-34 in Fig. 3) in the second direction (Y),
in plan view in a direction perpendicular to the semiconductor substrate (30), an outer circumference of the first bump (81) has a first side (top of 81 in Fig. 9) and a second side (left side of 45 in Fig. 3, bottom of 45 in Fig. 10A) that extend in the first direction (X) and are adjacent in the second direction (Y) and the first side (top of 81 in Fig. 9) is closer to the centroid (CE) of the semiconductor substrate (30) than the second side (left side of 45 in Fig. 3, bottom of 45 in Fig. 10A) in the second direction (Y),
the opening (45) has a first opening end portion (right side of 45 in Fig. 3, top of 45 in Fig. 10A) and a second opening end portion (left side of 45 in Fig. 3, bottom of 45 in Fig. 10A) that are adjacent in the second direction (Y).
Kurokawa773 fails to disclose in plan view in the direction perpendicular to the semiconductor substrate, the first opening end portion is between the first end portion of the mesa structure, and the first side and the second opening end portion is between the second end portion of the mesa structure and the second side, and
a first distance in the second direction between the first opening end portion and the first end portion of the mesa structure is larger than a second distance in the second direction between the second opening end portion and the second end portion of the mesa structure in plan view in the direction perpendicular to the semiconductor substrate.
In the similar field of endeavor of semiconductor devices, Fig. 16 of Kurokawa479 discloses in plan view in the direction perpendicular to the semiconductor substrate (31), the first opening end portion (OP1) is between the first end portion (P1) of the mesa structure (33-35), and the first side (see Annotation 1, Fig. 16 of Kurokawa479, S1) and the second opening end portion (OP2) is between the second end portion (P2) of the mesa structure (33-35) and the second side (see Annotation 1, Fig. 16 of Kurokawa479, S2), and
a first distance (d1) in the second direction between the first opening end portion (OP1) and the first end portion (P1) of the mesa structure (33-35) is larger than a second distance (d2) in the second direction between the second opening end portion (OP2) and the second end portion (P2) of the mesa structure (33-35) in plan view in the direction perpendicular to the semiconductor substrate (31).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the semiconductor device of Kurokawa773 with the arrangement as disclosed by Kurokawa479, to improve reliability (see Kurokawa, ¶ [0123]).
Regarding claim 4, Kurokawa773 and Kurokawa479 together disclose the semiconductor device according to claim 1 as applied above, and Fig. 3 of Kurokawa773 further discloses comprising:
a collector layer (Fig. 3, collector layer 32, ¶ [0051]) on the semiconductor substrate (30);
a base layer (Fig. 3, base layer 33, ¶ [0051]) on the collector layer (32); and
an emitter layer (Fig. 3, emitter layer 34, ¶ [0051]) on the base layer (33),
wherein the mesa structure (32-34) includes at least a part of the collector layer (32) and the base layer (33) (Fig. 3, “Each mesa is constituted by the collector layer 32, the base layer 33, and the emitter layer 34 stacked on each other”, ¶ [0058]).
Regarding claim 6, Kurokawa773 and Kurokawa479 together disclose the semiconductor device according to claim 1 as applied above, and Fig. 9 of Kurokawa773 further discloses comprising:
at least one second transistor (Fig. 9, transistor Q2, ¶ [0113]) that is on the semiconductor substrate (30) and has a mesa structure (32-34) including one or more semiconductor layers (32, 33) (Fig. 9, “The transistors Q1 and Q2 are each formed such that the plural unit transistors 60”, ¶ [0113]),
wherein the second bump (82) overlaps the at least one second transistor (Q2).
Regarding claim 7, Kurokawa773 and Kurokawa479 together disclose the semiconductor device according to claim 2 as applied above, and Fig. 3 of Kurokawa773 further discloses comprising:
a collector layer (32) on the semiconductor substrate (30);
a base layer (33) on the collector layer (32); and
an emitter layer (34) on the base layer (33),
wherein the mesa structure (32-34) includes at least a part of the collector layer (32) and the base layer (33) (Fig. 3, “Each mesa is constituted by the collector layer 32, the base layer 33, and the emitter layer 34 stacked on each other”, ¶ [0058]).
Regarding claim 8, Kurokawa773 and Kurokawa479 together disclose the semiconductor device according to claim 3 as applied above, and Fig. 3 of Kurokawa773 further discloses comprising:
a collector layer (32) on the semiconductor substrate (30);
a base layer (33) on the collector layer (32); and
an emitter layer (34) on the base layer (33),
wherein the mesa structure (32-34) includes at least a part of the collector layer (32) and the base layer (33) (Fig. 3, “Each mesa is constituted by the collector layer 32, the base layer 33, and the emitter layer 34 stacked on each other”, ¶ [0058]).
Regarding claim 14, Kurokawa773 and Kurokawa479 together disclose the semiconductor device according to claim 2 as applied above, and Fig. 9 of Kurokawa773 further discloses comprising:
at least one second transistor (Q2) that is on the semiconductor substrate (30) and has a mesa structure (32-34) including one or more semiconductor layers (32, 33),
wherein the second bump (82) overlaps the at least one second transistor (Q2).
Regarding claim 15, Kurokawa773 and Kurokawa479 together disclose the semiconductor device according to claim 3 as applied above, and Fig. 9 of Kurokawa773 further discloses comprising:
at least one second transistor (Q2) that is on the semiconductor substrate (30) and has a mesa structure (32-34) including one or more semiconductor layers (32, 33),
wherein the second bump (82) overlaps the at least one second transistor (Q2).
Regarding claim 16, Kurokawa773 and Kurokawa479 together disclose the semiconductor device according to claim 4 as applied above, and Fig. 9 of Kurokawa773 further discloses comprising:
at least one second transistor (Q2) that is on the semiconductor substrate (30) and has a mesa structure (32-34) including one or more semiconductor layers (32, 33),
wherein the second bump (82) overlaps the at least one second transistor (Q2).
Regarding claim 18, Kurokawa773 and Kurokawa479 together disclose the semiconductor device according to claim 7 as applied above, and Fig. 9 of Kurokawa773 further discloses comprising:
at least one second transistor (Q2) that is on the semiconductor substrate (30) and has a mesa structure (32-34) including one or more semiconductor layers (32, 33),
wherein the second bump (82) overlaps the at least one second transistor (Q2).
Regarding claim 19, Kurokawa773 and Kurokawa479 together disclose the semiconductor device according to claim 8 as applied above, and Fig. 9 of Kurokawa773 further discloses comprising:
at least one second transistor (Q2) that is on the semiconductor substrate (30) and has a mesa structure (32-34) including one or more semiconductor layers (32, 33),
wherein the second bump (82) overlaps the at least one second transistor (Q2).
Claims 5, 9-13, 17, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kurokawa773 (US 20190172773 A1) and Kurokawa479 (US 20190267479 A1) in further view of Tajima et al. (JP 2007073611 A) herein after “Tajima”.
Regarding claim 5, Kurokawa773 and Kurokawa479 together disclose the semiconductor device according to claim 1 as applied above, but the combination fails to disclose wherein
the insulating film is an organic protection film including an organic material.
In the similar field of endeavor of semiconductor devices, Fig. 16 of Tajima discloses wherein
the insulating film (Fig. 16, insulating film (protective film, protective resin film) 61, ¶ [0086]) is an organic protection film including an organic material (Fig. 16, “the insulating film 61 as a surface protection film…using an organic insulating film such as polyimide resin as the top insulating film 61”, ¶ [0086]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the insulating film of Kurokawa773 with organic material as disclosed by Tajima, to make the chip easier to handle during manufacturing (see Tajima, ¶ [0086]), and/or the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Regarding claim 9, Kurokawa773 and Kurokawa479 together disclose the semiconductor device according to claim 2 as applied above, but the combination fails to disclose wherein
the insulating film is an organic protection film including an organic material.
In the similar field of endeavor of semiconductor devices, Fig. 16 of Tajima discloses wherein
the insulating film (61) is an organic protection film including an organic material (Fig. 16, “the insulating film 61 as a surface protection film…using an organic insulating film such as polyimide resin as the top insulating film 61”, ¶ [0086]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the insulating film of Kurokawa773 with organic material as disclosed by Tajima, to make the chip easier to handle during manufacturing (see Tajima, ¶ [0086]), and/or the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Regarding claim 10, Kurokawa773 and Kurokawa479 together disclose the semiconductor device according to claim 3 as applied above, but the combination fails to disclose wherein
the insulating film is an organic protection film including an organic material.
In the similar field of endeavor of semiconductor devices, Fig. 16 of Tajima discloses wherein
the insulating film (61) is an organic protection film including an organic material (Fig. 16, “the insulating film 61 as a surface protection film…using an organic insulating film such as polyimide resin as the top insulating film 61”, ¶ [0086]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the insulating film of Kurokawa773 with organic material as disclosed by Tajima, to make the chip easier to handle during manufacturing (see Tajima, ¶ [0086]), and/or the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Regarding claim 11, Kurokawa773 and Kurokawa479 together disclose the semiconductor device according to claim 4 as applied above, but the combination fails to disclose wherein
the insulating film is an organic protection film including an organic material.
In the similar field of endeavor of semiconductor devices, Fig. 16 of Tajima discloses wherein
the insulating film (61) is an organic protection film including an organic material (Fig. 16, “the insulating film 61 as a surface protection film…using an organic insulating film such as polyimide resin as the top insulating film 61”, ¶ [0086]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the insulating film of Kurokawa773 with organic material as disclosed by Tajima, to make the chip easier to handle during manufacturing (see Tajima, ¶ [0086]), and/or the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Regarding claim 12, Kurokawa773 and Kurokawa479 together disclose the semiconductor device according to claim 7 as applied above, but the combination fails to disclose wherein
the insulating film is an organic protection film including an organic material.
In the similar field of endeavor of semiconductor devices, Fig. 16 of Tajima discloses wherein
the insulating film (61) is an organic protection film including an organic material (Fig. 16, “the insulating film 61 as a surface protection film…using an organic insulating film such as polyimide resin as the top insulating film 61”, ¶ [0086]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the insulating film of Kurokawa773 with organic material as disclosed by Tajima, to make the chip easier to handle during manufacturing (see Tajima, ¶ [0086]), and/or the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Regarding claim 13, Kurokawa773 and Kurokawa479 together disclose the semiconductor device according to claim 8 as applied above, but the combination fails to disclose wherein
the insulating film is an organic protection film including an organic material.
In the similar field of endeavor of semiconductor devices, Fig. 16 of Tajima discloses wherein
the insulating film (61) is an organic protection film including an organic material (Fig. 16, “the insulating film 61 as a surface protection film…using an organic insulating film such as polyimide resin as the top insulating film 61”, ¶ [0086]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the insulating film of Kurokawa773 with organic material as disclosed by Tajima, to make the chip easier to handle during manufacturing (see Tajima, ¶ [0086]), and/or the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Regarding claim 17, Kurokawa773, Kurokawa479 and Tajima together disclose the semiconductor device of claim 5 as applied above, and Fig. 9 of Kurokawa773 further discloses comprising:
at least one second transistor (Q2) that is on the semiconductor substrate (30) and has a mesa structure (32-34) including one or more semiconductor layers (32, 33),
wherein the second bump (82) overlaps the at least one second transistor (Q2).
Regarding claim 20, Kurokawa773, Kurokawa479 and Tajima together disclose the semiconductor device of claim 9 as applied above, and Fig. 9 of Kurokawa773 further discloses comprising:
at least one second transistor (Q2) that is on the semiconductor substrate (30) and has a mesa structure (32-34) including one or more semiconductor layers (32, 33),
wherein the second bump (82) overlaps the at least one second transistor (Q2).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CORALIE NETTLES whose telephone number is (571)270-5374. The examiner can normally be reached Mon-Fri. 7:30am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara J Green can be reached at (571) 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/C.A.N./Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893