DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to Applicant's amendments filed May 4, 2026. Claims 1, 3, 5, 9-13, and 16 have been amended. No claims have been added. No claims have been canceled. Currently, claims 1-20 are pending.
Applicant’s Amendments to the drawings overcome the drawing objection outlined in the previous Office Action. The drawing objection has been withdrawn.
Applicant’s Amendments to the specification overcome the specification objections outlined in the previous Office Action. The specification objections have been withdrawn.
Applicant’s Amendments to the claims overcome the claim objections outlined in the previous Office Action. The claim objections have been withdrawn.
Response to Arguments
Applicant’s arguments with respect to claims 1 and 3 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shibata et al. (US 20190006306 A1) herein after “Shibata”.
Regarding claim 1, Figs. 1-2, and 12 of Shibata disclose a semiconductor device (Figs. 1-2, semiconductor chip 100A, ¶ [0044]) comprising:
a semiconductor substrate (Fig. 2, semiconductor substrate 10, ¶ [0040]);
at least one first transistor (Fig. 2, transistor 21e, ¶ [0041]) that is on the semiconductor substrate (10) and has a mesa structure (Fig. 12, “The base layer 80 and the emitter layer 81 are formed in the shape of a mesa”, ¶ [0087]) including one or more semiconductor layers (80, 81);
a wire layer (Fig. 12, electrode 23b, ¶ [0041]) that covers the mesa structure (80, 81);
a first insulating film (Fig. 12, insulating layers 41, ¶ [0042]) that covers the wire layer (23b), wherein the first insulating film comprises an inorganic material (“the insulating layer 41 contains SiN”, ¶ [0042]);
a second insulating film (Fig. 12, insulating layers 42, ¶ [0042]) that covers the first insulating film (41) and has an opening (Fig. 9C, cavity 43b, ¶ [0043]) in a region that overlaps at least the mesa structure (80, 81);
a first bump (Fig. 2, pillar bump 30b, ¶ [0040]) that overlaps the at least one first transistor (21e), is electrically connected to the wire layer (23b) through the opening (43b), and extends in a first direction (vertical in Fig. 1) parallel with the semiconductor substrate (10); and
a second bump (Fig. 2, pillar bump 30a, ¶ [0040]) that is in a second direction (horizontal in Fig. 1) orthogonal to the first direction (vertical in Fig. 1) and extends in the first direction (vertical in Fig. 1),
wherein
the mesa structure (80, 81) has a first end portion (see Annotation 1, Fig. 12 of Shibata, P1) on one end side in the second direction (horizontal in Fig. 1) and a second end portion (see Annotation 1, Fig. 12 of Shibata, P2) on another end side in the second direction (horizontal in Fig. 1), and the first end portion (P1) is closer to the second bump (30a) than the second end portion (P2) in the second direction (horizontal in Fig. 1),
the opening (43b) has a first opening end portion (see Annotation 1, Fig. 12 of Shibata, OP1) and a second opening end portion (see Annotation 1, Fig. 12 of Shibata, OP2) that are adjacent in the second direction (horizontal in Fig. 1), and in plan view in a direction perpendicular to the semiconductor substrate (10), the first opening end portion (OP1) is closer to the second bump (30a) than the second opening end portion (OP2), and
the first end portion (P1) and the second end portion (P2) of the mesa structure (80, 81) are between the first opening end portion (OP1) and the second opening end portion (OP2), and
a first distance (see Annotation 1, Fig. 12 of Shibata, d1) in the second direction (horizontal in Fig. 1) between the first opening end portion (OP1) and the first end portion (P1) of the mesa structure (80, 81) is larger than a second distance (see Annotation 1, Fig. 12 of Shibata, d2) in the second direction (horizontal in Fig. 1) between the second opening end portion (OP2) and the second end portion (P2) of the mesa structure (80, 81) in plan view in the direction perpendicular to the semiconductor substrate (10).
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Annotation 1, Fig. 12 of Shibata
Regarding claim 2, Figs. 1-2, and 12 of Shibata disclose the semiconductor device according to claim 1 as applied above, and Figs. 1 and 12 of Shibata further disclose wherein
in plan view in the direction perpendicular to the semiconductor substrate (10), an outer circumference of the first bump (30b) has a first side (see Annotation 1, Fig. 12 of Shibata, S1) and a second side (see Annotation 1, Fig. 12 of Shibata, S2) that extend in the first direction (vertical in Fig. 1) and are adjacent in the second direction (horizontal in Fig. 1), and the first side (S1) is closer to the second bump (30a) than the second side (S2) in the second direction (horizontal in Fig. 1), and
a distance between an end portion (right side of 42 in Fig. 1) closer to the first bump (30b) than the second bump (30a) among end portions of the semiconductor substrate (10) in the second direction (horizontal in Fig. 1) and the first side (S1) is larger than a distance between the end portion (right side of 42 in Fig. 1) and the second side (S2).
Regarding claim 3, Figs. 1-2, and 12 of Shibata disclose a semiconductor device (100A) comprising:
a semiconductor substrate (10);
at least one transistor (21e) that is on the semiconductor substrate (10) and has a mesa structure (80, 81) including one or more semiconductor layers (80, 81);
a wire layer (23b) that covers the mesa structure (80, 81);
a first insulating film (41) that covers the wire layer (23b), wherein the first insulating film comprises an inorganic material (“the insulating layer 41 contains SiN”, ¶ [0042]);
a second insulating film (42) that covers the first insulating film (41) and has an opening (43b) in a region that overlaps at least the mesa structure (80, 81);
a first bump (30b) that overlaps the at least one transistor (21e), is electrically connected to the wire layer (23b) through the opening (43b), and extends in a first direction (vertical in Fig. 1) parallel to the semiconductor substrate (10); and
a second bump (30a) that is at a position opposite to the first bump (30b) across a centroid (see Annotation 2, Fig. 1 of Shibata, CE) of the semiconductor substrate (10),
wherein
the mesa structure (80, 81) has a first end portion (P1) on one end side in a second direction (horizontal in Fig. 1) orthogonal to the first direction (vertical in Fig. 1) and a second end portion (P2) on another end side in the second direction (horizontal in Fig. 1), and the first end portion (P1) is closer to the centroid (CE) of the semiconductor substrate (10) than the second end portion (P2) in the second direction (horizontal in Fig. 1),
in plan view in a direction perpendicular to the semiconductor substrate (10), an outer circumference of the first bump (30b) has a first side (see Annotation 1, Fig. 12 of Shibata, S1) and a second side (see Annotation 1, Fig. 12 of Shibata, S2) that extend in the first direction (vertical in Fig. 1) and are adjacent in the second direction (horizontal in Fig. 1) and the first side (S1) is closer to the centroid (CE) of the semiconductor substrate (10) than the second side (S2) in the second direction (horizontal in Fig. 1),
the opening (43b) has a first opening end portion (OP1) and a second opening end portion (OP2) that are adjacent in the second direction (horizontal in Fig. 1), and in plan view in the direction perpendicular to the semiconductor substrate (10), the first opening end portion (OP1) is between the first end portion (P1) of the mesa structure (80, 81), and
the first side (S1) and the second opening end portion (OP2) is between the second end portion (P2) of the mesa structure (80, 81) and the second side (S2), and
a first distance (d1) in the second direction (horizontal in Fig. 1) between the first opening end portion (OP1) and the first end portion (P1) of the mesa structure (80, 81) is larger than a second distance (d2) in the second direction (horizontal in Fig. 1) between the second opening end portion (OP2) and the second end portion (P2) of the mesa structure (80, 81) in plan view in the direction perpendicular to the semiconductor substrate (10).
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Annotation 2, Fig. 1 of Shibata
Regarding claim 4, Figs. 1-2, and 12 of Shibata disclose the semiconductor device according to claim 1 as applied above, and Fig. 12 of Shibata further discloses comprising:
a collector layer (“a collector layer (not shown) formed under the base layer 80”, ¶ [0088]) on the semiconductor substrate (10);
a base layer (Fig. 12, base layer 80, ¶ [0086]) on the collector layer (“collector layer”); and
an emitter layer (Fig. 12, emitter layer 81, ¶ [0086]) on the base layer (80),
wherein the mesa structure (80, 81) includes at least a part of the collector layer (“collector layer”) and the base layer (80).
Regarding claim 5, Figs. 1-2, and 12 of Shibata disclose the semiconductor device according to claim 1 as applied above, and Fig. 12 of Shibata further discloses wherein
the second insulating film (42) is an organic protection film (“insulating layers 41 and 42 are sequentially stacked as a protective film”, ¶ [0042]) including an organic material (“The insulating layers 40 through 42 may contain…, polyimide resin”, ¶ [0042]).
Regarding claim 6, Figs. 1-2, and 12 of Shibata disclose the semiconductor device according to claim 1 as applied above, and Fig. 2 of Shibata further discloses comprising:
at least one second transistor (Fig. 2, transistors 21a, ¶ [0041]) that is on the semiconductor substrate (10) and has a mesa structure (80, 81) including one or more semiconductor layers (80, 81),
wherein the second bump (30a) overlaps the at least one second transistor (21a).
Regarding claim 7, Figs. 2, and 12 of Shibata disclose the semiconductor device according to claim 2 as applied above, and Fig. 12 of Shibata further discloses comprising:
a collector layer (“collector layer”) on the semiconductor substrate (10);
a base layer (80) on the collector layer (“collector layer”); and
an emitter layer (81) on the base layer (80),
wherein the mesa structure (80, 81) includes at least a part of the collector layer (“collector layer”) and the base layer (80).
Regarding claim 8, Figs. 1-2, and 12 of Shibata disclose the semiconductor device according to claim 3 as applied above, and Fig. 12 of Shibata further discloses comprising:
a collector layer (“collector layer”) on the semiconductor substrate (10);
a base layer (80) on the collector layer (“collector layer”); and
an emitter layer (81) on the base layer (80),
wherein the mesa structure (80, 81) includes at least a part of the collector layer (“collector layer”) and the base layer (80).
Regarding claim 9, Figs. 2, and 12 of Shibata disclose the semiconductor device according to claim 2 as applied above, and Fig. 12 of Shibata further discloses wherein
the second insulating film (42) is an organic protection film (“insulating layers 41 and 42 are sequentially stacked as a protective film”, ¶ [0042]) including an organic material (“The insulating layers 40 through 42 may contain…, polyimide resin”, ¶ [0042]).
Regarding claim 10, Figs. 1-2, and 12 of Shibata disclose the semiconductor device according to claim 3 as applied above, and Fig. 12 of Shibata further discloses wherein
the second insulating film (42) is an organic protection film (“insulating layers 41 and 42 are sequentially stacked as a protective film”, ¶ [0042]) including an organic material (“The insulating layers 40 through 42 may contain…, polyimide resin”, ¶ [0042]).
Regarding claim 11, Fig. 12 of Shibata disclose the semiconductor device according to claim 4 as applied above, and Fig. 12 of Shibata further discloses wherein
the second insulating film (42) is an organic protection film (“insulating layers 41 and 42 are sequentially stacked as a protective film”, ¶ [0042]) including an organic material (“The insulating layers 40 through 42 may contain…, polyimide resin”, ¶ [0042]).
Regarding claim 12, Fig. 12 of Shibata disclose the semiconductor device according to claim 7 as applied above, and Fig. 12 of Shibata further discloses wherein
the second insulating film (42) is an organic protection film (“insulating layers 41 and 42 are sequentially stacked as a protective film”, ¶ [0042]) including an organic material (“The insulating layers 40 through 42 may contain…, polyimide resin”, ¶ [0042]).
Regarding claim 13, Fig. 12 of Shibata disclose the semiconductor device according to claim 8 as applied above, and Fig. 12 of Shibata further discloses wherein
the second insulating film (42) is an organic protection film (“insulating layers 41 and 42 are sequentially stacked as a protective film”, ¶ [0042]) including an organic material (“The insulating layers 40 through 42 may contain…, polyimide resin”, ¶ [0042]).
Regarding claim 14, Figs. 2, and 12 of Shibata disclose the semiconductor device according to claim 2 as applied above, and Fig. 2 of Shibata further discloses comprising:
at least one second transistor (21a) that is on the semiconductor substrate (10) and has a mesa structure (80, 81) including one or more semiconductor layers (80, 81),
wherein the second bump (30a) overlaps the at least one second transistor (21a).
Regarding claim 15, Figs. 1-2, and 12 of Shibata disclose the semiconductor device according to claim 3 as applied above, and Fig. 2 of Shibata further discloses comprising:
at least one second transistor (21a) that is on the semiconductor substrate (10) and has a mesa structure (80, 81) including one or more semiconductor layers (80, 81),
wherein the second bump (30a) overlaps the at least one second transistor (21a).
Regarding claim 16, Fig. 12 of Shibata disclose the semiconductor device according to claim 4 as applied above, and Fig. 2 of Shibata further discloses comprising:
at least one second transistor (21a) that is on the semiconductor substate and has a mesa structure (80, 81) including one or more semiconductor layers (80, 81),
wherein the second bump (30a) overlaps the at least one second transistor (21a).
Regarding claim 17, Fig. 12 of Shibata disclose the semiconductor device according to claim 5 as applied above, and Fig. 2 of Shibata further discloses comprising:
at least one second transistor (21a) that is on the semiconductor substrate (10) and has a mesa structure (80, 81) including one or more semiconductor layers (80, 81),
wherein the second bump (30a) overlaps the at least one second transistor (21a).
Regarding claim 18, Fig. 12 of Shibata disclose the semiconductor device according to claim 7 as applied above, and Fig. 2 of Shibata further discloses comprising:
at least one second transistor (21a) that is on the semiconductor substrate (10) and has a mesa structure (80, 81) including one or more semiconductor layers (80, 81),
wherein the second bump (30a) overlaps the at least one second transistor (21a).
Regarding claim 19, Fig. 12 of Shibata disclose the semiconductor device according to claim 8 as applied above, and Fig. 2 of Shibata further discloses comprising:
at least one second transistor (21a) that is on the semiconductor substrate (10) and has a mesa structure (80, 81) including one or more semiconductor layers (80, 81),
wherein the second bump (30a) overlaps the at least one second transistor (21a).
Regarding claim 20, Fig. 12 of Shibata disclose the semiconductor device according to claim 9 as applied above, and Fig. 2 of Shibata further discloses comprising:
at least one second transistor (21a) that is on the semiconductor substrate (10) and has a mesa structure (80, 81) including one or more semiconductor layers (80, 81),
wherein the second bump (30a) overlaps the at least one second transistor (21a).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/C.A.N./ Examiner, Art Unit 2893
/YARA B GREEN/ Supervisor Patent Examiner, Art Unit 2893
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