DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claims 4, 5, and 9 – 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 – 3 and 6 – 8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hayashi (US 2019/0295990 A1).
Regarding Claim 1, Hayashi (US 2019/0295990 A1) discloses a semiconductor device (Fig 1-8) comprising: a plurality of first semiconductor elements (5,6) that each have a first electrode (10,16), a second electrode (10,16), and a third electrode (12,18), a switching operation ([0031,0033]) of each of the plurality of first semiconductor elements (5,6) being controlled according to a first drive signal inputted to the third electrode (12,18); a plurality of first connecting members (102,105,106; [0131,0138]) respectively bonded ([0131,0138]) to the second electrodes (10,16) of the plurality of first semiconductor elements; a first detection terminal (end of 21; see callout 21 in Fig 1; [0036]) electrically connected ([0138]) to the second electrodes (10,16) of the plurality of first semiconductor elements; and a first signal wiring section (section of 21 extending in up-down direction of Fig 5; [0122]; note that the claim has not structurally limited nor defined the periphery of this claimed section) electrically interposed between the first detection terminal (end of 21 as seen in Fig 1) and the plurality of first connecting members (106), wherein the plurality of first semiconductor elements (5,6) are aligned (see Fig 5) in a first direction (e.g. 6 is aligned in up-down direction and in the left-right direction) perpendicular to a thickness direction of each of the plurality of first semiconductor elements, and are electrically connected ([0030-0038,0059]; see Fig 5) to each other in parallel ([0030-0038,0059]; see Fig 5), the first signal wiring section includes a plurality of first pad portions (portion or region or part of 21 where 106 interfaces 21; note that the claim has not structurally limited nor defined the periphery of this claimed portion) each located between a different pair of first semiconductor elements (5,6) adjacent to each other in the first direction as viewed in the thickness direction, and each of the plurality of first connecting members (106) is bonded to one of the first pad portions (portion or region of 21) and one of the plurality of first semiconductor elements (6) that is adjacent to the first pad portion as viewed (see Fig 5,7) in the thickness direction.
Regarding Claim 2, Hayashi further discloses the semiconductor device (Fig 1-8) according to claim 1, wherein each of the plurality of first semiconductor elements (5,6) has a first-element obverse surface (surface seen in Fig 5) and a first-element reverse surface (surface not seen in Fig 5 and opposite in the Z-direction to the surface seen in Fig 5) that are spaced apart from each other in the thickness direction (see Fig 8), and the second electrode (10,16) is arranged on the first-element obverse surface (surface seen in Fig 5).
Regarding Claim 3, Hayashi further discloses the semiconductor device (Fig 1-8) according to claim 2, wherein the plurality of first semiconductor elements (5,6) include a pair of first outer elements (6,6 located furthest +Y and located furthest -Y in Fig 5) located at opposite ends (+Y and -Y) in the first direction, and a first inner element (6 located closer to 2) sandwiched between the pair of first outer elements in the first direction, and the first inner element (6) is sandwiched between two of the first pad portions (portion or region or part of 21 where 106 interfaces 21; see Fig 5 showing centrally located 6 is sandwiched by two 106 or two regions at the interface of 106 and 21; note that the claim has not structurally limited nor defined the periphery of this claimed portion) as viewed in the thickness direction, and has two of the plurality of first connecting members (106) bonded thereto.
Regarding Claim 6, Hayashi further discloses the semiconductor device (Fig 1-8) according to claim 2, wherein the first signal wiring section (section of 21 extending in up-down direction of Fig 5; [0122]; note that the claim has not structurally limited nor defined the periphery of this claimed section) includes a first strip portion (portion or region of 21 that extends in Y-direction in Fig 5; note that the claim has not structurally limited nor defined the periphery of this claimed portion) that extends in the first direction (Y-direction) as viewed in the thickness direction, the first strip portion is located in a first sense of a second direction (X-direction) from the plurality of first semiconductor elements, the second direction being perpendicular to the thickness direction and the first direction, and the first pad portions (portion or region or part of 21 where 106 interfaces 21; note that the claim has not structurally limited nor defined the periphery of this claimed portion) overlap with the first strip portion as viewed in the second direction.
Regarding Claim 7, Hayashi further discloses the semiconductor device (Fig 1-8) according to claim 6, wherein the first pad portions (portion or region or part of 21 where 106 interfaces 21; note that the claim has not structurally limited nor defined the periphery of this claimed portion) are integrally formed (21 is shown as an integral structure in Fig 5) with the first strip portion (portion or region of 21 that extends in Y-direction in Fig 5; note that the claim has not structurally limited nor defined the periphery of this claimed portion).
Regarding Claim 8 Hayashi further discloses the semiconductor device (Fig 1-8) according to claim 6, wherein the first detection terminal (end of 21; see callout 21 in Fig 1; [0036]) is located in a first sense (see Fig 5 showing end of 21 is above 5,6 in Y-direction) of the first direction (Y-direction) from the plurality of first semiconductor elements (5,6), the first signal wiring section further includes a first bonding portion to which the first detection terminal is bonded, and the first strip portion is electrically connected to the first bonding portion.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Miyazaki (US 2020/0035656 A1) teaches of a semiconductor device (Fig 3-4) comprising: a plurality of first semiconductor elements (Q1,Q4) that each have a first electrode (electrical interface of Q1,Q4 and SSW1,SSW4 is an electrode), a second electrode (electrical interface of Q1,Q4 and SSW1,SSW4 is an electrode), and a third electrode (electrical interface of Q1,Q4 and SSW1,SSW4 is an electrode); a plurality of first connecting members (SSW1,SSW4) respectively bonded to the second electrodes of the plurality of first semiconductor elements; a first detection terminal (SST1) electrically connected to the second electrodes of the plurality of first semiconductor elements; and a first signal wiring section electrically interposed between the first detection terminal and the plurality of first connecting members. This could be used in a 103 Rejection.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROSHN K VARGHESE whose telephone number is (571)270-7975. The examiner can normally be reached M-Th: 900 am-300 pm.
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/ROSHN K VARGHESE/Primary Examiner, Art Unit 2896
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