DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 12-14 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yu (US 2021/0327778).
Regarding claim 1, Yu discloses, in at least figures 9-12 and related text, a package structure, comprising:
a packaging substrate (96, [46]) having a first surface (lower surface of 96, figures) and a second surface (upper surface of 96, figures) opposite the first surface (lower surface of 96, figures);
a semiconductor device (88, [27]) on the first surface (lower surface of 96, figures) of the packaging substrate (96, [46]) and coupled with the packaging substrate (96, [46]); and
a cap layer (106/108/110/112, [39], [43], [44]) covering the first surface (lower surface of 96, figures) and encapsulating the semiconductor device (88, [27]), wherein the cap layer (106/108/110/112, [39], [43], [44]) and the packaging substrate (96, [46]) have a total thickness (T2/T3, [45], [46]) in a first direction (vertical direction, figures) perpendicular to the first surface (lower surface of 96, figures), and a ratio between a distance (thickness of 110/108, figures) from an upper surface of the cap layer (106/108/110/112, [39], [43], [44]) to an upper surface of the semiconductor device (88, [27]) in the first direction (vertical direction, figures) and the total thickness (T2/T3, [45], [46]) satisfies a first preset value.
Regarding claim 12, Yu discloses the package structure of claim 1 as described above.
Yu discloses, in at least figures 9-12 and related text, a conductive ball (120, [50]) on the second surface (upper surface of 96, figures) and coupled with the semiconductor device (88, [27]).
Regarding claim 13, Yu discloses, in at least figures 9-12 and related text, a memory system (the limitation of "a memory system" has not patentable weight because it is interpreted as intended use), comprising a package structure comprising:
a packaging substrate (96, [46]) having a first surface (lower surface of 96, figures) and a second surface (upper surface of 96, figures) opposite the first surface (lower surface of 96, figures);
a semiconductor device (88, [27]) on the first surface (lower surface of 96, figures) of the packaging substrate (96, [46]) and coupled with the packaging substrate (96, [46]); and
a cap layer (106/108/110/112, [39], [43], [44]) covering the first surface (lower surface of 96, figures) and encapsulating the semiconductor device (88, [27]), wherein the cap layer (106/108/110/112, [39], [43], [44]) and the packaging substrate (96, [46]) have a total thickness (T2/T3, [45], [46]) in a first direction (vertical direction, figures) perpendicular to the first surface (lower surface of 96, figures), and a ratio between a distance (thickness of 110/108, figures) from an upper surface of the cap layer (106/108/110/112, [39], [43], [44]) to an upper surface of the semiconductor device (88, [27]) in the first direction (vertical direction, figures) and the total thickness (T2/T3, [45], [46]) satisfies a first preset value,
wherein the semiconductor device (88, [27]) comprising a memory controller and a memory device coupled thereto ([27]), the memory controller being configured to control the memory device.
Regarding claim 14, Yu discloses, in at least figures 9-12 and related text, a method of fabricating a package structure, comprising:
providing a packaging substrate (96, [46]) having a first surface (lower surface of 96, figures) and a second surface (upper surface of 96, figures) opposite the first surface (lower surface of 96, figures);
disposing a semiconductor device (88, [27]) on the first surface (lower surface of 96, figures) of the packaging substrate (96, [46]) and coupled with the packaging substrate (96, [46]); and
forming a cap layer (106/108/110/112, [39], [43], [44]) covering the first surface (lower surface of 96, figures) and encapsulating the semiconductor device (88, [27]), wherein the cap layer (106/108/110/112, [39], [43], [44]) and the packaging substrate (96, [46]) have a total thickness (T2/T3, [45], [46]) in a first direction (vertical direction, figures) perpendicular to the first surface (lower surface of 96, figures), and a ratio between a distance (thickness of 110/108, figures) from an upper surface of the cap layer (106/108/110/112, [39], [43], [44]) to an upper surface of the semiconductor device (88, [27]) in the first direction (vertical direction, figures) and the total thickness (T2/T3, [45], [46]) satisfies a first preset value.
Regarding claim 20, Yu discloses the method of claim 14 as described above.
Yu discloses, in at least figures 9-12 and related text, forming a conductive ball (120, [50]) on the second surface (upper surface of 96, figures), the conductive ball (120, [50]) being coupled with the semiconductor device (88, [27]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu (US 2021/0327778).
Regarding claim 5, Yu discloses the package structure of claim 1 as described above.
Yu does not explicitly disclose the total thickness of the cap layer and the packaging substrate in the first direction comprises 500 microns to 750 microns.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the total thickness of the cap layer and the packaging substrate as claimed in claim 5 in order to optimize the performance of the device in .. It is noted that the selection dimension of the total thickness of the cap layer and the packaging substrate as being no more than use of known technique to improve similar devices in the same way. See MPEP 2143 I. C. It is noted that if a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond that person's skill. KSR International Co. v. Teleflex Inc., 550 US 398, 82 USPQ2d 1385, 1389 (2007). In Gardnerv.TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
The specification contains no disclosure of either the critical nature of the claimed arrangement (i.e.- the total thickness of the cap layer and the packaging substrate in the first direction comprises 500 microns to 750 microns) or any unexpected results arising therefrom.
Where patentability is said to be based upon particular chosen limitations or upon another variable recited in a claim, the applicant must show that the chosen limitations are critical. In re Woodruff, 919 F.2d 1575, 1578 (FED. Cir. 1990).
Claim(s) 6-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu (US 2021/0327778) in view of Groothuis (US 2013/0119528).
Regarding claim 6, Yu discloses the package structure of claim 1 as described above.
Yu does not explicitly disclose the semiconductor device comprises a plurality of semiconductor dies coupled with each other.
Groothuis teaches, in at least figure 1 and related text, the device comprising the semiconductor device comprises a plurality of semiconductor dies (102, [17]) coupled with each other, for the purpose of reducing the size of die packages to fit within the space constraints of electronic devices ([4]).
Yu and Groothuis are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Yu with the specified features of Groothuis because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Yu to have the semiconductor device comprising a plurality of semiconductor dies coupled with each other, as taught by Groothuis, for the purpose of reducing the size of die packages to fit within the space constraints of electronic devices ([4], Groothuis).
Regarding claim 7, Yu discloses the package structure of claim 1 as described above.
Yu does not explicitly disclose a first semiconductor die comprising a first bonding layer having a plurality of first bonding contacts; and a second semiconductor die comprising a second bonding layer having a plurality of second bonding contacts, wherein the first bonding layer is bonded with the second bonding layer, and the first semiconductor die is coupled with the second semiconductor die through the first bonding contacts and the second bonding contacts.
Groothuis teaches, in at least figure 1 and related text, the device comprising a first semiconductor die (lower 102, [17], figure) comprising a first bonding layer (layer of 114 of top surface of lower 102, figure) having a plurality of first bonding contacts (114, [22]); and a second semiconductor die (upper 102, [17], figure) comprising a second bonding layer (layer of 114 of bottom surface of upper 102, figure) having a plurality of second bonding contacts (114, [22]), wherein the first bonding layer (layer of 114 of top surface of lower 102, figure) is bonded with the second bonding layer (layer of 114 of bottom surface of upper 102, figure), and the first semiconductor die (lower 102, [17], figure) is coupled with the second semiconductor die (upper 102, [17], figure) through the first bonding contacts (114 of lower 102, [22]) and the second bonding contacts (114 of upper 102, [22]), for the purpose of reducing the size of die packages to fit within the space constraints of electronic devices ([4]).
Yu and Groothuis are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Yu with the specified features of Groothuis because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Yu to have the first semiconductor die comprising a first bonding layer having a plurality of first bonding contacts; and the second semiconductor die comprising a second bonding layer having a plurality of second bonding contacts, wherein the first bonding layer is bonded with the second bonding layer, and the first semiconductor die is coupled with the second semiconductor die through the first bonding contacts and the second bonding contacts, as taught by Groothuis, for the purpose of reducing the size of die packages to fit within the space constraints of electronic devices ([4], Groothuis).
Regarding claim 8, Yu in view of Groothuis discloses the package structure of claim 7 as described above.
Groothuis further teaches, in at least figure 1 and related text, a first conductive channel (116, [22]) penetrating through the first semiconductor die (lower 102, [17], figure) and coupled with the first bonding contact (114 of lower 102, [22]), for the purpose of reducing the size of die packages to fit within the space constraints of electronic devices ([4]).
Regarding claim 9, Yu in view of Groothuis discloses the package structure of claim 7 as described above.
Groothuis further teaches, in at least figure 1 and related text, a second conductive channel (116, [22]) penetrating through the second semiconductor die (upper 102, [17], figure) and coupled with the second bonding contact (114 of upper 102, [22]), for the purpose of reducing the size of die packages to fit within the space constraints of electronic devices ([4]).
Claim(s) 10-11 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu (US 2021/0327778) in view of Pagaila (US 2014/0319661).
Regarding claim 10, Yu discloses the package structure of claim 1 as described above.
Yu does not explicitly disclose the cap layer comprises an insulating layer and a conductive layer, wherein the conductive layer encapsulates the insulating layer.
Pagaila teaches, in at least figure 7 and related text, the device comprising the cap layer (180/190/186, [61], [63]) comprises an insulating layer (180, [61]) and a conductive layer (190/186, [63]), wherein the conductive layer (190/186, [63]) encapsulates the insulating layer (180, [61]), for the purpose of isolating semiconductor die from EMI, RFI, and other inter-device interference ([11]).
Yu and Pagaila are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Yu with the specified features of Pagaila because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Yu to have the cap layer comprising an insulating layer and a conductive layer, wherein the conductive layer encapsulates the insulating layer, as taught by Pagaila, for the purpose of isolating semiconductor die from EMI, RFI, and other inter-device interference ([11], Pagaila).
Regarding claim 11, Yu in view of Pagaila discloses the package structure of claim 10 as described above.
The claimed limitation of "a power supply network on the first surface and/or in the packaging substrate, wherein the power supply network is coupled with the semiconductor device" has not patentable weight because it is interpreted as intended use.
Pagaila further teaches, in at least figure 7 and related text, the conductive layer (190/186, [63]) is coupled with a ground line ([65]) in the power supply network, for the purpose of isolating semiconductor die from EMI, RFI, and other inter-device interference ([11]).
Regarding claim 19, Yu discloses the method of claim 14 as described above.
Yu does not explicitly disclose forming an insulating layer covering and encapsulating the semiconductor device; forming a conductive layer encapsulating the insulating layer, wherein the conductive layer is grounded.
Pagaila teaches, in at least figure 7 and related text, the method comprising forming an insulating layer (180, [61]) covering and encapsulating the semiconductor device (124, [42]); forming a conductive layer (190/186, [63]) encapsulating the insulating layer (180, [61]), wherein the conductive layer (190/186, [63]) is grounded ([65]), for the purpose of isolating semiconductor die from EMI, RFI, and other inter-device interference ([11]).
Yu and Pagaila are analogous art because they both are directed to method for forming a semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Yu with the specified features of Pagaila because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method disclosed in Yu to have the forming an insulating layer covering and encapsulating the semiconductor device; the forming a conductive layer encapsulating the insulating layer, wherein the conductive layer is grounded, as taught by Pagaila, for the purpose of isolating semiconductor die from EMI, RFI, and other inter-device interference ([11], Pagaila).
Claim(s) 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu (US 2021/0327778) in view of Kang (US 2015/0279825).
Regarding claim 17, Yu discloses the method of claim 14 as described above.
Yu does not explicitly disclose one semiconductor die or more semiconductor dies coupled with each other, and the method further comprises thinning a substrate of the semiconductor die such that a thickness of the semiconductor device satisfies the first preset value.
Kang teaches, in at least figures 1A-1K and related text, the method comprising one semiconductor die or more semiconductor dies coupled with each other (100/200, [25]), and the method further comprises thinning ([28], [29]) a substrate of the semiconductor die (200, [25]) such that a thickness of the semiconductor device satisfies the first preset value (figures), for the purpose of providing smaller stacking thickness of semiconductor chips thereby being compatible with processing equipments and improving productivity ([100]).
Yu and Kang are analogous art because they both are directed to method for forming a semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Yu with the specified features of Kang because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method disclosed in Yu to have the one semiconductor die or more semiconductor dies coupled with each other, and the method further comprising thinning a substrate of the semiconductor die such that a thickness of the semiconductor device satisfies the first preset value, as taught by Kang, for the purpose of providing smaller stacking thickness of semiconductor chips thereby being compatible with processing equipments and improving productivity ([100], Kang).
Regarding claim 18, Yu discloses the method of claim 14 as described above.
Yu does not explicitly disclose providing a first semiconductor die comprising a first bonding layer having a plurality of first bonding contacts; providing a second semiconductor die comprising a second bonding layer having a plurality of second bonding contacts; bonding the first bonding layer with the second bonding layer, wherein the first semiconductor die is coupled with the second semiconductor die through the first bonding contacts and the second bonding contacts.
Kang teaches, in at least figures 1A-1K and related text, the method comprising providing a first semiconductor die (100, [25]) comprising a first bonding layer (layer 109, figures) having a plurality of first bonding contacts (109, [24]); providing a second semiconductor die (200, [25]) comprising a second bonding layer (layer 209, figures) having a plurality of second bonding contacts (209, [25]); bonding the first bonding layer (layer 109, figures) with the second bonding layer (layer 209, figures), wherein the first semiconductor die (100, [25]) is coupled with the second semiconductor die (200, [25]) through the first bonding contacts (109, [24]) and the second bonding contacts (209, [25]) (figures), for the purpose of providing smaller stacking thickness of semiconductor chips thereby being compatible with processing equipments and improving productivity ([100]).
Yu and Kang are analogous art because they both are directed to method for forming a semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Yu with the specified features of Kang because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method disclosed in Yu to have the providing a first semiconductor die comprising a first bonding layer having a plurality of first bonding contacts; the providing a second semiconductor die comprising a second bonding layer having a plurality of second bonding contacts; the bonding the first bonding layer with the second bonding layer, wherein the first semiconductor die is coupled with the second semiconductor die through the first bonding contacts and the second bonding contacts, as taught by Kang, for the purpose of providing smaller stacking thickness of semiconductor chips thereby being compatible with processing equipments and improving productivity ([100], Kang).
Allowable Subject Matter
Claims 2-4 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 1 and 2 that recite "a pressure strain of the package structure satisfies a second preset value" in combination with other elements of the base claims 1 and 2.
Claims 15-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 14 and 15 that recite "a pressure strain of the package structure satisfies a second preset value" in combination with other elements of the base claims 14 and 15.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
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/TONG-HO KIM/ Primary Examiner, Art Unit 2811