DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1, 2, 4, 6, 8-12, 14-16, 18, and 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 3-5, 8-12, 14, and 16-18 of U.S. Patent No. 11,942,502. Although the claims at issue are not identical, they are not patentably distinct from each other because each of the limitations of the claims of the present application are substantially recite in the corresponding claims of the patent, hence the patent claims would anticipate the application claims.
Regarding claim 1 of the present application, see claims 1 and 3 of the patent.
Regarding claim 2 of the present application, see claim 1 of the patent.
Regarding claim 4 of the present application, see claim 4 of the patent.
Regarding claim 6 of the present application, see claim 5 of the patent.
Regarding claim 8 of the present application, see claim 1 of the patent.
Regarding claim 9 of the present application, see claim 8 and 10 of the patent.
Regarding claim 10 of the present application, see claim 9 of the patent.
Regarding claim 11 of the present application, see claim 8 of the patent.
Regarding claim 12 of the present application, see claim 11 of the patent.
Regarding claim 14 of the present application, see claim 12 of the patent.
Regarding claim 15 of the present application, see claim 14 and 16 of the patent.
Regarding claim 16 of the present application, see claim 14 of the patent.
Regarding claim 18 of the present application, see claim 17 of the patent.
Regarding claim 20 of the present application, see claim 18 of the patent.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4-6, 8-10, 12-16, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kashihara (U.S. Pub #2015/0054110), in view of Hashiguchi et al (U.S. Pub #2020/0105814).
With respect to claim 1, Kashihara teaches a solid-state imaging apparatus, comprising:
a first semiconductor substrate (Fig. 5, SL);
a second semiconductor substrate (Fig. 5, SS), wherein a front surface side of the first semiconductor substrate forms a wiring layer (Fig. 5, MLa) formation surface of the first semiconductor substrate,
wherein the first semiconductor substrate includes :a photoelectric conversion portion (Fig. 5, PD) that photoelectrically converts incident light;
a transfer transistor (Fig. 5, TX) that transfers electric charges of the photoelectric conversion portion; and
a voltage conversion transistor (Fig. 5, undepicted; Fig. 2 AM1 and Paragraph 82) that converts the electric charges transferred by the transfer transistor into a corresponding voltage, and
wherein the second semiconductor substrate includes a charge voltage retention portion (Fig. 5, CD) that retains the corresponding voltage converted by the voltage conversion transistor (Paragraph 83); and
a through electrode (Fig. 5, CT2) that penetrates through the second semiconductor substrate and transmits the corresponding voltage converted by the transfer transistor to the charge voltage retention portion.
Kashihara does not teach
that the wiring layer of the first substrate joins to a back surface side of the second semiconductor substrate which is an opposite side of a wiring layer formation surface of the second semiconductor substrate
a through electrode that penetrates through the second semiconductor substrate.
Hashiguchi teaches that a wiring layer (Figs. 1, 3B, and 4B, 105) of the first substrate (Figs. 1, 3B, and 4B, 110A/101) joins to a back surface side of a second semiconductor substrate (Figs. 1, 3B, and 4B, 110B/121) which is an opposite side of a wiring layer formation surface (Figs. 1, 3B, and 4B, 125) of the second semiconductor substrate
a through electrode (Figs. 1, 3B, and 4B, 157) that penetrates through the second semiconductor substrate.
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to
arrange the second semiconductor substrate of Kashihara such that the first substrate joins to a back surface side of the second semiconductor substrate which is an opposite side of a wiring layer, and to
provide a through electrode that penetrates through the second semiconductor substrate of Kashihara as taught by Hashiguchi in order to improve the performance of the imaging device (Paragraph 255, 282, etc.).
With respect to claim 2, Kashihara teaches a photomask (Fig. 5, LSF1 and Paragraph 98) arranged between the first semiconductor substrate and the second semiconductor substrate, wherein the photomask is formed by a portion of a metal wiring provided within a wiring layer.
With respect to claim 4, Hashiguchi teaches that a cross-sectional diameter of the through electrode (Figs. 1, 3B, and 4B, 157) penetrating both the first semiconductor substrate and the second semiconductor substrate is less than or equal to the cross-sectional diameter of the through electrode penetrating only the second semiconductor substrate.
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to
provide a through electrode as taught by Hashiguchi in order to improve the performance of the imaging device (Paragraph 255, 282, etc.).
With respect to claim 5, Kashihara teaches that the charge voltage retention portion of the second semiconductor substrate includes a capacitor (Fig. 5, CD).
With respect to claim 6, Hashiguchi teaches that the first semiconductor substrate and the second semiconductor substrate are electrically coupled only via (Fig. 8A, 157a) a plurality of the through electrodes provided within a pixel region (Fig. 8A, generally underneath region of 111/113) of the solid-state imaging apparatus.
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to
provide a through electrode as taught by Hashiguchi in order to improve the performance of the imaging device (Paragraph 255, 282, etc.).
With respect to claim 8, Hashiguchi teaches a light blocking film (Fig 8A, wiring portion 143) positioned below the photoelectric conversion portion (Fig. 8A, generally underneath region of 111/113) and above the through electrode (Fig. 8A, 157a) throughout a length of the through electrode in a cross-sectional view. Kashihari also teaches that a metal portion in the wiring layer can be a light blocking film (Fig. 5, LSF2).
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to
provide a through electrode below a light blocking film as taught by Hashiguchi in order to improve the performance of the imaging device (Paragraph 255, 282, etc.).
With respect to claim 9, Kashihara teaches a manufacturing method for a solid-state imaging apparatus, the method comprising:
forming a photoelectric conversion portion (Fig. 5, PD), a transfer transistor (Fig. 5, TX), and a voltage conversion transistor (Fig. 5, undepicted; Fig. 2, AM1 and Paragraph 82) in a first semiconductor substrate (Fig. 5, SL),
wherein the photoelectric conversion portion photoelectrically converts incident light, wherein the transfer transistor transfers electric charges of the photoelectric conversion portion and wherein the voltage conversion transistor converts the electric charges transferred by the transfer transistor into a corresponding voltage (Paragraph 82);
bonding a front surface side of the first semiconductor substrate which is a wiring layer formation surface of the first semiconductor substrate to a back surface side of a second semiconductor substrate (Fig. 5, SS) which is an opposite side of a wiring layer formation surface of the second semiconductor substrate;
forming a charge voltage retention portion (Fig. 5, CD) in the second semiconductor substrate after the bonding, wherein the charge voltage retention portion retains the corresponding voltage converted by the voltage conversion transistor.
Kashihara does not teach
that the wiring layer of the first substrate joins to a back surface side of the second semiconductor substrate which is an opposite side of a wiring layer formation surface of the second semiconductor substrate
a through electrode that penetrates through the second semiconductor substrate.
Hashiguchi teaches that a wiring layer (Figs. 1, 3B, and 4B, 105) of the first substrate (Figs. 1, 3B, and 4B, 110A/101) joins to a back surface side of a second semiconductor substrate (Figs. 1, 3B, and 4B, 110B/121) which is an opposite side of a wiring layer formation surface (Figs. 1, 3B, and 4B, 125) of the second semiconductor substrate
a through electrode (Figs. 1, 3B, and 4B, 157) that penetrates through the second semiconductor substrate.
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to
arrange the second semiconductor substrate of Kashihara such that the first substrate joins to a back surface side of the second semiconductor substrate which is an opposite side of a wiring layer, and to
provide a through electrode that penetrates through the second semiconductor substrate of Kashihara as taught by Hashiguchi in order to improve the performance of the imaging device (Paragraph 255, 282, etc.).
With respect to claim 10, Kashihara teaches that the method further comprises: arranging a photomask (Fig. 5, LSF1) between the first semiconductor substrate and the second semiconductor substrate; and forming the photomask by a portion of a metal wiring provided within a wiring layer.
With respect to claim 12, Hashiguchi teaches that a cross-sectional diameter of the through electrode (Figs. 1, 3B, and 4B, 157) penetrating both the first semiconductor substrate and the second semiconductor substrate is less than or equal to the cross-sectional diameter of the through electrode penetrating only the second semiconductor substrate.
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to
provide a through electrode as taught by Hashiguchi in order to improve the performance of the imaging device (Paragraph 255, 282, etc.).
With respect to claim 13, Hashiguchi teaches that the charge voltage retention portion of the second semiconductor substrate includes a capacitor (Fig. 5, CD).
With respect to claim 14, Hashiguchi teaches that the first semiconductor substrate and the second semiconductor substrate are electrically coupled only via (Fig. 8A, 157a) a plurality of the through electrodes provided within a pixel region (Fig. 8A, generally underneath region of 111/113) of the solid-state imaging apparatus.
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to
provide a through electrode as taught by Hashiguchi in order to improve the performance of the imaging device (Paragraph 255, 282, etc.).
With respect to claim 15, Kashihara teaches an electronic apparatus including a solid-state imaging apparatus, the electronic apparatus comprising:
an optical system (Fig. 27D, 11203);
a solid-state imaging apparatus (Fig. 27E, 11402) that receives light from the optical system,
a digital signal processor (Fig. 27E, 11201) that processes signals received from the solid-state imaging apparatus;
the solid-state imaging apparatus (Fig. 27E, 11402) comprising:
a first semiconductor substrate (Fig. 5, SL);
a second semiconductor substrate (Fig. 5, SS), wherein a front surface side of the first semiconductor substrate forms a wiring layer (Fig. 5, MLa) formation surface of the first semiconductor substrate,
wherein the first semiconductor substrate includes:a photoelectric conversion portion (Fig. 5, PD) that photoelectrically converts incident light;
a transfer transistor (Fig. 5, TX) that transfers electric charges of the photoelectric conversion portion; and
a voltage conversion transistor (Fig. 5, undepicted; Fig. 2 AM1 and Paragraph 82) that converts the electric charges transferred by the transfer transistor into a corresponding voltage, and
wherein the second semiconductor substrate includes a charge voltage retention portion (Fig. 5, CD) that retains the corresponding voltage converted by the voltage conversion transistor (Paragraph 83); and
a through electrode (Fig. 5, CT2) that penetrates through the second semiconductor substrate and transmits the corresponding voltage converted by the transfer transistor to the charge voltage retention portion.
Kashihara does not teach
that the wiring layer of the first substrate joins to a back surface side of the second semiconductor substrate which is an opposite side of a wiring layer formation surface of the second semiconductor substrate
a through electrode that penetrates through the second semiconductor substrate.
Hashiguchi teaches that a wiring layer (Figs. 1, 3B, and 4B, 105) of the first substrate (Figs. 1, 3B, and 4B, 110A/101) joins to a back surface side of a second semiconductor substrate (Figs. 1, 3B, and 4B, 110B/121) which is an opposite side of a wiring layer formation surface (Figs. 1, 3B, and 4B, 125) of the second semiconductor substrate
a through electrode (Figs. 1, 3B, and 4B, 157) that penetrates through the second semiconductor substrate.
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to
arrange the second semiconductor substrate of Kashihara such that the first substrate joins to a back surface side of the second semiconductor substrate which is an opposite side of a wiring layer, and to
provide a through electrode that penetrates through the second semiconductor substrate of Kashihara as taught by Hashiguchi in order to improve the performance of the imaging device (Paragraph 255, 282, etc.).
With respect to claim 16, Kashihara teaches a photomask (Fig. 5, LSF1) arranged between the first semiconductor substrate and the second semiconductor substrate, wherein the photomask is formed by a portion of a metal wiring provided within a wiring layer.
With respect to claim 18, Hashiguchi teaches that a cross-sectional diameter of the through electrode (Figs. 1, 3B, and 4B, 157) penetrating both the first semiconductor substrate and the second semiconductor substrate is less than or equal to the cross-sectional diameter of the through electrode penetrating only the second semiconductor substrate.
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to
provide a through electrode as taught by Hashiguchi in order to improve the performance of the imaging device (Paragraph 255, 282, etc.).
With respect to claim 19, Kashihara teaches that the charge voltage retention portion of the second semiconductor substrate includes a capacitor (Fig. 5, CD).
With respect to claim 20, Hashiguchi teaches that the first semiconductor substrate and the second semiconductor substrate are electrically coupled only via (Fig. 8A, 157a) a plurality of the through electrodes provided within a pixel region (Fig. 8A, generally underneath region of 111/113) of the solid-state imaging apparatus.
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to
provide a through electrode as taught by Hashiguchi in order to improve the performance of the imaging device (Paragraph 255, 282, etc.).
Allowable Subject Matter
Claims 3, 7, 11, and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN P SANDVIK whose telephone number is (571)272-8446. The examiner can normally be reached M-F: 10-6.
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/BENJAMIN P SANDVIK/ Primary Examiner, Art Unit 2812