DETAILED ACTION
This action is responsive to the amendment received on 06/23/2026
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention 2 (claims 14-20) in the reply filed on 03/04/2026 is acknowledged. Claim(s) 1-13 is/are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim.
Priority
Acknowledgment is made of applicant's claim for priority under 35 U.S.C. 119(a)-(d) or (f), 365(a) or (b), or 386(a) based upon an application filed in PEOPLE'S REPUBLIC OF CHINA on 05/30/2023.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 14-20 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 14 and 19 both recite the limitation “the second portion of the contact is in contact with a dielectric layer” near the end of the claims. However, both claims previously recited “a stack structure comprising a plurality of alternate conductive layers and dielectric layers”. Because of the earlier recitation of a plurality of dielectric layers, it is unclear if the singular dielectric layer recited later in the claims should be interpreted as part of the plurality of if it is a separate dielectric layer which is not part of the plurality of dielectric layers in the stack structure. Claim(s) 14 and 19 are therefore rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor, or a joint inventor, regards as the invention. Claims 15-18 and 20 are rejected under 35 U.S.C. 112(b) at least for their dependencies. For the purposes of this examination, the singular dielectric layer may be interpreted as both one of the dielectric layers in the stack structure or a separate dielectric layer not previously recited.
Claim 17 recites the limitation "the plurality of channel structures extends into the semiconductor substrate along a direction, and the stack structure is above the insulation layer along the direction" in lines 3-4. This limitation is unclear in view of the amendments to claim 14, which claim 17 depends on through claim 15. Claim 14 has been amended to recite a first direction and a second direction intersecting with the first direction. Claim 14 requires the stack structure to comprise alternating conductive and dielectric layers along the first direction such that the first direction is interpreted to refer to the vertical direction in Figure 2(s) which is the direction in which the alternating layers of the stack structure #130 are provided. Furthermore, in Figure 2(s), the stack structure (#130) is above the insulation layer (#104) in the vertical direction. It is therefore unclear if there is a relationship between the first/second directions of claim 14, and the direction in claim 17. Claim(s) 17 is therefore rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor, or a joint inventor, regards as the invention. Based on the above interpretations of the figures, it is the examiner’s interpretation that the direction of claim 17 is also intended to be referring to the first direction. For the purposes of this examination, claim 17 will be interpreted to read as “the plurality of channel structures extends into the semiconductor substrate along [[a]] the first direction, and the stack structure is above the insulation layer along the first direction”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 14-17 and 19-20 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by US 2023/0046500 A1; Son, Yonghoon; 02/2023; (“Son”).
Regarding Claim 14. Son discloses A three-dimensional (3D) memory device (#100, Figures 1-4, [0026]-[0029], semiconductor device which may include a memory region according to [0030]), comprising:
a stack structure (Figure 2A, stack of #120s and #130s) comprising a plurality of alternating conductive layers (#130, Figure 2A, gate electrodes) and dielectric layers (#120, Figure 2A, insulating layers) along a first direction (Figure 2A, #120s and #130s are stacked along a first z-direction), the stack structure having a first region (#R1, Figure 2A) and a second region (#R2, Figure 2A) along a second direction intersecting with the first direction (Figure 2A, #R1 and #R2 are respectively adjacent to one another along a second x-direction intersecting the first z-direction);
gate line slit structures (#MS, Figure 2B, separation regions which split the gate electrodes #130) extending through the stack structure along the first direction and dividing the stack structure into a plurality of memory blocks (Figure 2B, [0047], “separation regions MS continuously extending from the first region R1 and the second region R2 of the separation regions MS. The gate electrodes 130 between the separation regions MS may form a single memory block”, i.e. #MS extends through the stack in the first z-direction to divide it into separate blocks); and
a contact (#170, Figure 2A and 3A, plug zoomed in in block A from Figure 2A in Figure 3A) located in the second region (Figure 2A, #170s are located in #R2) and comprising a first portion extending from a surface of the stack structure to a target conductive layer (Figure 3A, a portion of #170 extends from a top surface of a topmost #130 of the stack in the box A to at least a bottom of the topmost #130 being the target) of the conductive layers along the first direction (Figure 3A, the target #130 is one of the many #130s in the stack which the contact extends to in the first z-direction) and a second portion covering part of the surface of the stack structure along the second direction (Figure 3A, a portion of #170 above the stack structure at least partially covers a top surface of the stack structure along the second x-direction),
wherein a material of the first portion and the second portion of the contact is same as a material of the conductive layers ([0158], “the pad region 130P and the contact plug 170 may be formed of the same material”, i.e. the entire #170 including the first and second portions and #130s may be made of a same material), and wherein the second portion of the contact is in contact with a dielectric layer (#190, Figure 2A, cell region insulating layer) in the second region along the first direction (Figures 2A and 3A, the portion of #170 above the stack structure is in contact with #190, in the region #R2, along the z-direction, where this is interpreted as a continuous contact between the two structures as each extends along the z-direction or at a single point of contact in the z-direction due to the tapered shape of the contact).
Regarding Claim 15. Son discloses The 3D memory device of claim 14, further comprising a plurality of channel structures (#CH, Figure 2B, channel structures) extending through the stack structure (Figure 2B, each #CH extends through the stack of #130s and #120s),
wherein each of the plurality of channel structures (#CH) comprises a memory film (#145A, Figure 2B, [0062], #145A may include a memory film structure including a tunneling layer, a charge storage layer, and a blocking layer, matching the description of [0047] in the instant application) and a semiconductor channel (#140, Figure 2B, channel layer formed of a semiconductor material according to [0061]) inwards from an inner surface of the channel structure to a center of the channel structure sequentially (Figure 2B, #140 is on an inner surface of #CH more towards the center of #CH than the memory film #145A).
Regarding Claim 16. Son discloses The 3D memory device of claim 15, further comprising a first connection structure (#185 over the #170 extending through box #A, Figure 2A, upper interconnection connected to #170) and a second connection structure (#185s over #CHs in region #R1, Figure 2A, upper interconnections connected to the channel pads #155 of #CH),
wherein the first connection structure is connected to the contact (Figure 2A, a #185 is directly connected to #170), and the second connection structure is connected to the channel structures (Figure 2A, #185s in the region #R1 are connected to #CHs).
Regarding Claim 17. Son discloses The 3D memory device of claim 15, further comprising a second conductive layer (#102, Figure 2B, first horizontal conductive layer) between a semiconductor substrate (#101, Figure 2B, second substrate) and an insulation layer (bottommost #120 of the stack, Figure 2B, let the bottommost insulating layer #120 be interpreted as an insulation layer separate from the stack structure) (Figure 2B, #102 is between #101 and the bottommost #120),
wherein the plurality of channel structures extends into the semiconductor substrate along [[a]] the first direction (Figure 2B, #CHs extend into #101 along the first z-direction), and the stack structure is above the insulation layer along the first direction (Figure 2B, the stack of #130s and #120s is above the bottommost #120 along the first z-direction), and wherein the second conductive layer is coupled to the semiconductor channel of each of the plurality of channel structures (Figure 2B, #102 is directly electrically coupled to #140 of each #CH).
Regarding Claim 19. Son discloses A memory system (#1000, Figure 13, data storage system), comprising:
a memory device configured to store data (#1100, Figure 13, semiconductor device which may be a memory device for data storage according to [0162]), the memory device comprising ([0162], #1100 may be the device of Figures 1-4):
a stack structure (Figure 2A, stack of #120s and #130s) comprising a plurality of alternate conductive layers (#130, Figure 2A, gate electrodes) and dielectric layers (#120, Figure 2A, insulating layers) along a first direction (Figure 2A, #120s and #130s are stacked along a first z-direction), and having a first region (#R1, Figure 2A) and a second region (#R2, Figure 2A) along a second direction intersecting with the first direction (Figure 2A, #R1 and #R2 are respectively adjacent to one another along a second x-direction intersecting the first z-direction);
gate line slit structures (#MS, Figure 2B, separation regions which split the gate electrodes #130) extending through the stack structure along the first direction and dividing the stack structure into a plurality of memory blocks (Figure 2B, [0047], “separation regions MS continuously extending from the first region R1 and the second region R2 of the separation regions MS. The gate electrodes 130 between the separation regions MS may form a single memory block”, i.e. #MS extends through the stack in the first z-direction to divide it into separate blocks); and
a contact (#170, Figure 2A and 3A, plug zoomed in in block A from Figure 2A in Figure 3A) in the second region (Figure 2A, #170s are located in #R2) and comprising a first portion extending from a surface of the stack structure to a target conductive layer along the first direction (Figure 3A, a portion of #170 extends from a top surface of a topmost #130 of the stack in the box A to at least a bottom of the topmost #130 being the target along the first z-direction) and a second portion covering a part of the surface of the stack structure (Figure 3A, the target #130 is one of the many #130s in the stack) and a second portion covering part of the surface of the stack structure along the second direction (Figure 3A, a portion of #170 above the stack structure at least partially covers a top surface of the stack structure along the second x-direction), wherein the first portion and the second portion of the contact comprise a same material as the conductive layers ([0158], “the pad region 130P and the contact plug 170 may be formed of the same material”, i.e. the entire #170 including the first and second portions and #130s may be made of a same material), and wherein the second portion of the contact is in contact with a dielectric layer (#190, Figure 2A, cell region insulating layer) in the second region along the first direction (Figures 2A and 3A, the portion of #170 above the stack structure is in contact with #190, in the region #R2, along the z-direction, where this is interpreted as a continuous contact between the two structures as each extends along the z-direction or at a single point of contact in the z-direction due to the tapered shape of the contact and insulating layer structures); and
a memory controller (#1200, Figure 13, controller) coupled to the memory device and configured to control the memory device (Figure 13, [0168], #1200 is coupled to #1100 through input/output pads #1101 and controls the memory device).
Regarding Claim 20. Son discloses The memory system of claim 19, further comprising a host coupled to the memory controller and configured to send or receive the data ([0169], “host interface 1230 may provide a communication function between the data storage system 1000 and an external host. When a control command is received from an external host through the host interface 1230”, i.e. an external host is coupled to #1200 and may send or receive data from data from the controller #1200 which is further detailed in [0172]).
Claim(s) 14 and 18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2019/0115358 A1; Lee et al.; 04/2019; (“Lee”). An annotated version of Figure 7I from Lee is provided below and referenced in the following rejection.
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Regarding Claim 14. Lee discloses A three-dimensional (3D) memory device (#10, Figures 1-6, semiconductor device which may be a memory device according to [0009] and wherein Figure 7I is a side view of the completed device), comprising:
a stack structure (#130s and #140s, Figures 3 and 7I, alternating stack of #130s and #140s) comprising a plurality of alternating conductive layers (#130s, Figure 7I, gate electrode layers) and dielectric layers (#140s, Figure 7I, insulating layers) along a first direction (Figure 7I, #130s and #140s are alternately disposed along the first z-direction), the stack structure having a first region (#CA, Figure 3, cell array region) and a second region (#CT, Figure 3, contact region) along a second direction intersecting with the first direction (Figure 7I, #CA and #CT are disposed adjacent to one another along a second y-direction which intersects with the first z-direction);
gate line slit structures (#160 and #160S, Figure 3, conductive lines and their spacers which split the gate electrodes) extending through the stack structure along the first direction and dividing the stack structure into a plurality of memory blocks (Figure 3, [0030] and [0045], #160s are the word line cuts which separate the stack into a plurality of structures or memory blocks by extending through the stack in the first z-direction); and
a contact (#171 of #170s, Figure 7I, contact plug) located in the second region (Figure 7I, #171 is located in the contact region #CT) and comprising a first portion extending from a surface of the stack structure to a target conductive layer of the conductive layers along the first direction (Figure 7I annotated, first portion of #171 extends from a side surface of #142 of #140s in the stack to a target conductive layer #131 of the conductive layers #130 along the first z-direction) and a second portion covering part of the surface of the stack structure along the second direction (Figure 7I annotated, the second portion of #171 covers part of the side surface of #142 along the second y-direction),
wherein a material of the first portion and the second portion of the contact is same as a material of the conductive layers ([0040], “contact plugs 170 may include the same material as a material for forming the gate electrode layers 130”, i.e. all of #171 and #130s include the same material), and wherein the second portion of the contact is in contact with a dielectric layer (#150, Figure 7I, molding insulating layer) in the second region along the first direction (Figure 7I annotated, the second portion of #171 is in contact with #150, in the region #CT, along the z-direction, where this is interpreted as a continuous contact between the two structures as each extends along the z-direction).
Regarding Claim 18. Lee discloses The 3D memory device of claim 14, wherein the gate line slit structures (#160 and #160S) comprise first sub-portions (Figure 3, horizontally extending portions of #160) and second sub-portions (Figure 3, vertically extending portions of #160), and the contact further at least comprises a third portion and a fourth portion (Figure 7I annotated, third and fourth portions of #171), and
wherein a material of the first sub-portions of the gate line slit structures is same as a material of the third portion of the contact, and a material of the second sub-portions of the gate line slit structures is same as the fourth portion of the contact ([0042] and [0102], #160 may be made of tungsten (W) and #170s may also be made of Tungsten (W) such that all portions of #160 and #171 may be made of Tungsten (W)).
Response to Arguments/Amendments
Applicant’s amendments to claims 14, 17, and 19 and corresponding remarks, see page 8 of the remarks, filed 06/23/2026, with respect to the objections to claims 14-20 have been fully considered. The objections to claims 14-20 have been withdrawn.
Applicant’s amendments to claims 14 and 19 along with corresponding arguments, see pages 8-9 of the remarks, filed 06/23/2026, with respect to the 35 U.S.C. 102 rejections of the claims, and their respective dependent claims, in view of US 2023/0046500 A1; Son, Yonghoon; 02/2023; (“Son”) have been fully considered but are not found persuasive. Claim(s) 14-17 and 19-20 stand(s) rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by US 2023/0046500 A1; Son, Yonghoon; 02/2023; (“Son”).
Applicant argues that the amendment to the claims to recite “wherein the second portion of the contact is in contact with a dielectric layer in the second region along the first direction” overcomes the cited prior art because Son fails to disclose that the second portion is in contact with an upper surface of a dielectric layer. Examiner respectfully disagrees.
Examiner first notes that applicant’s amendment to the claims does not appear to match the feature applicant claims is not taught by the cited prior art. The amendment to the claim does not refer to an upper surface of a dielectric layer. The claim amendment requires only that “the second portion of the contact is in contact with a dielectric layer in the second region along the first direction”. In Son, the second portion of the contact (Figure 2A, the portion of #170 passing though box #A that is above the stack structure) is entirely located within the second region (Figure 2A, #R2) and is in direct contact with a dielectric layer (#190, Figure 2A, cell region insulating layer). The phrase “along the first (z-direction) direction” is interpreted by the examiner to encompass two possible meanings, both of which are satisfied by the Son reference. In a first interpretation, because the contact (#170) has a tapered structure, a single line along the z-direction in an upward direction may pass from #190 into #170 such that along a z-direction, there is a point of contact between the second upper portion of the contact (#170) and the dielectric layer (#190). In a second interpretation, the uppermost portion of #170 in Figure 2A near #185, observed to have a vertical sidewall, is in continuous contact with #190 along the z-direction. Therefore, it is the examiner’s interpretation that Son does disclose the amended limitation and the 35 U.S.C. 102(a)(1)/(a)(2) rejection of claims 14-17 and 19-20 as being anticipated by US 2023/0046500 A1; Son, Yonghoon; 02/2023; (“Son”) is maintained.
Applicant’s amendments to claim 14 along with corresponding arguments, see page 9 of the remarks, filed 06/23/2026, with respect to the 35 U.S.C. 102 rejections of the claim, and its respective dependent claim, in view of US 2019/0115358 A1; Lee et al.; 04/2019; (“Lee”) have been fully considered but are not found persuasive. Claim(s) 14 and 18 stand(s) rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2019/0115358 A1; Lee et al.; 04/2019; (“Lee”)..
Applicant argues that the amendment to the claims to recite “wherein the second portion of the contact is in contact with a dielectric layer in the second region along the first direction” overcomes the cited prior art because Lee fails to disclose that the second portion is in contact with an upper surface of a dielectric layer. Examiner respectfully disagrees.
Examiner first notes that applicant’s amendment to the claims does not appear to match the feature applicant claims is not taught by the cited prior art. The amendment to the claim does not refer to an upper surface of a dielectric layer. The claim amendment requires only that “the second portion of the contact is in contact with a dielectric layer in the second region along the first direction”. In Lee, the second portion of the contact (Figure 7I annotated, the second portion of #171) is entirely located within the second region (Figure 7I, #CT) and is in direct contact with a dielectric layer (#150, Figure 7I, molding insulating layer). The phrase “along the first (z-direction) direction” is interpreted by the examiner to encompass two possible meanings as described above for the Son reference, the latter of which is satisfied by the Lee reference. In the second interpretation, the second portion of #171 in Figure 7I annotated is observed to have a vertical sidewall that is in continuous contact with #150 along the z-direction. Therefore, it is the examiner’s interpretation that Lee does disclose the amended limitation and the 35 U.S.C. 102(a)(1) rejection of claims 14 and 18 as being anticipated by US 2019/0115358 A1; Lee et al.; 04/2019; (“Lee”) is maintained.
Applicant’s request for the rejoinder of claims 1-13, see page 10 of the remarks, filed 06/23/2026, with respect to the believed allowability of claim 14 and incorporation of the features of claim 14 into claim 1 have been fully considered. However, because claim 14 stands rejected for the reasons provided above, the claims are not eligible for rejoinder at this time and claims 1-13 stand withdrawn.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TYLER JAMES WIEGAND whose telephone number is (571)270-0096. The examiner can normally be reached Mon-Fri. 8AM-5PM.
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/TYLER J WIEGAND/Examiner, Art Unit 2812
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