Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention 2 (claims 14-20) in the reply filed on 03/04/2026 is acknowledged. Claim(s) 1-13 is/are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim.
Priority
Acknowledgment is made of applicant's claim for priority under 35 U.S.C. 119(a)-(d) or (f), 365(a) or (b), or 386(a) based upon an application filed in PEOPLE'S REPUBLIC OF CHINA on 05/30/2023.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 03/13/2026 has/have been considered by the examiner and made of record in the application file.
Claim Objections
Claims 14-20 is/are objected to because of the following informalities where proposed corrections are bolded and underlined:
Claim 14, line 7, “a target conductive layer of the conductive layers”;
Claim 17, lines 4-5, “the insulation layer along the direction,[[ ,]] and wherein the second”, where there is an extra comma;
Claim 19, lines 7-9, “extending from a surface of [[ ]] the stack structure to a target”, where there is an unnecessary extra paragraph break in the middle of the lines.
The balance of claims are objected to at least for their dependencies. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 14-17 and 19-20 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by US 2023/0046500 A1; Son, Yonghoon; 02/2023; (“Son”).
Regarding Claim 14. Son discloses A three-dimensional (3D) memory device (#100, Figures 1-4, [0026]-[0029], semiconductor device which may include a memory region according to [0030]), comprising:
a stack structure (Figure 2A, stack of #120s and #130s) comprising a plurality of alternating conductive layers (#130, Figure 2A, gate electrodes) and dielectric layers (#120, Figure 2A, insulating layers), the stack structure having a first region (#R1, Figure 2A) and a second region (#R2, Figure 2A);
gate line slit structures (#MS, Figure 2B, separation regions which split the gate electrodes #130) extending through the stack structure and dividing the stack structure into a plurality of memory blocks (Figure 2B, [0047], “separation regions MS continuously extending from the first region R1 and the second region R2 of the separation regions MS. The gate electrodes 130 between the separation regions MS may form a single memory block”, i.e. #MS extends through the stack to divide it into separate blocks); and
a contact (#170, Figure 2A and 3A, plug zoomed in in block A from Figure 2A in Figure 3A) located in the second region (Figure 2A, #170s are located in #R2) and comprising a first portion extending from a surface of the stack structure to a target conductive layer (Figure 3A, a portion of #170 extends from a top surface of a topmost #130 of the stack in the box A to at least a bottom of the topmost #130 being the target) of the conductive layers (Figure 3A, the target #130 is one of the many #130s in the stack) and a second portion covering part of the surface of the stack structure (Figure 3A, a portion of #170 above the stack structure at least partially covers a top surface of the stack structure),
wherein a material of the first portion and the second portion of the contact is same as a material of the conductive layers ([0158], “the pad region 130P and the contact plug 170 may be formed of the same material”, i.e. the entire #170 including the first and second portions and #130s may be made of a same material).
Regarding Claim 15. Son discloses The 3D memory device of claim 14, further comprising a plurality of channel structures (#CH, Figure 2B, channel structures) extending through the stack structure (Figure 2B, each #CH extends through the stack of #130s and #120s),
wherein each of the plurality of channel structures (#CH) comprises a memory film (#145A, Figure 2B, [0062], #145A may include a memory film structure including a tunneling layer, a charge storage layer, and a blocking layer, matching the description of [0047] in the instant application) and a semiconductor channel (#140, Figure 2B, channel layer formed of a semiconductor material according to [0061]) inwards from an inner surface of the channel structure to a center of the channel structure sequentially (Figure 2B, #140 is on an inner surface of #CH more towards the center of #CH than the memory film #145A).
Regarding Claim 16. Son discloses The 3D memory device of claim 15, further comprising a first connection structure (#185 over the #170 extending through box #A, Figure 2A, upper interconnection connected to #170) and a second connection structure (#185s over #CHs in region #R1, Figure 2A, upper interconnections connected to the channel pads #155 of #CH),
wherein the first connection structure is connected to the contact (Figure 2A, a #185 is directly connected to #170), and the second connection structure is connected to the channel structures (Figure 2A, #185s in the region #R1 are connected to #CHs).
Regarding Claim 17. Son discloses The 3D memory device of claim 15, further comprising a second conductive layer (#102, Figure 2B, first horizontal conductive layer) between a semiconductor substrate (#101, Figure 2B, second substrate) and an insulation layer (bottommost #120 of the stack, Figure 2B, let the bottommost insulating layer #120 be interpreted as an insulation layer separate from the stack structure) (Figure 2B, #102 is between #101 and the bottommost #120),
wherein the plurality of channel structures extends into the semiconductor substrate along a direction (Figure 2B, #CHs extend into #101 along the z-direction), and the stack structure is above the insulation layer along the direction (Figure 2B, the stack of #130s and #120s is above the bottommost #120 along the z-direction),[[ ,]] and wherein the second conductive layer is coupled to the semiconductor channel of each of the plurality of channel structures (Figure 2B, #102 is directly electrically coupled to #140 of each #CH).
Regarding Claim 19. Son discloses A memory system (#1000, Figure 13, data storage system), comprising:
a memory device configured to store data (#1100, Figure 13, semiconductor device which may be a memory device for data storage according to [0162]), the memory device comprising ([0162], #1100 may be the device of Figures 1-4):
a stack structure (Figure 2A, stack of #120s and #130s) comprising a plurality of alternate conductive layers (#130, Figure 2A, gate electrodes) and dielectric layers (#120, Figure 2A, insulating layers), and having a first region (#R1, Figure 2A) and a second region (#R2, Figure 2A);
gate line slit structures (#MS, Figure 2B, separation regions which split the gate electrodes #130) extending through the stack structure and dividing the stack structure into a plurality of memory blocks (Figure 2B, [0047], “separation regions MS continuously extending from the first region R1 and the second region R2 of the separation regions MS. The gate electrodes 130 between the separation regions MS may form a single memory block”, i.e. #MS extends through the stack to divide it into separate blocks); and
a contact (#170, Figure 2A and 3A, plug zoomed in in block A from Figure 2A in Figure 3A) in the second region (Figure 2A, #170s are located in #R2) and comprising a first portion extending from a surface of [[ ]] the stack structure to a target conductive layer (Figure 3A, a portion of #170 extends from a top surface of a topmost #130 of the stack in the box A to at least a bottom of the topmost #130 being the target) and a second portion covering a part of the surface of the stack structure (Figure 3A, the target #130 is one of the many #130s in the stack) and a second portion covering part of the surface of the stack structure (Figure 3A, a portion of #170 above the stack structure at least partially covers a top surface of the stack structure), wherein the first portion and the second portion of the contact comprise a same material as the conductive layers ([0158], “the pad region 130P and the contact plug 170 may be formed of the same material”, i.e. the entire #170 including the first and second portions and #130s may be made of a same material); and
a memory controller (#1200, Figure 13, controller) coupled to the memory device and configured to control the memory device (Figure 13, [0168], #1200 is coupled to #1100 through input/output pads #1101 and controls the memory device).
Regarding Claim 20. Son discloses The memory system of claim 19, further comprising a host coupled to the memory controller and configured to send or receive the data ([0169], “host interface 1230 may provide a communication function between the data storage system 1000 and an external host. When a control command is received from an external host through the host interface 1230”, i.e. an external host is coupled to #1200 and may send or receive data from data from the controller #1200 which is further detailed in [0172]).
Claim(s) 14 and 18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2019/0115358 A1; Lee et al.; 04/2019; (“Lee”). An annotated version of Figure 7I from Lee is provided below and referenced in the following rejection.
Regarding Claim 14. Lee discloses A three-dimensional (3D) memory device (#10, Figures 1-6, semiconductor device which may be a memory device according to [0009] and wherein Figure 7I is a side view of the completed device), comprising:
a stack structure (#130s and #140s, Figures 3 and 7I, alternating stack of #130s and #140s) comprising a plurality of alternating conductive layers (#130s, Figure 7I, gate electrode layers) and dielectric layers (#140s, Figure 7I, insulating layers), the stack structure having a first region (#CA, Figure 3, cell array region) and a second region (#CT, Figure 3, contact region);
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gate line slit structures (#160 and #160S, Figure 3, conductive lines and their spacers which split the gate electrodes) extending through the stack structure and dividing the stack structure into a plurality of memory blocks (Figure 3, [0030] and [0045], #160s are the word line cuts which separate the stack into a plurality of structures or memory blocks); and
a contact (#171 of #170s, Figure 7I, contact plug) located in the second region (Figure 7I, #171 is located in the contact region #CT) and comprising a first portion extending from a surface of the stack structure to a target conductive layer of the conductive layers (Figure 7I annotated, first portion of #171 extends from a side surface of #142 of #140s in the stack to a target conductive layer #131 of the conductive layers #130) and a second portion covering part of the surface of the stack structure (Figure 7I annotated, the second portion of #171 covers part of the side surface of #142),
wherein a material of the first portion and the second portion of the contact is same as a material of the conductive layers ([0040], “contact plugs 170 may include the same material as a material for forming the gate electrode layers 130”, i.e. all of #171 and #130s include the same material).
Regarding Claim 18. Lee discloses The 3D memory device of claim 14, wherein the gate line slit structures (#160 and #160S) comprise first sub-portions (Figure 3, horizontally extending portions of #160) and second sub-portions (Figure 3, vertically extending portions of #160), and the contact further at least comprises a third portion and a fourth portion (Figure 7I annotated, third and fourth portions of #171), and
wherein a material of the first sub-portions of the gate line slit structures is same as a material of the third portion of the contact, and a material of the second sub-portions of the gate line slit structures is same as the fourth portion of the contact ([0042] and [0102], #160 may be made of tungsten (W) and #170s may also be made of Tungsten (W) such that all portions of #160 and #171 may be made of Tungsten (W)).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2016/0322374 A1; Sano et al.; 11/2016 – Figure 48 discloses a memory device wherein the conductive gate electrodes in the stack (#46) and their corresponding contact structures (#66) are formed of the same conductive material in a single integrated structure without any interface in order to prevent microscopic cavities or impurity layers at the interface and improve electrical characteristics (see [0097]).
US 2017/0301686 A1; Imamura et al.; 10/2017 – Figure 45 discloses a memory device wherein the conductive gate electrodes in the stack (#70) and their corresponding contact structures (#91) are formed of the same conductive material in a single integrated structure as one continuous body.
US 2021/0366919 A1; Sung et al.; 11/2021 – Figure 10E discloses a memory device wherein the conductive gate electrodes in the stack (#20) and their corresponding contact structures (#CNT2) are formed of the same conductive material in a single integrated structure as one continuous body (see [0056]).
US 10,192,784 B1; Cui et al.; 01/2019 – Figure 18B discloses a memory device wherein the conductive gate electrodes in the stack (#46) and their corresponding contact structures (#86) are formed of the same conductive material in a single integrated structure as one continuous body (see column 26 line 43 through column 27 line 2).
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/TYLER J WIEGAND/Examiner, Art Unit 2812