DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/20/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 10-16 are rejected under 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, first paragraph, because the claim purports to invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, but fails to recite a combination of elements as required by that statutory provision and thus cannot rely on the specification to provide the structure, material or acts to support the claimed function. As such, the claim recites a function that has no limits and covers every conceivable means for achieving the stated function, while the specification discloses at most only those means known to the inventor. Accordingly, the disclosure is not commensurate with the scope of the claim.
Claim 10 recites “a system comprising: a processing device”. Current disclosure pars. [0100] and [0118] the processing device is represented as other processing devices and therefore according BRI, the processing device is a generic placeholder and invokes 35 U.S.C. 112(f) and it is included as single component in the claims, therefore the claim is directed to single means claim.
The dependent claims fails to cure the deficiency of the rejected claim and therefore the dependent claims also rejected under same rationales as applied to claim 10 above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Jiang et al. (US 2024/0004680) and further in view of Smith et al. (US 2019/0050309).
As per claims 1, 10 and 17, Jiang teaches a method (Jiang: abstract)/a system comprising a processing device to perform operations/A processor comprising: a plurality of processing units and a controller (Jiang: par. [0026]; claim 16; Smith: par. [0034]) comprising: receiving a request to initiate a testing process for each of a plurality of processing units, wherein a first processing unit of the plurality of processing units executes a first set of operations by first virtual processor (Jiang: par. [0016]: “a performance test is executed on a physical CPU core that is part of a first mapping of virtual processors to logical CPU cores”; and a second processing unit of the plurality of processing units executes a second set of operations by a second virtual processor (Jiang: pars. [0025] – [0027]: teaches multiple virtual processors are mapped to logical CPU cores and executing operations e.g., none of the CPUs are off-parked and therefore executing workloads).
Jiang (pars. [0028] – [0034]) teaches a method of off-parking CPU core when a performance test is executed, i.e., the virtual processor 208 mapped to logical core 222 is remapped to logical core 226 (fig. 2B) and therefore no longer available for processing workloads. Since, the virtual processor 208 is remapped logical core 226, it is processing workload of virtual processor 208, which requires transfer of data and state to logical core 226).
Jiang expressly fails to teach causing execution of the first set of operations by the first virtual processor to be transferred from the first processing unit to the second processing unit; initiating execution of the testing process at the first processing unit while the second processing unit executes the first set of operations by the first virtual processor and the second set of operations by the second virtual processor; responsive to detecting that the execution of the testing process is completed at the first processing unit, causing execution of the first set of operations by the first virtual processor and the second set of operations by the second virtual processor to be transferred from the second processing unit to the first processing unit; and initiating execution of the testing process at the second processing unit while the first processing unit executes the first set of operations by the first virtual processor and the second set of operations by the second virtual processor.
Smith teaches causing execution of the first set of operations by the first virtual processor to be transferred from the first processing unit to the second processing unit; initiating execution of the testing process at the first processing unit while the second processing unit executes the first set of operations by the first virtual processor and the second set of operations by the second virtual processor; responsive to detecting that the execution of the testing process is completed at the first processing unit, causing execution of the first set of operations by the first virtual processor and the second set of operations by the second virtual processor to be transferred from the second processing unit to the first processing unit; and initiating execution of the testing process at the second processing unit while the first processing unit executes the first set of operations by the first virtual processor and the second set of operations by the second virtual processor. Smith: par. [0025]: “While the SBFTs are executing on a core, the core is not available to execute software (equivalent to MWAIT(C6)) or respond to any interrupt sources, for the duration of the test (which can be in excess of 30 milliseconds). Therefore, in order to meet real-time requirements, not all cores can be in this test mode simultaneously. At a minimum, cores are tested in two test groups 402/404 to allow any active tasks and interrupt handling to be migrated from cores under test to cores available to process the workload and handle interrupts”; par. [0027]: “the Test Manager logic still needs to schedule tests in a minimum of two Test Groups 402/404 and in a way to allow any other real-time workloads to continue to run, by migrating from in-test cores to available cores”; par. [0028]: “.as long as tests are not run simultaneously on both TestGroup1 and TestGroup2, to allow workloads to continue to execute on cores not under test”; As underlined above, Smith teaches performing real-time test by grouping of processor cores into test groups and while one group of processors are under test, the workload of the processor under test is migrated to another group and when the test is done, the workload is transferred back to first group and vice a versa. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to cause execution of the first set of operations by the first virtual processor to be transferred from the first processing unit (group) to the second processing unit (group); initiating execution of the testing process at the first processing unit while the second processing unit executes the first set of operations by the first virtual processor and the second set of operations by the second virtual processor and vice a versa as taught by Smith in the system of Jiang provide protection against single point faults and prevent hazardous events from occurring (Smith: pars. [0010] – [0012]).
As per claims 2, 11 and 18, Jiang and Smith teach wherein a third processing unit of the plurality of processing unit hosts a third virtual processor executing a third set of operations, and wherein the method further comprises: responsive to detecting that execution of the testing process is completed at the second processing unit, causing execution of the third set of operations to be transferred from the third virtual processor to the second virtual processor; and initiating execution of the testing process at the third processing unit while the first virtual processor executes at least one of the first set of operations or the second set of operations and the second virtual processor executes the third set of operations. Jiang teaches a plurality of processing units hosting plurality of virtual processors (figs. 2A and 2B: items 208, 210, 212, 214, 216) and Smith teaches two groups of cores one is processing workloads and the other is performing testing by migrating workload to the group not performing tests. Therefore, it would be readily apparent to one having ordinary skill in the art before the effective filing date of the claimed invention to migrate operations of third processing unit to second processing unit or any other available processing unit not part of test group to perform the test and also continue the other tasks simultaneously.
As per claims 3, 12 and 19, Jiang and Smith teach wherein the testing process is a fault detection process, and wherein the method further comprises: determining, based on a performance of the testing process of at least one processing unit of the plurality of processing units, whether a fault occurred at the at least one processing unit; and responsive to determining that a fault occurred at the at least one processing unit, transmitting an alert indicating the fault (Jiang: par. [0031]: “The recorded data related to the CPU core indicates CPU error data, warnings, and similar notifications”; Smith: par. [0023]: “signals a fault if any tests failed 316”).
As per claims 4, 13 and 20, Jiang and Smith teach wherein the first processing unit and the second processing unit are components of a first processor core of a system comprising the plurality of processing units (Smith: par. [0014]).
As per claims 5 and 14, Jiang and Smith expressly fail to teach wherein the plurality of processing units further comprises a fourth processing unit and a fifth processing unit that are components of a second processor core of the system, wherein the fourth processing unit executes a fourth set of operations associated with a fourth virtual processor and the fifth processing unit executes a fifth set of operations associated with a fifth virtual processor, and wherein the method further comprises: responsive to the request to initiate the testing process, causing execution of the fourth set of operations to be transferred from the fourth virtual processor to the fifth virtual processor; and initiating execution of the testing process at the fourth processing unit while the testing process is simultaneously performed using at least one of the first processing unit or the second processing unit of the first processor core. However, as explained above with respect to claims 1 and 2, Smith teaches grouping the cores into test groups and group of cores performing workload operations, where it would be readily apparent to one having ordinary skill in the art to select any of the processing core for testing and migrating operations from the core under test to another core for simultaneous testing and performing operations as taught by Jiang and Smith to performing the testing while still the system available for executing the operations.
As per claims 6 and 15, Jiang and Smith teach wherein the first virtual processor and the second virtual processor are associated with a virtual computing system running on the plurality of processing units (Jiang: pars. [0061] – [0062]).
As per claims 7 and 16, Jiang and Smith teach wherein the virtual computing system comprises at least one of a virtual machine or a container (Jiang: pars. [0061] – [0062]).
As per claim 8, Jiang and Smith teach wherein causing execution of the first set of operations to be transferred from the first virtual processor to the second virtual processor comprises transmitting a first instruction to a virtual system manager associated with the first virtual processor and the second virtual processor to transfer execution of the first set of operations from the first virtual processor to the second virtual processor, and wherein causing execution of the first set of operations and the second set of operations to be transferred from the second virtual processor to the first virtual processor comprises transmitting a second instruction to the virtual system manager to transfer execution of the first set of operations and the second set of operations from the first virtual processor to the second virtual processor (Jiang: par. [0014] hypervisor maps the virtual processors and allocates the workload; par. [0022] hypervisor scheduling tasks; par. [0031]: “the performance test is executed using testing software implemented by a component of the host device, such as an OS kernel (executing with or without a hypervisor), a hypervisor, or a processor power management component. Executing the performance test may comprise causing the CPU core to execute a set of commands or instructions”).
As per claim 9, Jiang and Smith teach wherein the plurality of processing units is comprised in at least one of: a control system for an autonomous or semi-autonomous machine; a perception system for an autonomous or semi-autonomous machine; a system for performing simulation operations; a system for performing digital twin operations; a system for performing light transport simulation; a system for performing collaborative content creation for 3D assets; a system for performing deep learning operations; a system implemented using an edge device; a system implemented using a robot; a system for performing conversational AI operations; a system for generating synthetic data; a system for presenting at least one of virtual reality content, augmented reality content, or mixed reality content; a system implemented at least partially in a data center; or a system implemented at least partially using cloud computing resources (Jiang: pars. [0020], [0033]; Smith: par. [0038]).
Conclusion
The examiner also requests, in response to this Office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line no(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application. 37 C.F.R. § 1.75(d) (1) requires such support in the Specification for any new language added to the claims and 37 C.F.R. § 1.83(a) requires support be found in the Drawings for all claimed features.
When responding to this office action, Applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of the art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections See 37 CFR 1.111(c).
Examiner has cited particular columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant, in preparing the responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
The cited prior arts of record not relied upon teach a method of testing processors by migrating workloads.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAUSHIKKUMAR M PATEL whose telephone number is (571)272-5536. The examiner can normally be reached Mon-Fri: 9:00 AM - 5:30 PM.
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Kaushikkumar M. Patel
Primary Examiner
Art Unit 2138
/Kaushikkumar M Patel/Primary Examiner, Art Unit 2138