DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4 and 7-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pan (US 20230274998 A1).
Regarding claim 1, Pan teaches an electronic device (4, Fig 4), comprising: a unit chip (UC: unit chip including component 11, reinforcement, and a portion of power regulating device 15; please see annotated figure below) including:
an electronic component (11) having a power delivery circuit (PDC: 11p, including pads on both surfaces 111 and 112, and all 11v conductive elements); and
a reinforcement (R: portions of 13, 30, and 40 between 11 and 15; please see annotated figure below) supporting (shown supporting) the electronic component (11),
wherein the reinforcement (R) is configured to transmit (component receives power signal, [0029]) a power signal (p2, Fig 3A) to the power delivery circuit (PDC, Fig 4),
wherein the reinforcement (R) includes a thermosetting reinforcement (epoxy resin, [0031]; encapsulant 40 would be made out of the same material as encapsulant 12) or a glass reinforcement.
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Regarding claim 2, Pan teaches the device of claim 1 and goes on to teach wherein the reinforcement (R, Fig 4) includes fillers (F: fillers, [0031]; encapsulant 40 would be made out of the same material as encapsulant 12).
Regarding claim 3, Pan teaches the device of claim 1 and goes on to teach wherein the unit chip (UC, Fig 4) further comprises:
a conductive element (30) within (shown within) the reinforcement (R) and configured to provide a power path (p3, Fig 3A; component receives power signal, [0029]).
Regarding claim 4, Pan teaches the device of claim 3 and goes on to teach wherein the reinforcement (R, Fig 4) includes fillers (F) disposed on (shown on) at least two sides (30S: left and right sides of 30) of the conductive element (30).
Regarding claim 7, Pan teaches the device of claim 1 and goes on to teach wherein the electronic component (11, Fig 4) has a circuit region (11C: bottom portion of 11 that is connected to 30 and the lower pads; please see annotated figure above) and a logic circuit (11L: top portion of 11 containing 11v; please see annotated figure above; 11 may be a CPU, [0027], which would contain a logic circuit) disposed between (shown between) the circuit region (11C) and the power delivery circuit (PDC).
Regarding claim 8, Pan teaches the device of claim 7 and goes on to teach a carrier (10, Fig 4) over (shown over) which the unit chip (UC) is disposed and configured to provide (component receives power signal, [0029]) a power path (p1, Fig 3A) between (shown between) a power source (power source, [0054]) and the unit chip (UC),
wherein the electronic component (11) is disposed between (shown between) the carrier (10) and the reinforcement (R).
Regarding claim 9, Pan teaches the device of claim 8 and goes on to teach wherein the carrier (10, Fig 4) is electrically connected (shown electrically connected) with the power delivery circuit (PDC) through a connection (12v1) not covered (shown not covered) by the unit chip (UC).
Regarding claim 10, Pan teaches the device of claim 1 and goes on to teach wherein the unit chip (UC, Fig 4) further comprises:
a power regulating device (15) at least partially disposed in (shown partially disposed in) the reinforcement (R) and configured to provide (component receives power signal, [0029]) a power path (p1/p2/p3).
Regarding claim 11, Pan teaches the device of claim 10 and goes on to teach wherein the power regulating device (15, Fig 4) has a first surface (15B: bottom of 15) facing (shown facing) the power delivery circuit (PDC) and
a second surface (15T: top of 15) opposite (shown opposite) to the first surface (15B), and
wherein the power regulating device (15) is configured to transmit (component receives power signal, [0029]) the power signal (p2, Fig 3A) to the power delivery circuit (PDC, Fig 4) through (shown through) the first surface (15B).
Regarding claim 12, Pan teaches the device of claim 10 and goes on to teach wherein the unit chip (UC, Fig 4) further comprises:
a conductive element (30) within (shown within) the reinforcement (R) and configured to electrically connect (shown electrically connecting) the power regulating device (15) to the power delivery circuit (PDC); and
an interconnection structure (IC: 13p and portion of 13a outside of R) disposed over (shown over when device is rotated 90 degrees) the reinforcement (R) and configured to electrically connect (shown electrically connecting) the power regulating device (15) to the conductive element (30).
Regarding claim 13, Pan teaches an electronic device (4, Fig 4), comprising: a unit chip (UC: unit chip including component 11, reinforcement, and a portion of power regulating device 15; please see annotated figure above) including:
an electronic component (11) having a power delivery circuit (PDC: 11p, including pads on both surfaces 111 and 112, and all 11v conductive elements) and a logic circuit (11L: top portion of 11 containing 11v; please see annotated figure above; 11 may be a CPU, [0027], which would contain a logic circuit); and
a reinforcement (R: portions of 13, 30, and 40 between 11 and 15; please see annotated figure above) supporting (shown supporting) the electronic component (11) and having a power regulating device (15) configured to provide (component receives power signal, [0029]) a power signal (p2, Fig 3A) to the logic circuit (11L, Fig 4) through the power delivery circuit (PDC).
Regarding claim 14, Pan teaches the device of claim 13 and goes on to teach wherein the power regulating device (15, Fig 4) is at least partially embedded (shown partially embedded) in the reinforcement (R).
Regarding claim 15, Pan teaches the device of claim 13 and goes on to teach wherein the power regulating device (15, Fig 4) is attached (shown attached) to a backside surface (112) of the electronic component (11) through an adhesive layer (12, comprised of epoxy resin, [0031], which is adhesive) and includes a conductive pad (13p) at least partially exposed (shown exposed) from the reinforcement (R).
Regarding claim 16, Pan teaches the device of claim 13 and goes on to teach wherein the unit chip (UC, Fig 4) further comprises: a conductive element (30) within (shown within) the reinforcement (R) and configured to transmit (component receives power signal, [0029]) the power signal (p2) from the power regulating device (15) to the power delivery circuit (PDC).
Regarding claim 17, Pan teaches the device of claim 13 and goes on to teach wherein the power regulating device (15, Fig 4) is electrically connected (shown electrically connected) with a backside surface (112) of the electronic component (11) through an electrical contact (11p).
Regarding claim 18, Pan teaches an electronic device (4, Fig 4), comprising: a unit chip (UC: unit chip including component 11, reinforcement, and a portion of power regulating device 15; please see annotated figure above) including:
an electronic component (11) having I/O connections (I/O: I/O pins on active surface 111, [0056]), a power delivery circuit (PDC: 11p, including pads on both surfaces 111 and 112, and all 11v conductive elements), and a logic circuit (11L: top portion of 11 containing 11v; please see annotated figure above; 11 may be a CPU, [0027], which would contain a logic circuit) between (shown between) the I/O connections (I/O) and the power delivery circuit (PDC);
a reinforcement (R: portions of 13, 30, and 40 between 11 and 15; please see annotated figure above) supporting (shown supporting) the electronic component (11) and exclusive (shown without) of a capacitance device (none shown); and
a conductive element (30) penetrating (shown penetrating) the reinforcement (R).
Regarding claim 19, Pan teaches the device of claim 18 and goes on to teach further comprising: a carrier (10, Fig 4) over (shown over) which the unit chip (UC) is disposed,
wherein the electronic component (11) is electrically connected (shown electrically connected) with the carrier (10) through (shown through) the I/O connections (I/O) and
the conductive element (30) is configured to transmit (component receives power signal, [0029]) a power signal (p2, Fig 3A) to the logic circuit (11L).
Regarding claim 20, Pan teaches the device of claim 19 and goes on to teach wherein the unit chip (UC, Fig 4) further comprises: an interconnection structure (IC: 13p and portion of 13a outside of R) disposed over (shown over when device is rotated 90 degrees) the reinforcement (R) and configured to electrically connect (shown electrically connecting) the conductive element (30) and the carrier (10).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Pan (US 20230274998 A1) as applied to claims 1-4 and 7-20 above, and further in view of the obviousness of change in shape.
Regarding claim 5, Pan teaches the device of claim 3, the conductive element (30, Fig 4), and the power delivery circuit (PDC).
Pan fails to explicitly teach the conductive element tapers toward the power delivery circuit.
However, MPEP 2144.04 Section IV.B states that limitations related to changes in shape are not sufficient to patentably distinguish over the prior art. A person of ordinary skill in the art would have found it obvious to change the shape of a non-critical element.
Paragraph [0048] of the instant application states, "In some arrangements, the conductive element 13v may taper toward the power delivery circuit (such as the conductive element 11v) of the electronic component 11." However, the specification is silent to the criticality of the taper of the conductive element to the design. A change in shape would have been obvious to one of ordinary skill in the art before the time of filing.
Therefore, Pan discloses the limitations of claim 5 in view of the obviousness of change in shape.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Pan (US 20230274998 A1) as applied to claims 1-4 and 7-20 above, and further in view of Fillion (US 20190304910 A1).
Regarding claim 6, Pan teaches the device of claim 3, the unit chip (UC, Fig 4), the conductive element (30), and the reinforcement (R).
Pan fails to explicitly teach the unit chip further comprises: a seed layer disposed between the conductive element and the reinforcement.
However, Fillion teaches wherein the unit chip further comprises: a seed layer (68, Fig 5; manufacture of interconnect begins with seed metal, [0052]) disposed between (shown between) the conductive element and the reinforcement.
Pan and Fillion are considered analogous to the claimed invention because both are from the same field of endeavor of embedded electronic package devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the device of Pan with the features of Fillion to create a device wherein the unit chip further comprises: a seed layer disposed between the conductive element and the reinforcement because the via structure has an order of magnitude lower interconnect resistance and interconnect inductance compared to wire bonds or solder bumps (Fillion, [0004]) that efficiently provide electrical connections for logic or control semiconductor devices within the power module (Fillion, [0008]) for achieving better performance, greater miniaturization, and higher reliability (Fillion, [0002]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chung (US 20250087646 A1) - backside power delivery package.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jeremy D Watts whose telephone number is (703)756-1055. The examiner can normally be reached M-R 8:00am-4:30pm, F 8:00-3pm EST.
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/JEREMY DANIEL WATTS/Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897