DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The response filed 07/08/2026 is accepted, in which, claims 1, 4, 8, 14, 17, and 18 are amended and claims 3 and 6 are newly canceled. Claims 1, 8, and 14 are independent. Claims 15-20 are withdrawn. Claims 1-2, 4-5, and 7-14 await an action on the merits as follows.
The objection to the specification is withdrawn in view of the amended title.
Response to Arguments
Applicant's arguments filed 07/08/2026 have been fully considered but they are not persuasive.
Regarding amended claim 1, on pages 10-11 of the response, Applicant argues:
"However, as illustrated in Fig. 7 of Tekleab (reproduced above), the bottom surface of the gate dielectric layer 35 is in direct contact with the silicon cap layer 23. In other words, there is no layer having a top surface and a bottom surface that are respectively in direct contact with the gate dielectric layer 35 and the silicon cap layer 23 of Tekleab.
In addition, on page 6 of the Action with respect to the rejection of claim 3, the Office cites Fig. 6 of Ono and asserts that the dielectric film 8 of Ono corresponds to the claimed interface layer.
However, the bottom surface of the dielectric film 8 of Ono is in direct contact with the channel region 3 of Ono.
In contrast, amended claim 1 recites "a top surface of the interface layer is in direct contact with the dielectric layer, and a bottom surface of the interface layer is in direct contact with the capping layer."
For at least the above reasons, Applicant respectfully submits that amended claim 1 is patentable and respectfully requests allowance of amended claim 1. Claims 2, 5, and 7 depend from claim 1 and recite additional distinguishing features. Accordingly, Applicant respectfully requests allowance of these claims. Claim 6 has been cancelled and thus the rejection as to this claim is now moot."
Examiner respectfully disagrees.
Ono teaches a base product of silicon oxide layer 11, Fig 15, on the channel with a high-k layer 12 on top of it as a gate dielectric layer 10 to which the claimed invention can be seen as an improvement in that a decrease in a current driving force is suppressed, the drop accompanying a variance of a relative positional relationship of a boundary between the source/drain region and a channel region with respect to the gate dielectric film, and that a high-performance fine semiconductor device capable of operating at a sufficiently high speed is realized, [0007].
Tekleab teaches a known technique of inserting a silicon cap layer 23, Fig 7, on the channel layer, between the S/D regions, with a high-k dielectric layer 35 as a gate dielectric layer on top of it that is comparable to the base product.
Tekleab’s known technique, as cited above, would have been recognized by one skilled in the art as applicable to the base product of Ono and the results would have been predictable and resulted in superior gate stack reliability, improvements to negative bias temperature instability, threshold voltage tunability (Lee, [0003]), and improved fabrication techniques of silicon germanium channel and silicon/silicon germanium dual channel devices, which do not degrade performance of SiGe channels (Lee, [0005]), which results in an improved product.
The combination results in a gate dielectric layer comprising two layers on a silicon cap on top of the channel with an interface layer (silicon oxide layer) directly on the cap, with a high-k dielectric layer directly on top of it.
The combination of Ono and Tekleab discloses a dielectric layer located on the channel layer; an interface layer located between the dielectric layer and the channel layer; and a work function metal layer located on the dielectric layer; and a capping layer located between the channel layer and the gate structure, wherein a top surface of the interface layer is in direct contact with the dielectric layer, and a bottom surface of the interface layer is in direct contact with the capping layer.
Therefore, the claimed subject matter would have been obvious to a person having ordinary skill in the art at the time of the effective filing date of the invention.
The rationale to support a conclusion that the claim would have been obvious is that a particular known technique was recognized as part of the ordinary capabilities of one skilled in the art. One of ordinary skill in the art would have been capable of applying this known technique to a known device that was ready for improvement and the results would have been predictable to one of ordinary skill in the art.
The argument is overcome the and rejection stands.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-2, 4-5, 7-10, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Tekleab (US 20100109044 A1), and further in view of Ono (US 20070018238 A1).
Regarding claim 1, Tekleab teaches a semiconductor device (72, Fig 7), comprising:
a substrate (12);
a channel layer (22) located on (shown on) the substrate (12), wherein
the channel layer (22) comprises silicon germanium (silicon germanium, [0022]);
a source/drain region (38) adjacent (shown adjacent) to the channel layer (22);
a gate structure (34) located on (shown on) the channel layer (22),
wherein the gate structure (34) comprises:
a dielectric layer (35) located on (shown on) the channel layer (22);
a work function metal layer (36) located on (shown on) the dielectric layer (35); and
a capping layer (23) located between (shown between) the channel layer (22) and the gate structure (34),
Tekleab fails to explicitly teach an interface layer located between the dielectric layer and the channel layer; and a top surface of the interface layer is in direct contact with the dielectric layer, and a bottom surface of the interface layer is in direct contact with the capping layer.
However, Ono teaches an interface layer (11, Fig 15) located between (shown between the high-k dielectric layer 12 and the channel 3) the dielectric layer and the channel layer; a top surface (11T: top surface of 11) of the interface layer (11), and a bottom surface (11B: bottom of 11) of the interface layer (11).
Tekleab goes on to teach a top surface of the interface layer is in direct contact (in direct contact; The combination results in a gate dielectric layer comprising two layers on a silicon cap on top of the channel with an interface layer directly on the cap, with a high-k dielectric layer directly on top of it.) with the dielectric layer (35), and
a bottom surface of the interface layer is in direct contact (in direct contact; The combination results in a gate dielectric layer comprising two layers on a silicon cap on top of the channel with an interface layer directly on the cap, with a high-k dielectric layer directly on top of it.) with the capping layer (23).
Tekleab and Ono are considered analogous to the claimed invention because both are from the same field of endeavor of semiconductor display devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the device of Tekleab with the features of Ono to create a device with an interface layer located between the dielectric layer and the channel layer; and a top surface of the interface layer is in direct contact with the dielectric layer, and a bottom surface of the interface layer is in direct contact with the capping layer so that a decrease in a current driving force is suppressed and a high-performance fine semiconductor device capable of operating at a sufficiently high speed is realized (Ono, [0007]).
Regarding claim 2, the combination of Tekleab and Ono discloses the device of claim 1. Tekleab goes on to teach wherein the substrate (12, Fig 7) has a different lattice constant (different; compressively stressed layer 22 has a larger atom-to-atom spacing than substrate 12, [0021]) from the channel layer (22).
Regarding claim 4, the combination of Tekleab and Ono discloses the device of claim 1. Tekleab teaches the source/drain region (38, Fig 7).
Ono goes on to teach wherein the interface layer (8, Fig 6) partially overlaps (shown partially overlapping S/D regions 6) the source/drain region in a vertical direction (Y: vertical direction in Fig 6).
Regarding claim 5, the combination of Tekleab and Ono discloses the device of claim 1. Tekleab goes on to teach wherein the gate structure (34, Fig 7) further comprises:
a fill layer (37) located on (shown on) the work function metal layer (36).
Regarding claim 7, the combination of Tekleab and Ono discloses the device of claim 1. Tekleab goes on to teach wherein the substrate (12, Fig 7) comprises silicon (silicon, [0018]).
Regarding claim 8, Tekleab teaches a semiconductor device (72, Fig 7), comprising:
a substrate (12);
a channel layer (22) located on (shown on) the substrate (12), wherein
the channel layer (22) comprises silicon germanium (silicon germanium, [0022]) and is configured to exert a compressive force (compressively stressed, [0021]);
a source/drain region (38) adjacent (shown adjacent) to the channel layer (22); and
a gate structure (34) located on (shown on) the channel layer (22) and
comprising a dielectric layer (35), wherein
the dielectric layer (35) is located on (shown on) the channel layer (22), and
a capping layer (23) located between (shown between) the channel layer (22) and the gate structure (34),
Tekleab fails to explicitly teach an interface layer.
However, Ono teaches an interface layer (11, Fig 15), and goes on to teach a top surface (11T: top surface of 11, Fig 15 Ono) of the interface layer (11) and a bottom surface (11B: bottom of 11) of the interface layer (11).
Tekleab goes on to teach the interface layer is located between (between; The combination results in a gate dielectric layer comprising two layers on a silicon cap on top of the channel with an interface layer directly on the cap, with a high-k dielectric layer directly on top of it.) the dielectric layer (35) and the channel layer (22); and
a top surface of the interface layer is in direct contact (in direct contact; The combination results in a gate dielectric layer comprising two layers on a silicon cap on top of the channel with an interface layer directly on the cap, with a high-k dielectric layer directly on top of it.) with the dielectric layer (35), and
a bottom surface of the interface layer is in direct contact (in direct contact; The combination results in a gate dielectric layer comprising two layers on a silicon cap on top of the channel with an interface layer directly on the cap, with a high-k dielectric layer directly on top of it.) with the capping layer (23).
Tekleab and Ono are considered analogous to the claimed invention because both are from the same field of endeavor of semiconductor display devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the device of Tekleab with the features of Ono to create a device with an interface layer located between the dielectric layer and the channel layer; and a top surface of the interface layer is in direct contact with the dielectric layer, and a bottom surface of the interface layer is in direct contact with the capping layer so that a decrease in a current driving force is suppressed and a high-performance fine semiconductor device capable of operating at a sufficiently high speed is realized (Ono, [0007]).
Regarding claim 9, the combination of Tekleab and Ono discloses the device of claim 8. Tekleab goes on to teach an interlayer dielectric layer (39, Fig 7) located on (shown on) the substrate (12) and the gate structure (34).
Regarding claim 10, the combination of Tekleab and Ono discloses the device of claim 9. Tekleab goes on to teach wherein the interlayer dielectric layer (39, Fig 7) surrounds (shown surrounding) the gate structure (34).
Regarding claim 14, Tekleab teaches a manufacturing method of a semiconductor device (72, Fig 7), comprising:
forming a source/drain region (38) in (shown in) a substrate (12);
growing a channel layer (22) over (shown over) the substrate (12), wherein
the channel layer (22) directly contacts (shown in direct contact) the substrate (12) and comprises silicon germanium (silicon germanium, [0022]);
forming a capping layer (23) on (shown on) the channel layer (22); and
forming a gate structure (34) on (shown on) the capping layer (23) on (shown on) the channel layer (22), wherein
the gate structure (34) comprises a dielectric layer (35), wherein
the dielectric layer (35) is located on (shown on) the channel layer (22), and
a capping layer (23) located between (shown between) the channel layer (22) and the gate structure (34),
Tekleab fails to explicitly teach an interface layer.
However, Ono teaches an interface layer (11, Fig 15), and goes on to teach a top surface (11T: top surface of 11, Fig 15 Ono) of the interface layer (11) and a bottom surface (11B: bottom of 11) of the interface layer (11).
Tekleab goes on to teach the interface layer is located between (between; The combination results in a gate dielectric layer comprising two layers on a silicon cap on top of the channel with an interface layer directly on the cap, with a high-k dielectric layer directly on top of it.) the dielectric layer (35) and the channel layer (22); and
a top surface of the interface layer is in direct contact (in direct contact; The combination results in a gate dielectric layer comprising two layers on a silicon cap on top of the channel with an interface layer directly on the cap, with a high-k dielectric layer directly on top of it.) with the dielectric layer (35), and
a bottom surface of the interface layer is in direct contact (in direct contact; The combination results in a gate dielectric layer comprising two layers on a silicon cap on top of the channel with an interface layer directly on the cap, with a high-k dielectric layer directly on top of it.) with the capping layer (23).
Tekleab and Ono are considered analogous to the claimed invention because both are from the same field of endeavor of semiconductor display devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the method of Tekleab with the features of Ono to create a method with an interface layer located between the dielectric layer and the channel layer; and a top surface of the interface layer is in direct contact with the dielectric layer, and a bottom surface of the interface layer is in direct contact with the capping layer so that a decrease in a current driving force is suppressed and a high-performance fine semiconductor device capable of operating at a sufficiently high speed is realized (Ono, [0007]).
Claims 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Tekleab (US 20100109044 A1), in view of Ono (US 20070018238 A1), and further in view of Lee (US 20200111714 A1).
Regarding claim 11, the combination of Tekleab and Ono discloses the device of claim 8. Tekleab teaches the source/drain region (38, Fig 7).
The combination fails to explicitly teach a first conductive contact located on the source/drain region.
However, Lee teaches a first conductive contact (195, Fig 8; source drain contacts comprised of tungsten, [0076]) located on (shown on) the source/drain region.
Tekleab, Ono, and Lee are considered analogous to the claimed invention because all are from the same field of endeavor of semiconductor display devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the device of Tekleab and Ono with the features of Lee to create a device with a first conductive contact located on the source/drain region to provide superior gate stack reliability, improvements to negative bias temperature instability, threshold voltage tunability (Lee, [0003]), and improved fabrication techniques of silicon germanium channel and silicon/silicon germanium dual channel devices, which do not degrade performance of SiGe channels (Lee, [0005]).
Regarding claim 12, the combination of Tekleab, Ono, and Lee discloses the device of claim 11. Tekleab teaches the gate structure (34, Fig 7).
Lee goes on to teach a second conductive contact (155, Fig 6; gate layers include gate metal layers comprised of a combination of tungsten and cobalt, [0064]) located on (shown on) the gate structure (34, Fig 7), wherein
the second conductive contact (155) comprises different material (cobalt) from the first conductive contact (195).
Regarding claim 13, the combination of Tekleab, Ono, and Lee discloses the device of claim 12. Lee goes on to teach wherein the first conductive contact (195, Fig 8) comprises tungsten (tungsten, [0076]) and
the second conductive contact (155) comprises tungsten and cobalt (tungsten and cobalt, [0064]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Mizushima (US 20040251458 A1) - tensile strain changes lattice constant
Rai (4004159) - Interface layer overlaps S/D regions
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jeremy D Watts whose telephone number is (703)756-1055. The examiner can normally be reached M-R 8:00am-4:30pm, F 8:00-3pm EST.
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/JEREMY DANIEL WATTS/Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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