DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
The response filed 03/18/2026 is accepted, in which, Applicant elects Invention I without traverse directed to a semiconductor device of claims 1-13 along with generic claim 14.
Response to Amendment
The response filed 03/18/2026 is accepted. Claims 1, 8, and 14 are independent. Claims 15-20 are withdrawn. Claims 1-14 await an action on the merits as follows.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 5-10, and 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tekleab (US 20100109044 A1).
Regarding claim 1, Tekleab teaches a semiconductor device (72, Fig 7), comprising:
a substrate (12);
a channel layer (22) located on (shown on) the substrate (12), wherein
the channel layer (22) comprises silicon germanium (silicon germanium, [0022]);
a source/drain region (38) adjacent (shown adjacent) to the channel layer (22); and
a gate structure (34) located on (shown on) the channel layer (22),
wherein the gate structure (34) comprises:
a dielectric layer (35) located on (shown on) the channel layer (22); and
a work function metal layer (36) located on (shown on) the dielectric layer (35).
Regarding claim 2, Tekleab teaches the device of claim 1 and goes on to teach wherein the substrate (12, Fig 7) has a different lattice constant (different; compressively stressed layer 22 has a larger atom-to-atom spacing than substrate 12, [0021]) from the channel layer (22).
Regarding claim 5, Tekleab teaches the device of claim 1 and goes on to teach wherein the gate structure (34, Fig 7) further comprises:
a fill layer (37) located on (shown on) the work function metal layer (36).
Regarding claim 6, Tekleab teaches the device of claim 1 and goes on to teach a capping layer (23, Fig 7) located between (shown between) the channel layer (22) and the gate structure (34).
Regarding claim 7, Tekleab teaches the device of claim 1 and goes on to teach wherein the substrate (12, Fig 7) comprises silicon (silicon, [0018]).
Regarding claim 8, Tekleab teaches a semiconductor device (72, Fig 7), comprising:
a substrate (12);
a channel layer (22) located on (shown on) the substrate (12), wherein
the channel layer (22) comprises silicon germanium (silicon germanium, [0022]) and is configured to exert a compressive force (compressively stressed, [0021]);
a source/drain region (38) adjacent (shown adjacent) to the channel layer (22); and
a gate structure (34) located on (shown on) the channel layer (22).
Regarding claim 9, Tekleab teaches the device of claim 8 and goes on to teach an interlayer dielectric layer (39, Fig 7) located on (shown on) the substrate (12) and the gate structure (34).
Regarding claim 10, Tekleab teaches the device of claim 9 and goes on to teach wherein the interlayer dielectric layer (39, Fig 7) surrounds (shown surrounding) the gate structure (34).
Regarding claim 14, Tekleab teaches a manufacturing method of a semiconductor device (72, Fig 7), comprising:
forming a source/drain region (38) in (shown in) a substrate (12);
growing a channel layer (22) over (shown over) the substrate (12), wherein
the channel layer (22) directly contacts (shown in direct contact) the substrate (12) and comprises silicon germanium (silicon germanium, [0022]); and
forming a gate structure (34) on (shown on) the channel layer (22).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Tekleab (US 20100109044 A1) as applied to claims 1-2, 5-10, and 14 above, and further in view of Ono (US 20070018238 A1).
Regarding claim 3, Tekleab teaches the device of claim 1 the gate structure (34, Fig 7), the dielectric layer (35), and the channel layer (22).
Tekleab fails to explicitly teach wherein the gate structure further comprises: an interface layer located between the dielectric layer and the channel layer.
However, Ono teaches wherein the gate structure further comprises:
an interface layer (8, Fig 6) located between (shown between the high-k dielectric layer 9 and the channel 3) the dielectric layer and the channel layer.
Tekleab and Ono are considered analogous to the claimed invention because both are from the same field of endeavor of semiconductor display devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the device of Tekleab with the features of Ono to create a device wherein the gate structure further comprises: an interface layer located between the dielectric layer and the channel layer so that a decrease in a current driving force is suppressed and a high-performance fine semiconductor device capable of operating at a sufficiently high speed is realized (Ono, [0007]).
Regarding claim 4, the combination of Tekleab and Ono discloses the device of claim 3. Tekleab teaches the source/drain region (38, Fig 7).
Ono goes on to teach wherein the interface layer (8, Fig 6) partially overlaps (shown partially overlapping S/D regions 6) the source/drain region in a vertical direction (Y: vertical direction in Fig 6).
Claims 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Tekleab (US 20100109044 A1) as applied to claims 1-2, 5-10, and 14 above, and further in view of Lee (US 20200111714 A1).
Regarding claim 11, Tekleab teaches the device of claim 8 and the source/drain region (38, Fig 7).
Tekleab fails to explicitly teach a first conductive contact located on the source/drain region.
However, Lee teaches a first conductive contact (195, Fig 8; source drain contacts comprised of tungsten, [0076]) located on (shown on) the source/drain region.
Tekleab and Lee are considered analogous to the claimed invention because both are from the same field of endeavor of semiconductor display devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the device of Tekleab with the features of Lee to create a device with a first conductive contact located on the source/drain region to provide superior gate stack reliability, improvements to negative bias temperature instability, threshold voltage tunability (Lee, [0003]), and improved fabrication techniques of silicon germanium channel and silicon/silicon germanium dual channel devices, which do not degrade performance of SiGe channels (Lee, [0005]).
Regarding claim 12, the combination of Tekleab and Lee discloses the device of claim 11. Tekleab teaches the gate structure (34, Fig 7).
Lee goes on to teach a second conductive contact (155, Fig 6; gate layers include gate metal layers comprised of a combination of tungsten and cobalt, [0064]) located on (shown on) the gate structure (34, Fig 7), wherein
the second conductive contact (155) comprises different material (cobalt) from the first conductive contact (195).
Regarding claim 13, the combination of Tekleab and Lee discloses the device of claim 12. Lee goes on to teach wherein the first conductive contact (195, Fig 8) comprises tungsten (tungsten, [0076]) and
the second conductive contact (155) comprises tungsten and cobalt (tungsten and cobalt, [0064]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Mizushima (US 20040251458 A1) - tensile strain changes lattice constant
Rai (4004159) - Interface layer overlaps S/D regions
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/JEREMY DANIEL WATTS/Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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