DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
At the following locations, indicated by the notation [claim(s), line(s)], please make the following changes to provide better clarity, proper grammar, or proper antecedent basis:
[19, 2] change “The transistor portion” to “the transistor portion”.
[19, 3] change “The diode portion” to “the diode portion”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 8-11, 13, 18, and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kobayashi et al. (US 2019/0280118) (hereafter Kobayashi118).
Regarding claim 1, Kobayashi118 discloses a silicon carbide semiconductor device comprising a transistor portion 141 (Fig. 7, paragraph 0005) and a diode portion (region between 141 in Fig. 7), comprising:
a semiconductor substrate 101 (Fig. 7, paragraph 0006);
a plurality of trench portions 107 (Fig. 7, paragraph 0009) that are provided on a front surface of the semiconductor substrate 101 (Fig. 7);
a drift region 102 (Fig. 7, paragraph 0006) of a first conductivity type (“n-“ in Fig. 7) that is provided on the semiconductor substrate 101 (Fig. 7); and
a second conductivity type region 121 (Fig. 7, paragraph 0007) that covers a side wall and a bottom of a trench portion 107 (Fig. 7) in the diode portion (region between 141 in Fig. 7)); wherein
the transistor portion 141 (Fig. 7) and the diode portion (region between 141 in Fig. 7) are alternately arrayed along an extending direction of the trench portion 107 (Fig. 7) in a mesa portion 103a (Fig. 7, paragraph 0007) that is sandwiched between the plurality of trench portions 107 (Fig. 7).
Regarding claim 2, Kobayashi118 further discloses the silicon carbide semiconductor device according to claim 1, wherein the transistor portion 141 (Fig. 7) has a source region 105 (Fig. 7, paragraph 0007) of a first conductivity type (“n+” in Fig. 7) and a contact region 106 (Fig. 7, paragraph 0007) of a second conductivity type (“p+” in Fig. 7) on the front surface of the semiconductor substrate 101 (Fig. 7).
Regarding claim 3, Kobayashi118 further discloses the silicon carbide semiconductor device according to claim 2, wherein in a depth direction (vertical direction in Fig. 7) of the semiconductor substrate 101 (Fig. 7), a thickness of the source region 105 (Fig. 7) is thinner than a thickness of the contact region 106 (Fig. 7).
Regarding claim 4, Kobayashi118 further discloses the silicon carbide semiconductor device according to claim 2, including a base region 104 (Fig. 7, paragraph 0007) of the second conductivity type (“p” in Fig. 7) that is provided above the drift region 102 (Fig. 7) and below the source region 105 (Fig. 7) and the contact region 106 (Fig. 7).
Regarding claim 5, Kobayashi118 further discloses the silicon carbide semiconductor device according to claim 4, wherein a width (horizontal length of 104 in Fig. 7) in the extending direction (horizontal direction in Fig. 7) of the trench portion 107 (Fig. 7) of the base region 104 (Fig. 7) is smaller than a total of a width (horizontal length of 106 in Fig. 7) of the contact region 106 (Fig. 7) in the extending direction of the trench portion and a width (horizontal length of 105 in Fig. 7) of the source region 106 (Fig. 7) in the extending direction (horizontal direction in Fig. 7) of the trench portion.
Regarding claim 8, Kobayashi118 (utilized different elements for a second conductivity type region as applied in claim 1 in the above) discloses a silicon carbide semiconductor device comprising a transistor portion 141 (Fig. 7, paragraph 0005) and a diode portion (region between 141 in Fig. 7), comprising:
a semiconductor substrate 101 (Fig. 7, paragraph 0006);
a plurality of trench portions 107 (Fig. 7, paragraph 0009) that are provided on a front surface of the semiconductor substrate 101 (Fig. 7);
a drift region 102 (Fig. 7, paragraph 0006) of a first conductivity type (“n-“ in Fig. 7) that is provided on the semiconductor substrate 101 (Fig. 7); and
a second conductivity type region (121-123 in Fig. 7, paragraph 0007) that covers a side wall and a bottom of a trench portion 107 (Fig. 7) in the diode portion (region between 141 in Fig. 7)); wherein
the transistor portion 141 (Fig. 7) and the diode portion (region between 141 in Fig. 7) are alternately arrayed along an extending direction of the trench portion 107 (Fig. 7) in a mesa portion 103a (Fig. 7, paragraph 0007) that is sandwiched between the plurality of trench portions 107 (Fig. 7);
wherein the transistor portion 141 (Fig. 7) has a source region 105 (Fig. 7, paragraph 0007) of a first conductivity type (“n+” in Fig. 7) and a contact region 106 (Fig. 7, paragraph 0007) of a second conductivity type (“p+” in Fig. 7) on the front surface of the semiconductor substrate 101 (Fig. 7); and
wherein the second conductivity type region (121-123 in Fig. 7) and the contact region 106 (Fig. 7) are directly contacting in the extending direction (horizontal direction in Fig. 7) of the trench portion.
Regarding claim 9, Kobayashi118 further discloses the silicon carbide semiconductor device according to claim 4, comprising a mesa body region (122 and 123 in Fig. 7, paragraph 0007) of the second conductivity type (“p+” in Fig. 7) in the mesa portion 103a (Fig. 7) along the extending direction (horizontal direction in Fig. 7) of the trench portion 107 (Fig. 7), which is provided to contact a lower end of the base region 104 (Fig. 7).
Regarding claim 10, Kobayashi118 further discloses the silicon carbide semiconductor device according to claim 9, wherein the mesa body region (122 and 123 in Fig. 7) includes: a first mesa body portion 122 (Fig. 7, paragraph 0007) that is provided in the transistor portion 141 (Fig. 7) and the diode portion (region between 141 in Fig. 7); a second mesa body portion 123 (Fig. 7, paragraph 0007) that is provided above the first mesa body portion 122 (Fig. 7) in the transistor portion 141 (Fig. 7) and having an upper end which is in direct contact with the lower end of the base region 104 (Fig. 7); wherein an upper end of the first mesa body portion 122 (Fig. 7) is in direct contact with a lower end of the second mesa body portion 123 (Fig. 7) in the transistor portion 141 (Fig. 7).
Regarding claim 11, Kobayashi118 further discloses the silicon carbide semiconductor device according to claim 10, wherein each doping concentration (see “p+” in Fig. 7) of the first mesa body portion 122 (Fig. 7) and the second mesa body portion 123 (Fig. 7) is equal to or greater than a doping concentration (see “p” in Fig. 7) of the base region 104 (Fig. 7) or equal to or less than a doping concentration of the contact region.
Regarding claim 13, Kobayashi118 (utilized different elements for a second conductivity type region as applied in claim 1 in the above) discloses a silicon carbide semiconductor device comprising a transistor portion 141 (Fig. 7, paragraph 0005) and a diode portion (region between 141 in Fig. 7), comprising:
a semiconductor substrate 101 (Fig. 7, paragraph 0006);
a plurality of trench portions 107 (Fig. 7, paragraph 0009) that are provided on a front surface of the semiconductor substrate 101 (Fig. 7);
a drift region 102 (Fig. 7, paragraph 0006) of a first conductivity type (“n-“ in Fig. 7) that is provided on the semiconductor substrate 101 (Fig. 7); and
a second conductivity type region (portion of 121 in the region between 141 in Fig. 7) that covers a side wall and a bottom of a trench portion 107 (Fig. 7) in the diode portion (region between 141 in Fig. 7); wherein
the transistor portion 141 (Fig. 7) and the diode portion (region between 141 in Fig. 7) are alternately arrayed along an extending direction of the trench portion 107 (Fig. 7) in a mesa portion 103a (Fig. 7, paragraph 0007) that is sandwiched between the plurality of trench portions 107 (Fig. 7);
wherein the transistor portion 141 (Fig. 7) has a source region 105 (Fig. 7, paragraph 0007) of a first conductivity type (“n+” in Fig. 7) and a contact region 106 (Fig. 7, paragraph 0007) of a second conductivity type (“p+” in Fig. 7) on the front surface of the semiconductor substrate 101 (Fig. 7);
a base region 104 (Fig. 7, paragraph 0007) of the second conductivity type (“p” in Fig. 7) that is provided above the drift region 102 (Fig. 7) and below the source region 105 (Fig. 7) and the contact region 106 (Fig. 7); and
wherein a trench body region (portion of 121 in 141 in Fig. 7) of the second conductivity type (“p+” in Fig. 7) that is provided to cover the bottom and the side wall of the plurality of trench portions 107 (Fig. 7) and that has a doping concentration higher than that of the base region 104 (Fig. 7, wherein “p”).
Regarding claim 18, Kobayashi118 further discloses the silicon carbide semiconductor device according to claim 4, wherein the base region 104 (Fig. 7) is provided between (see Fig. 7, wherein 104 is formed diagonally between 105 and 107) the source region 105 (Fig. 7) and the trench portion 107 (Fig. 7) on the front surface of the semiconductor substrate 101 (Fig. 7).
Regarding claim 19, Kobayashi118 further discloses the silicon carbide semiconductor device according to claim 2, wherein The transistor portion 141 (Fig. 7) sandwiches the trench portion 107 (Fig. 7) to face the diode portion (region between 141 in Fig. 7), and The diode portion (region between 141 in Fig. 7) sandwiches the trench portion 107 (Fig. 7) to face the transistor portion 141 (Fig. 7).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Kobayashi118 as applied to claim 4 above, and further in view of Arthur et al. (US 2020/0194546) (hereafter Arthur).
Regarding claim 6, Kobayashi118 discloses the silicon carbide semiconductor device according to claim 4, however Kobayashi118 does not disclose an area of the base region is smaller than a total of an area of the contact region and an area of the source region in a top view.
Arthur discloses an area of the base region 34 (Fig. 4, paragraph 0028) is smaller than a total of an area of the contact region (not shown in Fig. 4 but see 60 in Fig. 3, paragraph 0030) and an area of the source region 32 (Fig. 4, paragraph 0028) in a top view.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kobayashi118 to form an area of the base region is smaller than a total of an area of the contact region and an area of the source region in a top view, as taught by Arthur, since a change in size is generally recognized as being within the level of ordinary skill in the art In re Rose, 105 USPQ 237 (CCPA 1955). Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Claims 7, 12, 14-17, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kobayashi118 as applied to claims 1, 4, 10, 13, and 19 above, and further in view of Kobayashi et al. (US 2018/0182885) (hereafter Kobayashi885).
Regarding claim 7, Kobayashi118 discloses the silicon carbide semiconductor device according to claim 4, however Kobayashi118 does not disclose the base region is provided to be in direct contact with the side wall of the trench portion in the diode portion at the front surface of the semiconductor substrate.
Kobayashi885 discloses the base region 16 (Figs. 16 and 17, paragraph 0081) is provided to be in direct contact with the side wall of the trench portion 28 (Fig. 16, paragraph 0086) in the diode portion (“B” in Fig. 16, paragraph 0062) at the front surface of the semiconductor substrate 1 (Fig. 16, paragraph 0062).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kobayashi118 to form the base region is provided to be in direct contact with the side wall of the trench portion in the diode portion at the front surface of the semiconductor substrate, as taught by Kobayashi885, since the p-type base region 16 (Kobayashi885, Fig. 16, paragraph 0081) is formed so as to have a boundary within a width of the trench 28 (Kobayashi885, Fig. 16, paragraph 0081) that separates the region A (Kobayashi885, Fig. 16, paragraph 0081) and the region B (Kobayashi885, Fig. 16, paragraph 0081) later.
Regarding claim 12, Kobayashi118 discloses the silicon carbide semiconductor device according to claim 10, however Kobayashi118 does not disclose each doping concentration of the first mesa body portion and the second mesa body portion is 1×1018 cm-3 or more and 4×1018 cm-3 or less.
Kobayashi885 discloses each doping concentration of the first mesa body portion (lower 3 in Fig. 1, paragraph 0079) and the second mesa body portion (upper 3 in Fig. 1, paragraph 0079) is about 1.0×1017 to 1.0×1019/cm-3.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kobayashi118 to form each doping concentration of the first mesa body portion and the second mesa body portion is 1×1018 cm-3 or more and 4×1018 cm-3 or less, as taught by Kobayashi885, since in the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Regarding claim 14, Kobayashi118 discloses the silicon carbide semiconductor device according to claim 13, however Kobayashi118 does not disclose the trench body region includes: a first trench body portion that is provided in the transistor portion and the diode portion; and a second trench body portion that is provided above the first trench body portion in the diode portion and having an upper end which is in direct contact with a lower end of the base region; wherein an upper end of the first trench body portion is provided to be in direct contact with a lower end of the second trench body portion in the diode portion.
Kobayashi885 discloses the trench body region (portion of 3 in “A” and region between 3 and 16 in Fig. 16) includes: a first trench body portion (lower region between 3 and 16 in Fig. 16) that is provided in the transistor portion (“A” in Fig. 16) and the diode portion (“B” in Fig. 16); and a second trench body portion (upper region between 3 and 16 in Fig. 16) that is provided above the first trench body portion (lower region between 3 and 16 in Fig. 16) in the diode portion (“B” in Fig. 16) and having an upper end which is in direct contact with a lower end of the base region 16 (Fig. 16); wherein an upper end of the first trench body portion (lower region between 3 and 16 in Fig. 16) is provided to be in direct contact with a lower end of the second trench body portion in the diode portion (upper region between 3 and 16 in Fig. 16).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kobayashi118 to form the trench body region includes: a first trench body portion that is provided in the transistor portion and the diode portion; and a second trench body portion that is provided above the first trench body portion in the diode portion and having an upper end which is in direct contact with a lower end of the base region; wherein an upper end of the first trench body portion is provided to be in direct contact with a lower end of the second trench body portion in the diode portion, as taught by Kobayashi885, since in the OFF state (Kobayashi885, paragraph 0066), the Schottky diode part is protected by a parasitic junction FET caused by a depletion layer spreading from the deep p.sup.+-type region 3 (Kobayashi885, paragraph 0066), the electric field may be mitigated and the leak current in the OFF state may be reduced.
Regarding claim 15, Kobayashi118 in view of Kobayashi885 discloses the silicon carbide semiconductor device according to claim 14, however Kobayashi118 does not disclose the second conductivity type region includes the first trench body portion, the second trench body portion and the base region.
Kobayashi885 discloses the second conductivity type region (p conductivity in Fig. 16) includes the first trench body portion (lower region between 3 and 16 in Fig. 16), the second trench body portion (upper region between 3 and 16 in Fig. 16) and the base region 16 (Fig. 16).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kobayashi118 to form the second conductivity type region includes the first trench body portion, the second trench body portion and the base region, as taught by Kobayashi885, since in the OFF state (Kobayashi885, paragraph 0066), the Schottky diode part is protected by a parasitic junction FET caused by a depletion layer spreading from the deep p.sup.+-type region 3 (Kobayashi885, paragraph 0066), the electric field may be mitigated and the leak current in the OFF state may be reduced.
Regarding claim 16, Kobayashi118 in view of Kobayashi885 discloses the silicon carbide semiconductor device according to claim 14, however Kobayashi118 does not disclose the second conductivity type region includes the first trench body portion, the second trench body portion, the base region and the contact region.
Kobayashi885 discloses the second conductivity type region (p conductivity in Fig. 16) includes the first trench body portion, (lower region between 3 and 16 in Fig. 16) the second trench body portion (upper region between 3 and 16 in Fig. 16), the base region 16 (Fig. 16) and the contact region 18 (Fig. 16).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kobayashi118 to form the second conductivity type region includes the first trench body portion, the second trench body portion, the base region and the contact region, as taught by Kobayashi885, since in the OFF state (Kobayashi885, paragraph 0066), the Schottky diode part is protected by a parasitic junction FET caused by a depletion layer spreading from the deep p.sup.+-type region 3 (Kobayashi885, paragraph 0066), the electric field may be mitigated and the leak current in the OFF state may be reduced.
Regarding claim 17, Kobayashi118 discloses the silicon carbide semiconductor device according to claim 1, however Kobayashi118 does not disclose a thickness of the second conductivity type region is 0.1 µm or more, or 0.3 µm or less on the side wall of the trench portion.
Kobayashi885 discloses a thickness of the second conductivity type region 3 (Fig. 1, paragraph 0077) is about 0.1 to 1.5 μm on the side wall of the trench portion 28 (Fig. 1, paragraph 0073).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kobayashi118 to form a thickness of the second conductivity type region is 0.1 µm or more, or 0.3 µm or less on the side wall of the trench portion, as taught by Kobayashi885, since a change in size is generally recognized as being within the level of ordinary skill in the art In re Rose, 105 USPQ 237 (CCPA 1955). In addition, in the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Regarding claim 20, Kobayashi118 discloses the silicon carbide semiconductor device according to claim 19, however Kobayashi118 does not disclose an area of the transistor portion is greater than an area of the diode portion in a top view.
Kobayashi885 discloses an area of the transistor portion (A-1, Fig. 3, paragraph 0071) is greater (see paragraph 0070, wherein “the area of the region B may be smaller than the area of the region A”) than an area of the diode portion (B-3, Fig. 3, paragraph 0071) in a top view.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kobayashi118 to form an area of the transistor portion is greater than an area of the diode portion in a top view, as taught by Kobayashi885, since a change in size is generally recognized as being within the level of ordinary skill in the art In re Rose, 105 USPQ 237 (CCPA 1955). Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Conclusion
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/L.B.K/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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