DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement(s) submitted on October 30, 2023 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) is/are being considered by the examiner.
Claim Objections
Claims 1, 6, 8, 11 and 20 are objected to because of the following informalities:
“a first conductivity-type” should read “the first conductivity-type” (claim 1, line 5);
“a second conductivity type” should read “the second conductivity type” (claim 1, line 7 and claim 11, line 2);
“a front surface of the semiconductor substrate” should read “the front surface of the semiconductor substrate” (claim 6, lines 2-3 and claim 20, lines 4 and 7);
the period between “therebetween” and “on” must be deleted (claim 6, line 5);
“a lower end of the base region” should read “the lower end of the base region” (claim 8, lines 2-3).
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 8-11, 14-15 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2017/0221714 A1 (hereinafter “Wakimoto”).
Regarding claim 1, Wakimoto discloses in Figs. 1, 2 and related text a silicon carbide semiconductor device ([0048]) comprising:
a plurality of trench portions (7; [0049]) provided on a front surface of a semiconductor substrate (1; [0049]);
a drift region (2; [0049]) of a first conductivity-type (n-type) provided on the semiconductor substrate;
a base region (4a, 4b; [0053]) of a second conductivity type (p-type) provided above the drift region;
a source region (5; [0049]) of the first conductivity-type provided above the drift region and having a higher doping concentration than the drift region ([0047]; the source region is designated n+ whereas the drift region is designated n-);
a contact region (6; [0049]) of the second conductivity type provided above the drift region and having a higher doping concentration than the base region ([0047]; the contact region is designated p++ whereas the base region is designated p); and
a second conductivity type region (13; [0052]) provided below the source region and above a lower end of the base region and having a higher doping concentration than the base region ([0047]; the second conductivity type region is designated p+ whereas the base region is designated p), wherein
the second conductivity type region is provided to be in contact with a side wall of any trench portion of the plurality of trench portions (Fig. 1).
Regarding claim 2, Wakimoto discloses a doping concentration of the second conductivity type region (p+) is greater than a doping concentration of the base region (p) and is lower than or equal to the doping concentration of the contact region (p++) (Fig. 2; [0047], [0052] and [0065]).
Regarding claim 3, Wakimoto discloses a doping concentration of the second conductivity type region is 1×1018 cm-3 or more and 1×1020 cm-3 or less (Fig. 2; [0065]).
Regarding claim 8, Wakimoto discloses a body region (12; Fig. 1; [0051]) of the second conductivity type provided to be in contact with the lower end of the base region between the plurality of trench portions adjacent to each other.
Regarding claim 9, Wakimoto discloses the body region comprises a first body region (12a; Fig. 6; [0067]) and a second body region (12b; Fig. 6; [0069]) provided above the first body region,
an upper end of the second body region is in contact with the lower end of the base region (Fig. 9), and
an upper end of the first body region is in contact with a lower end of the second body region (Fig. 6).
Regarding claim 10, Wakimoto shows the second conductivity type region and the contact region are separated by the base region therebetween (Fig. 1).
Regarding claim 11, Wakimoto discloses a trench bottom region (11; Fig. 1; [0050]) of the second conductivity type provided on a lower end of the plurality of trench portions and having a higher doping concentration (p+) than the base region (p).
Regarding claim 14, Wakimoto shows the second conductivity type region is provided so as to extend from a side wall of one trench portion to a side wall of another trench portion adjacent thereto in an arrangement direction of the plurality of trench portions (Fig. 1).
Regarding claim 15, Wakimoto shows the second conductivity type region is provided so as to extend from a side wall of one trench portion to a side wall of another trench portion adjacent thereto in an arrangement direction of the plurality of trench portions (Fig. 1).
Claim(s) 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2008/0124870 A1 (hereinafter “Park”).
Regarding claim 20, Park discloses a method for fabricating a silicon carbide semiconductor device ([0053]), comprising:
forming a mask (203) on a front surface of a semiconductor substrate (202) comprising a plurality of trench portions (210) (Figs. 2A-2F; [0027]-[0029]);
implanting a dopant (211) into the front surface of the semiconductor substrate with the mask to form a second conductivity type region (204) of a second conductivity type (n-type) so as to be in contact with a side wall of any trench portion of the plurality of trench portions (Fig. 2G; [0030]); and
implanting a dopant (213) into the front surface of the semiconductor substrate with the mask to form a source region (208) of a first conductivity type (p-type) (Fig. 2H; [0035]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wakimoto in view of US 2007/0045700 A1 (hereinafter “Ohtani-2007”).
Regarding claim 4, Wakimoto discloses the silicon carbide semiconductor device according to claim 1.
Wakimoto does not disclose the source region is provided so as to extend from a side wall of one trench portion of the plurality of trench portions to a side wall of another trench portion adjacent thereto in an arrangement direction of the plurality of trench portions.
Ohtani-2007 teaches in Fig. 14B and related text the source region (104; [0125]) is provided so as to extend from a side wall of one trench portion of the plurality of trench portions (110; [0073]) to a side wall of another trench portion adjacent thereto in an arrangement direction of the plurality of trench portions.
Wakimoto and Ohtani-2007 are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Wakimoto with the specified features of Ohtani-2007 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to provide the source region so as to extend from a side wall of one trench portion of the plurality of trench portions to a side wall of another trench portion adjacent thereto in an arrangement direction of the plurality of trench portions, as taught by Ohtani-2007, in order to lower a resistance of the source region by increasing its width, thereby increasing an on-state current of the semiconductor device.
Regarding claim 18, Wakimoto discloses the silicon carbide semiconductor device according to claim 1.
Wakimoto does not disclose the source region faces another source region with the trench portion sandwiched therebetween, and the contact region faces another contact region with the trench portion sandwiched therebetween.
Ohtani-2007 teaches in Figs. 10, 14A-14B and related text the source region (104; [0115]) faces another source region with the trench portion (110; [0073]) sandwiched therebetween, and the contact region (105; [0115]) faces another contact region with the trench portion sandwiched therebetween.
Wakimoto and Ohtani-2007 are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Wakimoto with the specified features of Ohtani-2007 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form the source region to face another source region with the trench portion sandwiched therebetween, and to form the contact region to face another contact region with the trench portion sandwiched therebetween, as taught by Ohtani-2007, in order to define a rectangular unit cell of the semiconductor device (Ohtani-2007: [0115]).
Claim(s) 6 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wakimoto in view of US 2003/0222304 A1 (hereinafter “Ohtani-2003”).
Regarding claim 6, Wakimoto discloses the silicon carbide semiconductor device according to claim 1.
Wakimoto does not disclose the base region is provided between the source region and the contact region on the front surface of the semiconductor substrate, and the source region and the contact region are separated by the base region therebetween on the front surface of the semiconductor substrate.
Ohtani-2003 teaches in Figs. 5A-5B and related text the base region (21; [0033]) is provided between the source region (22; [0033]) and the contact region (23; [0033]) on the front surface of the semiconductor substrate (11; [0032]), and
the source region and the contact region are separated by the base region therebetween on the front surface of the semiconductor substrate.
Wakimoto and Ohtani-2003 are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Wakimoto with the specified features of Ohtani-2003 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to provide the base region between the source region and the contact region on the front surface of the semiconductor substrate, and to separate the source region and the contact region by the base region therebetween on the front surface of the semiconductor substrate, as taught by Ohtani-2003, in order to increase the blocking voltage in an off-state without increasing the on-resistance (Ohtani-2003: [0054]).
Regarding claim 7, Wakimoto discloses the silicon carbide semiconductor device according to claim 1.
Wakimoto does not disclose a width of the base region between the source region and the contact region in an extending direction of the plurality of trench portions is 0.2 μm or more and 0.5 μm or less.
Ohtani-2003 teaches in Figs. 5A-5B and related text the base region (21; [0033]) is provided between the source region (22; [0033]) and the contact region (23; [0033]).
However, Ohtani-2003 does not teach a width of the base region between the source region and the contact region in an extending direction of the plurality of trench portions is 0.2 μm or more and 0.5 μm or less.
Wakimoto and Ohtani-2003 are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Wakimoto with the specified features of Ohtani-2003 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to provide the base region between the source region and the contact region, as taught by Ohtani-2003, wherein a width of the base region between the source region and the contact region in an extending direction of the plurality of trench portions is 0.2 μm or more and 0.5 μm or less, in order to increase the blocking voltage in an off-state without increasing the on-resistance (Ohtani-2003: [0054]), and because it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. Ohtani-2003 explains in [0053] that certain dimensions of the vertical metal oxide semiconductor (MOS) transistor can be adjusted based on the performance required for the transistor.
Claim(s) 13, 16 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wakimoto in view of US 2009/0289264 A1 (hereinafter “Matsuki”).
Regarding claim 13, Wakimoto discloses the silicon carbide semiconductor device according to claim 1.
Wakimoto does not disclose a thickness of the second conductivity type region in a depth direction of the semiconductor substrate is 0.05 μm or more and 0.2 μm or less.
Matsuki teaches in Fig. 4 and related text a thickness of the second conductivity type region (6; [0024] and [0043]) in a depth direction of the semiconductor substrate (1; [0023]) is 0.05 μm or more and 0.2 μm or less.
Wakimoto and Matsuki are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Wakimoto with the specified features of Matsuki because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form a thickness of the second conductivity type region in a depth direction of the semiconductor substrate to be 0.05 μm or more and 0.2 μm or less, as taught by Matsuki, in order to secure a high drain-source breakdown voltage regardless of a depth of the source region (Matsuki: [0010] and [0045]).
Regarding claim 16, Wakimoto discloses the silicon carbide semiconductor device according to claim 1.
Wakimoto does not disclose the second conductivity type region terminates so as not to extend from a side wall of one trench portion to a side wall of another trench portion adjacent thereto in an arrangement direction of the plurality of trench portions.
Matsuki teaches in Fig. 4 and related text the second conductivity type region (6; [0043]) terminates so as not to extend from a side wall of one trench portion to a side wall of another trench portion adjacent thereto in an arrangement direction of the plurality of trench portions (7; [0022] and [0043]).
Wakimoto and Matsuki are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Wakimoto with the specified features of Matsuki because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form the second conductivity type region to terminate so as not to extend from a side wall of one trench portion to a side wall of another trench portion adjacent thereto in an arrangement direction of the plurality of trench portions, as taught by Matsuki, in order to secure a high drain-source breakdown voltage regardless of a depth of the source region (Matsuki: [0010] and [0045]).
Regarding claim 17, Wakimoto discloses the silicon carbide semiconductor device according to claim 2.
Wakimoto does not disclose the second conductivity type region terminates so as not to extend from a side wall of one trench portion to a side wall of another trench portion adjacent thereto in an arrangement direction of the plurality of trench portions.
Matsuki teaches in Fig. 4 and related text the second conductivity type region (6; [0043]) terminates so as not to extend from a side wall of one trench portion to a side wall of another trench portion adjacent thereto in an arrangement direction of the plurality of trench portions (7; [0022] and [0043]).
Wakimoto and Matsuki are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Wakimoto with the specified features of Matsuki because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form the second conductivity type region to terminate so as not to extend from a side wall of one trench portion to a side wall of another trench portion adjacent thereto in an arrangement direction of the plurality of trench portions, as taught by Matsuki, in order to secure a high drain-source breakdown voltage regardless of a depth of the source region (Matsuki: [0010] and [0045]).
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wakimoto in view of US 2016/0163854 A1 (hereinafter “Nishimura”).
Regarding claim 19, Wakimoto discloses the silicon carbide semiconductor device according to claim 1.
Wakimoto does not disclose the source region faces the contact region with the trench portion sandwiched therebetween, and the contact region faces the source region with the trench portion sandwiched therebetween.
Nishimura teaches in Fig. 10 and related text the source region (34; [0092]) faces the contact region (33 (33a, 33b); [0091]-[0092]) with the trench portion (25; [0091]) sandwiched therebetween, and the contact region faces the source region with the trench portion sandwiched therebetween.
Wakimoto and Nishimura are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Wakimoto with the specified features of Nishimura because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form the source region to face the contact region with the trench portion sandwiched therebetween, and to form the contact region to face the source region with the trench portion sandwiched therebetween, as taught by Nishimura, in order to cause the current flowing through the semiconductor device to flow substantially uniformly between unit cells which are adjacent to each other (Nishimura: [0094]).
Allowable Subject Matter
Claims 5 and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art of record, individually or in combination, does not teach or suggest “a width of the second conductivity type region in an extending direction of the plurality of trench portions is greater than a width of the source region in the extending direction of the plurality of trench portions” as recited in claim 5, and “a distance between the contact region and the second conductivity type region in an extending direction of the trench portions is greater than a distance between the first body region and the trench bottom region in an arrangement direction of the trench portions” as recited in claim 12.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER M ALBRECHT whose telephone number is (571)272-7813. The examiner can normally be reached M-F 9:30 AM - 6:30 PM (CT).
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/PETER M ALBRECHT/Primary Examiner, Art Unit 2811