Prosecution Insights
Last updated: July 17, 2026
Application No. 18/491,832

MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

Non-Final OA §103
Filed
Oct 23, 2023
Priority
Nov 10, 2021 — JP 2021-183645 +1 more
Examiner
GARCES, NELSON Y
Art Unit
2814
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Fuji Electric Co., Ltd.
OA Round
1 (Non-Final)
80%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
83%
With Interview

Examiner Intelligence

Grants 80% — above average
80%
Career Allowance Rate
471 granted / 587 resolved
+12.2% vs TC avg
Minimal +3% lift
Without
With
+2.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
28 currently pending
Career history
631
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
76.6%
+36.6% vs TC avg
§102
15.9%
-24.1% vs TC avg
§112
5.6%
-34.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 587 resolved cases

Office Action

§103
DETAILED ACTION This action is responsive to the application No. 18/491,832 filed on October 23, 2023. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant's election without traverse of the Group I invention and Species 2 disclosed in Fig. 7 in the reply filed on 04/02/2026 is acknowledged. The Applicants indicated that claims 12-22 read on the elected species. Claims 1-11 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Accordingly, pending in this Office action are claims 1-22. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 12 and 15-19 are rejected under 35 U.S.C. 103 as being unpatentable over Naito (US 2018/0350962) in view of Toyoji (JP 2021/034400). Regarding Claim 12, Naito (see, e.g., Figs. 2, 9), teaches a semiconductor device, comprising: a semiconductor substrate 10 having a transistor portion 70 and a diode portion 80 (see, e.g., pars. 0029, 0050); and an interlayer dielectric film 38 arranged on a front surface of the semiconductor substrate 10, a contact hole 54 being provided so as to penetrate through the interlayer dielectric film 38 (see, e.g., par. 0032), wherein the semiconductor substrate 10 has a lifetime control region 36 formed from the front surface of the semiconductor substrate 10, from the diode portion 70 across at least a portion of the transistor portion 80 (see, e.g., par. 0066), a TiN layer 62 is provided in contact with the interlayer dielectric film 38 (see, e.g., par. 0094). Naito does not teach that a Ti silicide layer is provided at a bottom surface of the contact hole. Toyoji (see, e.g., Fig. 1), in similar semiconductor devices to Naito, on the other hand, teaches that a Ti silicide layer 14 is provided at a bottom surface of the contact hole 11a, to reduce the contact resistance between the semiconductor substrate 9 and the titanium film 12, thus, providing an ohmic contact (see, e.g., pars. 0008, 0055, 0057). It would have been obvious to one of ordinary skill in the art at the time of filing to include in Naito’s device, a Ti silicide layer provided at a bottom surface of the contact hole, as taught by Toyoji, to reduce the contact resistance between the semiconductor substrate and the titanium film. Regarding Claim 15, Naito and Toyoji teach all aspects of claim 12. Naito (see, e.g., Figs. 2. 9), teaches that the TiN layer 62 covers an entire surface of the side wall of the contact hole 54. Regarding Claim 16, Naito and Toyoji teach all aspects of claim 12. Toyoji (see, e.g., Fig. 1), teaches that the TiN layer 13 is further provided at an upper surface of the Ti silicide layer 14 (see, e.g., par. 0057). Regarding Claim 17, Naito and Toyoji teach all aspects of claim 12. Toyoji is silent with respect to the claim limitation that a thickness of the Ti silicide layer 14 is 10 nm or more and 100 nm or less. However, this claim limitation is merely considered a change in the thickness of the Ti silicide layer in Naito’s/Toyoji’s device. The specific claimed thickness, absent any criticality, is only considered to be an obvious modification of the thickness of the Ti silicide layer in Naito’s/Toyoji’s device, as the courts have held that changes in thickness without any criticality, are within the level of skill in the art. According to the courts, a particular thickness is nothing more than one among numerous thicknesses that a person having ordinary skill in the art will find obvious to provide using routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Accordingly, since the applicant has not established the criticality (see next paragraph below) of the claimed Ti silicide thickness, it would have been obvious to one of ordinary skill in the art at the time of filing to have the claimed thickness in Naito’s/Toyoji’s device. CRITICALITY The specification contains no disclosure of either the critical nature of the claimed Ti silicide thickness or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen thickness or upon another variable recited in a claim, the applicant must show that the chosen thickness is critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990). Regarding Claim 18, Naito and Toyoji teach all aspects of claim 17. Toyoji is silent with respect to the claim limitation that a thickness of the Ti silicide layer 14 is 20 nm or more and 30 nm or less. However, this claim limitation is merely considered a change in the thickness of the Ti silicide layer in Naito’s/Toyoji’s device. See also the comments stated above in claim 17 regarding criticality of thicknesses which are considered repeated here. Regarding Claim 19, Naito and Toyoji teach all aspects of claim 12. Toyoji (see, e.g., Fig. 1, teaches that the contact hole 11a may have a tapered cross-sectional shape that widens as it moves away from the semiconductor substrate 9 (see, e.g., par. 0052). Toyoji is silent with respect to the claim limitation that a taper angle of the contact hole is 80 degrees or more and less than 90 degrees. However, this claim limitation is merely considered a change in the taper angle of the contact hole in Naito’s/Toyoji’s device. See also the comments stated above in claim 17 regarding criticality which are considered repeated here. Claims 13 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Naito (US 2018/0350962) in view of Toyoji (JP 2021/034400) and further in view of Lee (US 2015/0147880). Regarding Claim 13, Naito and Toyoji teach all aspects of claim 12. Toyoji (see, e.g., Fig. 1), teaches that the TiN layer has a first Ti layer 12 provided in contact with the side wall of the contact hole 11a, and a second TiN layer 13 different from the first Ti layer 12 which is provided so as to cover the first Ti layer 12 in the side wall of the contact hole 11a (see, e.g., pars. 0053-0054). Naito and Toyoji do not teach that the TiN layer has a first TiN layer and a second TiN layer different from the first TiN layer. Naito and Toyoji disclose the claimed invention except for the use of Ti instead of TiN. Lee (see, e.g., Fig. 14, par. 0041), on the other hand teaches that TiN and Ti are equivalent materials known in the art. Therefore, because these conductive materials were art-recognized equivalents at the time of the invention, one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, one of ordinary skill in the art would have found it obvious to substitute TiN for Ti since the substitution would yield predictable results. See Supreme Court decision in KSR International Co. v. Teleflex Inc., 550 U.S. _, 82 YSPQ2d 1385 (2007). Regarding Claim 14, Naito, Toyoji, and Lee teach all aspects of claim 13. Toyoji (see, e.g., Fig. 1), teaches that the second TiN layer 13 is provided at an upper surface of the Ti silicide layer 14 (see, e.g., pars. 0054, 0057). Claims 20-22 are rejected under 35 U.S.C. 103 as being unpatentable over Naito (US 2018/0350962) in view of Toyoji (JP 2021/034400) and further in view of Suzawa (US 2020/0051852). Regarding Claim 20, Naito and Toyoji teach all aspects of claim 12. They do not teach that the contact hole has a first portion on a side of the front surface of the semiconductor substrate, and a second portion which is positioned on the first portion, wherein the second portion has a taper angle different from that of the first portion. Suzawa (see, e.g., Fig. 9 and Annotated Fig. 7), on the other hand, teaches that the contact hole 14 has a first portion 14b on a side of the front surface of the semiconductor substrate 10, and a second portion 14a which is positioned on the first portion 14b, wherein the second portion 14a has a taper angle β2 different from that β1 of the first portion 14b, so that the barrier metal 15 may be formed having a uniform thickness and the barrier metal 15 does not grow thick at portions (see, e.g., par. 0092). PNG media_image1.png 402 488 media_image1.png Greyscale It would have been obvious to one of ordinary skill in the art at the time of filing to include in Naito’s/Toyoji’s device, the contact hole having a first portion on a side of the front surface of the semiconductor substrate, and a second portion which is positioned on the first portion, wherein the second portion has a taper angle different from that of the first portion, as taught by Suzawa, so that the barrier metal may be formed having a uniform thickness and the barrier metal does not grow thick at portions. Regarding Claim 21, Naito, Toyoji, and Suzawa teach all aspects of claim 20. Suzawa (see, e.g., Fig. 9), teaches that the interlayer dielectric film 13 has a stacked structure with a first layer 11 and a second layer 12 stacked on the first layer 11, wherein the second layer 12 corresponds to the second portion 14a and is formed of a material different from that of the first layer 11 corresponding to the first portion 14b (see, e.g., pars. 0061, 0080). Regarding Claim 22, Naito, Toyoji, and Suzawa teach all aspects of claim 21. Suzawa (see, e.g., Fig. 9), teaches that the first layer 11 is an HTO film (see, e.g., par. 0061). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nelson Garces whose telephone number is (571) 272-8249. The examiner can normally be reached on Mon-Fri 9:00 AM-5:30 PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Wael Fahmy can be reached on (571) 272-1705. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Nelson Garces/Primary Examiner, Art Unit 2814
Read full office action

Prosecution Timeline

Oct 23, 2023
Application Filed
Apr 23, 2026
Non-Final Rejection mailed — §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
80%
Grant Probability
83%
With Interview (+2.7%)
2y 5m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 587 resolved cases by this examiner. Grant probability derived from career allowance rate.

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