Prosecution Insights
Last updated: April 19, 2026
Application No. 18/492,027

Power Semiconductor Module Arrangement

Non-Final OA §102§103
Filed
Oct 23, 2023
Examiner
FOX, BRANDON C
Art Unit
2818
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Infineon Technologies AG
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
2y 5m
To Grant
96%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allow Rate
686 granted / 800 resolved
+17.8% vs TC avg
Moderate +10% lift
Without
With
+10.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
24 currently pending
Career history
824
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
56.9%
+16.9% vs TC avg
§102
33.9%
-6.1% vs TC avg
§112
5.9%
-34.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 800 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This is a Non-Final office action based on application 18/492,027 filed October 23, 2023. Claims 1-15 are currently pending and have been considered below. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-5, 12-13 & 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tian (Chinese Publication 113270373). Regarding claim 1, Tian discloses a power device comprising: a housing (Fig. 3, 12); a substrate (60) arranged in or forming a bottom of the housing, the substrate comprising a copper clad ceramic layer therefore including dielectric insulation layer and a first metallization layer attached to the dielectric insulation layer (Paragraph [0035]); a semiconductor arrangement (70) arranged on the substrate; and a plurality of bus bars (21, 22, 31, 32) electrically coupled to each other by the semiconductor arrangement and/or the first metallization layer, each of the plurality of bus bars comprising a first end, a second end opposite the first end, a first surface having a first outline, and a second surface opposite the first surface, the second surface having a second outline that is a projection of the first outline (Fig. 3 & 6), wherein the first end of each of the plurality of bus bars is electrically and mechanically coupled to the substrate, and the second end of each of the plurality of bus bars extends to the outside of the housing (Fig. 4), wherein each of the plurality of bus bars comprises a metal sheet (Paragraph [0047]), wherein the outline of the first surface of a bus bar is identical to the outline of the first surface of each of the other bus bars of the plurality of bus bars (Fig. 6). Regarding claim 2, Tian further discloses: each of the plurality of bus bars is bent at least once along its length (Fig. 6). Regarding claim 3, Tian further discloses: each of the plurality of bus bars comprises at least one horizontal section and at least one of one or more vertical sections or one or more diagonal sections (Fig. 6). Regarding claim 4, Tian further discloses: wherein the plurality of bus bars comprises at least four bus bars (21, 22, 31, 32), wherein a first bus bar and a second bus bar of the at least four bus bars are coupled to the substrate such that the first surface of both the first bus bar and the second bus bar faces toward the substrate and the second surface of both the first bus bar and the second bus bar faces away from the substrate, and wherein a third bus bar and a fourth bus bar of the at least four bus bars are coupled to the substrate such that the second surface of both the third bus bar and the fourth bus bar face toward the substrate and the first surface of both the third bus bar and the fourth bus bar face away from the substrate (Fig. 3 & 6). Regarding claim 5, Tian further discloses: wherein the first metallization layer comprises at least three separate sections (60, 91, 92), wherein the first bus bar (31) and the third bus bar (32) are coupled to a first section of the first metallization layer, wherein the second bus bar (21) is coupled to a third section of the first metallization layer, and wherein the fourth bus bar (22) is coupled to a second section of the first metallization layer. Regarding claim 12, Tian further discloses: a shape of a bus bar of the plurality of bus bars defined by the outline of the first surface is asymmetric (Fig. 6). Regarding claim 13, Tian further discloses: each of the plurality of bus bars has a same thickness, and wherein the thickness corresponds to a distance between the first surface and the second surface (Fig. 6). Regarding claim 15, Tian further discloses: each of the plurality of bus bars further comprises legs extending from the metal sheet, and wherein the legs are arranged at or form the first end of the bus bar and are electrically and mechanically connected to the substrate (Fig. 4). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 6-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tian (Chinese Publication 113270373) in view of Nishiyama (Pre-Grant Publication 2018/0342440). Regarding claim 6 & 8, Tian further discloses: a first switching element (Fig. 3 & 10, 70) arranged on the second section of the first metallization layer; and a second switching element (70) arranged on the first section of the first metallization layer, wherein the fourth bus bar (21) is configured to be operatively coupled to a first electrical potential and the second bus bar (22) is configured to be operatively coupled to a second electrical potential, wherein the first bus bar (31) and the third bus bar (32) are configured to be coupled to an output potential (Paragraph [0030]), wherein each of the first switching element and the second switching element comprises a control terminal and a controllable load path between two load terminals, the load paths of the first switching element and the second switching element being operatively coupled in series and between the first electrical potential and the second electrical potential (Fig. 10 & Paragraph [0045]). Wherein the first switching element and the second switching element are operatively coupled with each other (Fig. 10). Tian does not disclose the output potential via a first common node or wherein the first bus bar and the third bus bar are arranged adjacent to each other, wherein a shortest distance between the first bus bar and the third bus bar in a horizontal direction is between 1 and 60mm, between 1 and 10mm, or between 3 and 7mm, wherein the second bus bar and the fourth bus bar are arranged adjacent to each other, wherein a shortest distance between the second bus bar and the fourth bus bar in a horizontal direction is between 1 and 60mm, between 1 and 10mm, or between 3 and 7mm. However Nishiyama discloses an electronic device comprising: A circuit configuration (Fig. 1) comprising a switching elements couple din series wherein the switching elements include a common output node. Nishiyama further discloses a pair of busbar (Fig. 4, NTE & PTE) wherein the busbar are adjacent to each other and spaced apart a shortest distance in a horizontal direction of 8.8mm (Paragraph [0153]). It would have been obvious to those having ordinary skill in the art at the time of invention to form the circuit configuration to have a common output node because it will simplify the circuitry. Further by having a pair of busbars separate by a distance of 8.8mm will serve to improved dielectric strength by increasing creepage distance between the busbars (Paragraph [0153]). Regarding claim 7, Tian further discloses: wherein the first switching element comprises at least one IGBT, at least one MOSFET, at least one JFET, or at least one HEMT, and/or wherein the second switching element comprises at least one IGBT, at least one MOSFET, at least one JFET, or at least one HEMT (Paragraph [0045]). Allowable Subject Matter Claims 9-11 & 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Claim 9 is considered allowable because none of the prior art either alone or in combination discloses a sensor element arranged between the first bus bar and the third bus bar and configured to detect a strength of a magnetic field caused by a first current flowing through the first bus bar and a second current flowing through the third bus bar, wherein the detected strength of the magnetic field is indicative of a sum of the first current and the second current. Claim 10 is considered allowable because none of the prior art either alone or in combination discloses a sensor element arranged between the second bus bar and the fourth bus bar and configured to detect a strength of a magnetic field caused by a third current flowing through the second bus bar and a fourth current flowing through the fourth bus bar, wherein the detected strength of the magnetic field is indicative of a sum of the third current and the fourth current. Claim 11 is considered allowable because none of the prior art either alone or in combination discloses a sensor element, wherein each of the at least four bus bars comprises an opening formed in the metal sheet and extending from the first surface to the second surface, and wherein the sensor element is arranged in the opening of the second bus bar or in the opening of the fourth bus bar. Claim 14 is considered allowable because none of the prior art either alone or in combination discloses wherein a maximum length of each of the plurality of bus bars is at least 10 times larger, at least 30 times larger, or at least 50 times larger than a thickness of the respective bus bar, wherein a maximum width of each of the plurality of bus bars is at least 5 times, at least 10 times, or at least 30 times larger than the thickness of the respective bus bar, and wherein the maximum length of each of the plurality of bus bars is larger than the maximum width of the respective bus bar. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRANDON C FOX whose telephone number is (571)270-5016. The examiner can normally be reached M-F 9:00AM-6:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff W Natalini can be reached at 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /BRANDON C FOX/Examiner, Art Unit 2818 /DAVID VU/Primary Examiner, Art Unit 2818
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Prosecution Timeline

Oct 23, 2023
Application Filed
Jan 23, 2026
Non-Final Rejection — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
96%
With Interview (+10.0%)
2y 5m
Median Time to Grant
Low
PTA Risk
Based on 800 resolved cases by this examiner. Grant probability derived from career allow rate.

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