DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 7-8, 10-11, 20-21, and 23-24 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Suk et al. (US 2025/0062208 A1; hereinafter “Suk”).
Regarding claim 7, Suk teaches a method of making a semiconductor device, comprising: providing a first bridge die (153) (Fig. 14 and paragraphs 47 and 99-100); depositing an encapsulant (167) over the first bridge die (Fig. 16 and paragraphs 101-104); forming a first interconnect structure (170) over the first bridge die and the encapsulant (Fig. 17 and paragraphs 105-106); and mounting a second bridge die (253) onto the first interconnect structure opposite the first bridge die and the encapsulant (Figs. 4 and 14 and paragraphs 65 and 100).
Regarding claim 8, Suk teaches further including forming a second interconnect structure (120) on the encapsulant opposite the first interconnect structure (paragraphs 90-91).
Regarding claim 10, Suk teaches further including forming a conductive pillar or conductive via (166) through the encapsulant from the first interconnect structure to the second interconnect structure (paragraph 49).
Regarding claim 11, Suk teaches further including: disposing a first semiconductor die (250) over the second interconnect structure within a footprint of the first bridge die (a footprint of 153) (Fig. 4 and paragraph 65); and disposing a second semiconductor die (251) over the second interconnect structure within the footprint of the first bridge die (Fig. 4 and paragraph 65).
Regarding claim 20, referring to Fig. 4 and related text, Suk teaches a semiconductor device, comprising: a first bridge die (153) (paragraphs 47 and 63-65); an encapsulant (167) deposited over the first bridge die (paragraphs 101-104); a first interconnect structure (170) disposed over the first bridge die and the encapsulant (paragraphs 105-106); and a second bridge die (253) mounted onto the first interconnect structure opposite the first bridge die and the encapsulant (paragraphs 65, 86, and 100).
Regarding claim 21, Suk teaches further including a second interconnect structure (120) formed on the encapsulant opposite the first interconnect structure (paragraphs 90-91).
Regarding claim 23, Suk teaches further including a conductive pillar or conductive via (166) formed through the encapsulant from the first interconnect structure to the second interconnect structure (paragraph 49).
Regarding claim 24, teaches further including: a first semiconductor die (250) disposed over the second interconnect structure within a footprint of the first bridge die (a footprint of 153) (Fig. 4 and paragraph 65); and a second semiconductor die (251) disposed over the second interconnect structure within the footprint of the first bridge die (Fig. 4 and paragraph 65).
Claims 1-5, 7-12, 14-18, and 20-25 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Yim (US 2025/0096098 A1).
Regarding claim 1, Yim teaches a method of making a semiconductor device, comprising: providing a first interconnect structure (110) (Fig. 7 and paragraphs 101-102); disposing a first bridge die (140 bridging between 110 and 150) over the first interconnect structure (Fig. 8 and paragraphs 48-50 and 103-104); depositing an encapsulant (159) over the first bridge die (Fig. 8 and paragraphs 47-48); forming a second interconnect structure (150) over the first bridge die and the encapsulant, wherein the first bridge die is directly electrically coupled to the second interconnect structure (Fig. 8 and paragraphs 47-48); and mounting a second bridge die (210) onto the second interconnect structure opposite the first bridge die and the encapsulant (Fig. 11 and paragraphs 67 and 109-110).
Regarding claim 2, Yim teaches forming a conductive via (142) through the first bridge die (paragraph 50).
Regarding claim 3, Yim teaches further including forming a conductive pillar or conductive via (145) through the encapsulant from the first interconnect structure to the second interconnect structure (paragraph 58).
Regarding claim 4, Yim teaches further including: disposing a first semiconductor die (230) over the second interconnect structure within a footprint of the first bridge die (a footprint of 140) (Fig. 12 and paragraphs 111-112); and disposing a second semiconductor die (240) over the second interconnect structure within the footprint of the first bridge die (Fig. 12 and paragraphs 111-112).
Regarding claim 5, Yim teaches further including disposing a third semiconductor die (250) over the second interconnect structure with the second bridge die between the first semiconductor die and the third semiconductor die (Fig. 12 and paragraphs 111-112).
Regarding claim 7, Yim teaches a method of making a semiconductor device, comprising: providing a first bridge die (140 bridging between 110 and 150) (Fig. 8 and paragraphs 48-50 and 103-104); depositing an encapsulant (159) over the first bridge die (Fig. 8 and paragraphs 47-48); forming a first interconnect structure (150) over the first bridge die and the encapsulant (Fig. 8 and paragraphs 47-48); and mounting a second bridge die (210) onto the first interconnect structure opposite the first bridge die and the encapsulant (Fig. 11 and paragraphs 67 and 109-110).
Regarding claim 8, Yim teaches further including forming a second interconnect structure (110) on the encapsulant opposite the first interconnect structure (Fig. 7 and paragraphs 101-102).
Regarding claim 9, Yim teaches forming a conductive via (142) through the first bridge die (paragraph 50).
Regarding claim 10, Yim teaches further including forming a conductive pillar or conductive via (145) through the encapsulant from the first interconnect structure to the second interconnect structure (paragraph 58).
Regarding claim 11, Yim teaches further including: disposing a first semiconductor die (230) over the second interconnect structure within a footprint of the first bridge die (a footprint of 140) (Fig. 12 and paragraphs 111-112); and disposing a second semiconductor die (240) over the second interconnect structure within the footprint of the first bridge die (Fig. 12 and paragraphs 111-112).
Regarding claim 12, Yim teaches further including disposing a third semiconductor die (250) over the second interconnect structure with the second bridge die between the first semiconductor die and the third semiconductor die (Fig. 12 and paragraphs 111-112).
Regarding claim 14, referring to Fig. 1 and related text, Yim teaches a semiconductor device, comprising: a first interconnect structure (110) (paragraphs 37-39); a first bridge die (140 bridging between 110 and 150) disposed over the first interconnect structure (paragraphs 48-50); an encapsulant (159) deposited over the first bridge die (paragraphs 47-49); a second interconnect structure (150) disposed over the first bridge die and the encapsulant, wherein the first bridge die is directly electrically coupled to the second interconnect structure (paragraphs 47-48); and a second bridge die (210) mounted to the second interconnect structure opposite the first bridge die and the encapsulant (paragraphs 64-67).
Regarding claim 15, Yim teaches further including a conductive via (142) formed through the first bridge die (paragraph 50).
Regarding claim 16, Yim teaches further including forming a conductive pillar or conductive via (145) through the encapsulant from the first interconnect structure to the second interconnect structure (paragraph 58).
Regarding claim 17, Yim teaches further including: a first semiconductor die (230) disposed over the second interconnect structure within a footprint of the first bridge die (a footprint of 140) (Fig. 1 and paragraph 64); and a second semiconductor die (240) disposed over the second interconnect structure within the footprint of the first bridge die (Fig. 1 and paragraph 64).
Regarding claim 18, Yim teaches further including a third semiconductor die (250) disposed over the second interconnect structure with the second bridge die between the first semiconductor die and the third semiconductor die (Fig. 1 and paragraph 64).
Regarding claim 20, referring to Fig. 1 and related text, Yim teaches a semiconductor device, comprising: a first bridge die (140 bridging between 110 and 150) (paragraphs 48-50); an encapsulant (159) deposited over the first bridge die (paragraphs 47-48); a first interconnect structure (150) disposed over the first bridge die and encapsulant (paragraphs 47-48); and a second bridge die (210) disposed over the first interconnect structure (paragraphs 64-67).
Regarding claim 21, Yim teaches further including forming a second interconnect structure (110) on the encapsulant opposite the first interconnect structure (Fig. 7 and paragraphs 101-102).
Regarding claim 22, Yim teaches forming a conductive via (142) through the first bridge die (paragraph 50).
Regarding claim 23, Yim teaches further including forming a conductive pillar or conductive via (145) through the encapsulant from the first interconnect structure to the second interconnect structure (paragraph 58).
Regarding claim 24, Yim teaches further including: a first semiconductor die (230) disposed over the second interconnect structure within a footprint of the first bridge die (a footprint of 140) (Fig. 1 and paragraph 64); and a second semiconductor die (240) disposed over the second interconnect structure within the footprint of the first bridge die (Fig. 1 and paragraph 64).
Regarding claim 25, Yim teaches further including a third semiconductor die (250) disposed over the second interconnect structure with the second bridge die between the first semiconductor die and the third semiconductor die (Fig. 1 and paragraph 64).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Suk as applied to claims 7 and 20 above, and further in view of Chen et al. (US 2025/0054926 A1; hereinafter “Chen”).
Regarding claims 9 and 22, Suk does not explicitly teach a conductive via through the first bridge die (153). Chen teaches a semiconductor device (Fig. 12 and paragraph 36), comprising: a conductive via (105) formed through a first bridge die (120) in order to be electrically connected to the underlying and overlying interconnect structures and to provide an electrical connection between semiconductor dies (Fig. 12 and paragraphs 14 and 36). Therefore, it would have been obvious to one of ordinary skill in the art to combine the teaching of Suk with that of Chen in order to be electrically connected to the underlying and overlying interconnect structures and to provide an electrical connection between semiconductor dies.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Suk.
Regarding claim 13, Suk teaches that the first bridge die (153) includes a second interconnect structure (163) having line spacing or line width is about 0.1 μm to about 50 μm (a line spacing of 163, which is W2, is about 0.1 μm to about 50 μm) (Fig. 2 and paragraphs 47 and 58), which is overlapping the claimed range of less than two microns. As such, it would have been obvious to one of ordinary skill in the art to adjust the line spacing or line width from Suk teaching the overlapping range to obtain the optimum and/or workable range, including the claimed range of less than two microns. See MPEP 2144.05 for overlap of ranges.
Claims 6, 13, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Yim.
Regarding claim 13, Yim teaches that the first bridge die (140) includes a second/third interconnect structure (143) having line spacing or line width (Fig. 1 and paragraph 48). While Yim does not explicitly teach the line spacing or line width less than two microns, it would have been obvious to one of ordinary skill in the art to adjust the line spacing or line width from Yim by a routine experimentation in order to obtain the optimum and/or workable range, including the claimed range of less than two microns: It has held that discovering an optimum or workable ranges involves only routine skill in the art. Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation. In re Aller, 105 USPQ 233.
Response to Arguments
Applicant’s arguments with respect to amended claims have been considered but are moot in view of new grounds of rejections as set forth above in this Office Action.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL B WHALEN whose telephone number is (571)270-3418. The examiner can normally be reached on M-F: 8AM-5PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached on (571)272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DANIEL WHALEN/Primary Examiner, Art Unit 2893
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