DETAILED ACTION
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 10/23/23 and 8/18/25 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 12-14, and 17 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 4, 11, 12, and 15 of copending Application No. 19/287,081 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other as detailed below.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Instant claims
‘081 claims
reasoning
1
4
Substantially similar except that the instant claim recites pull-up (PU) and pull-down (PD) transistors while the ‘081 claim recites generic transistors. However, both applications are directed to an SRAM device, so PU and PD transistors are obvious. Also the instant claim states the contact via is coupled to the source/drain whereas the ‘081 claim states the contact via is coupled to the source/drain contact, which is coupled to the source/drain. Thus, the ’081 claim is narrower in scope and this limitation is anticipated.
12
11
Substantially similar. The instant claim has the limitation that the first or second via is larger than the third or fourth via, whereas the ‘081 claim states the first or second via has a length that is larger than the length of the third or fourth via. Thus, the ’081 claim is narrower in scope and this limitation is anticipated.
13
12
Substantially similar
14
11
anticipated
17
15
Substantially similar
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 5, 6, 9-14, and 17 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as anticipated by or, in the alternative, under 35 U.S.C. 103 as obvious over Liaw (US 2023/0052883).
As to claim 1, Liaw teaches a memory cell (see annotated fig. 4A below), comprising:
first and second active regions (106 and 108), wherein each of the first and second active regions (106 and 108) extends lengthwise in a first direction (Y-axis, [0025]);
first and second gate structures (130B), wherein each of the first and second gate structures (130B) extends lengthwise in a second direction (X-axis) that is perpendicular to the first direction, the first gate structure (130B) engages the first and second active regions (106 and 108) in forming a first pull-down transistor (PD-1) and a first pull-up transistor (PU-1), respectively, and the second gate structure (130B) engages the first and second active regions (106 and 108) in forming a second pull-down transistor (PD-2) and a second pull-up transistor (PU-2), respectively ([0030], see annotated fig. 4A below);
a first source/drain contact via (126A) electrically coupled to a first common source/drain of the first and second pull-down transistors ([0036]);
a second source/drain contact via (126D) electrically coupled to a second common source/drain of the first and second pull-up transistors ([0036]);
a first gate contact (122) electrically coupled to the first gate structure (130B, not shown in fig. 2A, [0033]); and
a second gate contact (122) electrically coupled to the second gate structure (130B, not shown in fig. 2A, [0033]),
wherein one of the first and second source/drain contact vias has an area larger than either of the first and second gate contacts in a top view of the memory cell ([0036] – [0037], the S/D contact via 126A has a greater area than other S/D contact vias 126b-126D, which corresponds to the width W1 of the active region 106. As can be seen in fig. 2A below, the S/D contact via 126A is larger than a different gate contact 122, but obvious if not inherent that the gate contacts would be the same size.).
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As to claim 2, Liaw further teaches the first source/drain contact via (126A) electrically couples to an electrical ground (CVSS) of the memory cell, and the second source/drain contact via electrically couples to a power supply (CVDD) of the memory cell ([0031], one is high and the other is low).
As to claim 5, Liaw further teaches the first (126A) and second (126D) source/drain contact vias have different areas ([0036]).
As to claim 6, Liaw does not explicitly teach the first source/drain contact via includes a material composition different from the second source/drain contact via. However, using different materials would have been obvious so as to adjust resistance values.
As to claim 9, Liaw further teaches the one of the first and second source/drain contact (126A) vias extends beyond opposing edges of the memory cell along the first direction (beyond the dotted line in the X direction, fig. 2A).
As to claim 10, Liaw further teaches the one of the first and second source/drain contact vias (126A) includes a jog portion with a width larger than other portions of the one of the first and second source/drain contact vias (Fig. 2A, 126A is larger than 126D).
As to claim 11, Liaw further teaches the first gate contact electrically couples to a storage node of the memory cell, and the second gate contact electrically couples to a complimentary storage node of the memory cell ([0031]).
As to claim 12, Liaw teaches a memory cell (see annotated fig. 2A below), comprising:
first and second active regions (106 and 108), wherein each of the first and second active regions (106 and 108) extends lengthwise in a first direction (Y-axis, [0025]);
first and second gate structures (130B), wherein each of the first and second gate structures (130B) extends lengthwise in a second direction (X-axis) that is different from the first direction ([0030], see annotated fig. 4A below);
a first contact (120A) disposed on the first active region and between the first and second gate structures ([0035]);
a first contact via (126A) disposed on the first contact and electrically connected to the first contact ([0036]);
a second contact (120D) disposed on the second active region and between the first and second gate structures ([0035]);
a second contact via (126D) disposed on the second contact and electrically connected to the second contact ([0036]);
a third contact (120C) disposed on both of the first and second active regions (see fig. below, ([0035]);
a fourth contact (120C) disposed on both of the first and second active regions, wherein the first and second gate structures are between the third and fourth contacts along the first direction (see fig. below, [0035]);
a third contact via (126B, not shown but described) disposed on the third contact and electrically connected to the third contact ([0036]); and
a fourth contact via (126C, not shown but described) disposed on the fourth contact and electrically connected to the fourth contact ([0036]),
wherein one of the first and second contact vias is larger than one of the third and fourth contact vias in a top view of the semiconductor device ([0036], 126A is larger than 126B-D).
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As to claim 13, Liaw further teaches the first contact via (126A) electrically couples to an electrical ground (CVSS) of the memory cell, and the second contact via electrically couples to a power supply (CVDD) of the memory cell ([0031], one is high and the other is low).
As to claim 14, Liaw further teaches a length of the one of the first and second contact vias measured in the first direction is larger than a width of a corresponding one of the first and second contacts measured in the first direction (126A is an ellipse, thus the major axis is larger than the minor axis).
As to claim 17, Liaw further teaches a metal line extending in the first direction and electrically connected to the one of the first and second contact vias, wherein the metal line and the one of the first and second contact vias substantially have a same width measured in the second direction (Obvious the metal line would have the same width so as to properly contact the vias while minimizing space used).
Allowable Subject Matter
Claims 18-20 are allowed and claims 3, 4, 7, 8, 15, and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and the DP rejection is overcome. The following is a statement of reasons for the indication of allowable subject matter: The prior art taken either singularly or in combination fails to anticipate or fairly suggest the limitations of the claims listed above in such a manner that a rejection under 35 U.S.C. 102 or 103 would be proper.
The prior art fails to teach a combination of all of the features in the claims. As to claim 3, Liaw fails to teach the first and second source/drain contact vias have a same area, and the first and second gate contacts have a same area. Liaw very specifically teaches only the first S/D contact 126A is larger than the other contacts (i.e. second S/D contact 126D).
As to claim 7, Liaw fails to teach the first and second gate structures have a gate pitch and a gate width, and a length of the one of the first and second source/drain contact vias measured in the first direction is larger than a sum of the gate pitch and the gate width.
As to claim 8, Liaw fails to teach a portion of the first and second gate structures is directly under the one of the first and second source/drain contact vias.
As to claim 15, Liaw fails to teach the length of the one of the first and second contact vias measured in the first direction is larger than a distance between two outward facing sidewalls of the first and second gate structures measured in the first direction.
As to claim 18, Liaw teaches a semiconductor device, comprising:
a device layer including a plurality of first transistors (PG-1 and (PG-2) in a write-port of a static random-access memory (SRAM) cell ([0032]) and at least a second transistor in a read-port of the SRAM cell;
a metal line layer (ML1) disposed on the device layer and electrically coupled to the first and second transistors in the device layer, wherein the metal line layer includes a power supply line, an electrical ground line, and a plurality of signal lines ([0033]);
a first contact via (126A) disposed between the device layer and the metal line layer, wherein the first contact via is electrically coupled to the power supply line (CVSS, [0031]);
a second contact via (126B) disposed between the device layer and the metal line layer, wherein the second contact via is electrically coupled to the electrical ground line (CVDD, [0031]); and
a plurality of third contact vias (126D) disposed between the device layer and the metal line layer ([0033]), wherein the third contact vias (126D) are electrically coupled to the signal lines ([0031]),
Liaw fails to teach each of the first and second contact vias (126A and 126B) has an area larger than any of the third contact vias (126D) in a top view of the semiconductor device. Only the first contact 126A has a larger area. Liaw specifically teaches the area of 126A is larger than those of 126B-126D ([0036]).
The remaining claims are allowable or allowed at least because they depend from allowable claims.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
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Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAREN M KUSUMAKAR whose telephone number is (571)270-3520. The examiner can normally be reached on Monday – Friday from 7:30a – 4:30p EST.
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/KAREN KUSUMAKAR/
Primary Examiner, Art Unit 2897
4/7/26
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