Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/23/2023 was filed after the mailing date of the first action on the merits. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-12, and 14-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over KR 20140041970 A, in view of NAKAMURA et al, US 20130313689 A1 and further in view of Brandenburg et al, US 20040113281 A1.
‘970 teaches:
a first semiconductor chip (100) comprising a substrate having a front surface (FS) and an opposite rear surface (BS), a rear protective layer (315) on the rear surface of the substrate, a plurality of first rear through-vias (400) penetrating through the rear protective layer and extending into the substrate, a plurality of second rear through-vias penetrating through the rear protective layer and extending into the substrate [In regards to the “plurality”, examiner only needs to demonstrate at least one (see In re Harza)] , a plurality of front through-vias (200) extending from the front surface of the substrate and connected to the plurality of first rear through-vias, and a plurality of rear pads (420) on the rear protective layer (315), wherein the plurality of rear pads (420) are connected to the plurality of first and second rear through-vias (200, 400);
a second semiconductor chip (140) on the first semiconductor chip (100), the second semiconductor chip comprising a plurality of front pads (155, 152, 162) electrically connected to the plurality of rear pads (420); and
wherein each of the plurality of first and second rear through-vias (200) has a width greater than a width of each of the plurality of front through-vias (151) (see figure 1g)
‘970 fails to teach:
a plurality of bump structures between the plurality of rear pads of the first semiconductor chip and the plurality of front pads of the second semiconductor chip; and
an adhesive layer surrounding the plurality of bump structures between the first semiconductor chip and the second semiconductor chip.
Nakamura teaches:
As shown in FIG. 2B, second seed film 27 formed by successively stacking titanium (Ti) and copper (Cu) is provided on the lower surface of front bump 28, and the upper surface of front bump 28 is covered by front plating layer 29 which is an alloy containing tin (Sn) as a main component. (para 28)
Brandenburg teaches:
For this purpose, the package 10 is equipped with a gate 46 and vent 48 through which a suitable polymeric material can be injected into the cavity 42 to form the compound 44. (figures 3-5), para 21
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the above references, because it is conventionally done in the art to electrically connect substrates through bump structures and fill the cavities to avoid voids or defects within the package.
Nakumara further teaches:
2. The semiconductor package of claim 1, wherein the first semiconductor chip
comprises a center region and a peripheral region around the center region,
wherein the plurality of first rear through-vias are in the center region and the plurality of second rear through-vias are in the peripheral region. See figures 2a and 2b, 5a and 5b
‘0970 further teaches:
3. The semiconductor package of claim 2, wherein the plurality of second rear
through-vias are electrically insulated from the plurality of front through-vias. See figure 1g.
4. The semiconductor package of claim 2, wherein the width of each of the
plurality of second rear through-vias is different from the width of each of the plurality of first rear through-vias. See figure 1g
5. The semiconductor package of claim 4, wherein the width of each of the plurality of second rear through-vias is greater than the width of each of the plurality of first rear through-vias. See figure 1g
6. The semiconductor package of claim 1, wherein the first semiconductor chip
further comprises a barrier insulating layer (210) extending between at least a portion of the plurality of first and second rear through-vias and the substrate. Figure 1g
7. The semiconductor package of claim 6, wherein the barrier insulating layer
comprises at least one of silicon oxide and silicon nitride. (para 12)
8. The semiconductor package of claim 6, wherein the barrier insulating layer is.
only between the plurality of first rear through-vias and the substrate. Figure 1g
9. The semiconductor package of claim 1, wherein the width of each of the plurality of first and second rear through-vias is in a range of about 5 µm to about 15 µm, and
wherein the width of each of the plurality of front through-vias is in a range of about 2 µm to about 8 µm.
In regards to the specific range of values, these range would have been determined through routine experimentation and would not lend themselves to patentability, in the instant application without displaying unexpected results. (in Re Aller)
10. The semiconductor package of claim 1, wherein each of the plurality of first
and second rear through-vias has a height smaller than a height of each of the plurality of front through-vias. See Figure 1 g
11. The semiconductor package of claim 10, wherein the height of each of the plurality of first and second rear through-vias is in a range of about 2 µm to about 10 µm.
In regards to the specific range of values, these range would have been determined through routine experimentation and would not lend themselves to patentability, in the instant application without displaying unexpected results. (in Re Aller)
12. The semiconductor package of claim 1, wherein the rear protective layer
comprises at least one of silicon oxide and silicon nitride. (para 16)
14. A semiconductor package, comprising:
‘970 teaches:
a plurality of semiconductor chips (100, 140) stacked in a first direction; and
wherein at least one of the plurality of semiconductor chips comprises:
a substrate (100) having a front surface (FS) and an opposite rear surface (BS);
a rear protective layer (315) on the rear surface of the substrate (100);
a plurality of rear pads (420) [In regards to the “plurality”, examiner only needs to demonstrate at least one (see In re Harza)] on the rear protective layer;
a plurality of rear through-vias (200) penetrating through the rear protective layer and
connected to the plurality of rear pads; Figure 1g
a front circuit layer (130) on the front surface of the substrate;
a plurality of front pads (155) on the front circuit layer, and
a plurality of front through-vias (151) extending from the front surface of the substrate to at least some of the plurality of rear through-vias, and electrically connected to at least some of the plurality of front pads. (figure 1g)
‘0970 fails to teach:
a plurality of bump structures between and electrically connecting adjacent ones of the
plurality of semiconductor chips; and
at least one adhesive layer surrounding the plurality of bump structures.
Nakamura teaches:
As shown in FIG. 2B, second seed film 27 formed by successively stacking titanium (Ti) and copper (Cu) is provided on the lower surface of front bump 28, and the upper surface of front bump 28 is covered by front plating layer 29 which is an alloy containing tin (Sn) as a main component. (para 28)
Brandenburg teaches:
For this purpose, the package 10 is equipped with a gate 46 and vent 48 through which a suitable polymeric material can be injected into the cavity 42 to form the compound 44. (figures 3-5), para 21
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the above references, because it is conventionally done in the art to electrically connect substrates through bump structures and fill the cavities to avoid voids or defects within the package.
Nakamura teaches:
15. The semiconductor package of claim 14, wherein the plurality of rear pads and
the plurality of front pads that are adjacent to each other in the first direction are electrically connected to each other by the plurality of bump structures. [In regards to the “plurality”, examiner only needs to demonstrate at least one (see In re Harza)]
16. The semiconductor package of claim 14, wherein, in the first direction, a
height of each of the plurality of rear through-vias is smaller than a height of each of the
plurality of front through-vias. (see figure 1g ‘970)
17. The semiconductor package of claim 14, wherein in a second direction that is
transverse to the first direction, a width of each of the plurality of rear through-vias is greater than a width of each of the plurality of front through-vias. (see figure 1g ‘970)
Brandenburg teaches:
18. The semiconductor package of claim 14, further comprising: a molding member encapsulating at least a portion of each of the plurality of
semiconductor chips. (see figure 3)
‘0970 teaches:
19. A semiconductor package, comprising:
a first semiconductor chip (100) comprising a substrate having a front surface and an
opposite rear surface, a rear protective layer (315) on the rear surface of the substrate, a plurality of rear through-vias (400) penetrating through the rear protective layer and extending into the substrate, [In regards to the “plurality”, examiner only needs to demonstrate at least one (see In re Harza)]
a plurality of front through-vias (200) extending from the front surface of the substrate and connected to the plurality of rear through-vias (400), and a plurality of rear pads (420) on the rear protective layer and connected to the plurality of rear through-vias (400);
a second semiconductor chip (140) on the first semiconductor chip, the second
semiconductor chip comprising a plurality of front pads (155, 152, 162) electrically connected to the plurality of rear pads;
wherein the plurality of rear through-vias comprise a plurality of first rear through-
vias electrically connected to the plurality of front through-vias, and a plurality of second rear through-vias electrically insulated from the plurality of front through-vias. (see figure 1g)
‘0970 fails to teach:
a plurality of bump structures between the plurality of rear pads of the first
semiconductor chip and the plurality of front pads of the second semiconductor chip;
an adhesive layer surrounding the plurality of bump structures between the first
semiconductor chip and the second semiconductor chip.
Nakamura teaches:
As shown in FIG. 2B, second seed film 27 formed by successively stacking titanium (Ti) and copper (Cu) is provided on the lower surface of front bump 28, and the upper surface of front bump 28 is covered by front plating layer 29 which is an alloy containing tin (Sn) as a main component. (para 28)
Brandenburg teaches:
For this purpose, the package 10 is equipped with a gate 46 and vent 48 through which a suitable polymeric material can be injected into the cavity 42 to form the compound 44. (figures 3-5), para 21
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the above references, because it is conventionally done in the art to electrically connect substrates through bump structures and fill the cavities to avoid voids or defects within the package.
‘0970 further teaches
20. The semiconductor package of claim 19, wherein a lower surface of each of the plurality of first rear through-vias comprises a recess portion in contact with an upper
surface of a respective one of the plurality of front through-vias. See figure 1g
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over KR 20140041970 A, in view of NAKAMURA et al, US 20130313689 A1 and further in view of Brandenburg et al, US 20040113281 A1.
The above references fail to teach:
13. The semiconductor package of claim 1, wherein the substrate comprises at
least one of a silicon and germanium.
Examiner takes official notice that it is well known in the art to form a substrate that comprises at least one of a silicon and germanium.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL LEBENTRITT whose telephone number is (571)272-1873. The examiner can normally be reached IFP Mon- Fri 8:30 am- 6 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at (571)272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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MICHAEL . LEBENTRITT
Primary Examiner
Art Unit 2893
/MICHAEL LEBENTRITT/Primary Examiner, Art Unit 2893