DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species D, claims 1-20 in the reply filed on 02/20/2026 is acknowledged.
Foreign Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. KR10-2023-0055096, filed on 04/27/2023.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/18/2024, 07/26/2024, and 10/23/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 9-13, and 15 are rejected under 35 U.S.C. 102 as being anticipated by Kim et al. ( US 2023/0011153 A1; hereinafter Kim )
Regarding claim 1, Kim teaches a semiconductor device ( Fig. 18 ), comprising: a substrate ( Fig. 18 substrate 100 ) that includes an active region ( Fig. 18 region of substrate that includes transistors ); an active pattern ( Fig. 18 first active pattern F1 or second active pattern F2 ) on the active region ( as discussed above ); a source/drain pattern ( Fig. 18 source/drain region 220 ) on the active pattern ( Fig. 18 F1 or F2 ); an active contact ( Fig. 18 first source/drain contact 250 ) that extends from a top surface of the source/drain pattern ( Fig. 18 #220 ) to a sidewall of the source/drain pattern ( as shown in Fig. 18 250_1 touches 220 ), wherein the active contact includes a first part ( Fig. 18 250_1 covering portions of element 220 except the top portion of element 220 ) that covers the sidewall of the source/drain pattern and a second part that covers the top surface of the source/drain pattern ( Fig. 18 part of 250_1 that covers the top portion of 220 ); a first layer ( Fig. 18 261 ) between the source/drain pattern ( Fig. 18 #220 ) and the first part ( as discussed above ); and a second layer ( Fig. 18 #263 ) separated from the first layer ( Fig. 18 #261 ) and across the first part ( Fig. 18 #263 is formed on both sides of #250_1 ), wherein each of the first layer ( Fig. 18 #261 ) and the second layer ( Fig. 18 #263 ) includes a silicide layer ( [0111] The first silicide layer 260 may include a first layer 261 disposed along the surface of the second doping layer 222, and a second layer 263 disposed between the first layer 261 and the first source/drain contact 250 ).
Regarding claim 2, Kim teaches the semiconductor device of claim 1 ( as discussed above ), wherein the first layer ( Fig. 18 #261 ) includes: a first silicon layer ( Fig. 18: second doping layer 222 ) that covers the top surface and opposite sidewalls ( [0124] For example, a part of the second doping layer 222 that is in contact with the pre silicide layer (30 of FIG. 26) may be silicidized to form the first layer 261) of the source/drain pattern ( Fig. 18 #220 ); and a first silicide layer ( Fig. 18: first silicide layer 260 ) on the first silicon layer ( Fig. 18 #222 ).
Regarding claim 3, Kim teaches the semiconductor device of claim 2 ( as discussed above ), wherein the first silicon layer ( Fig. 18 #222 ) has an impurity concentration that increases with decreasing distance ( [0112] The first layer 261 and the second layer 263 may include different materials from each other. The first layer 261 may include a material in which a part of the second doping layer 222 is silicidized. The second layer 263 may include a material in which silicon (Si) doped with the first impurity at a third concentration higher than the second concentration is silicidized ) from the silicide layer ( Fig. 18 #260 ).
Regarding claim 4, Kim teaches the semiconductor device of claim 1 ( as discussed above ), wherein the second layer ( Fig. 18 #263 ) includes: a second silicide layer ( Fig. 18 #263 ) that covers an outer sidewall of the first part ( Fig. 18 #250_1 ); and a second silicon layer ( Fig. 18 #222 ) on the second silicide layer ( Fig. 18 #263 ).
Regarding claim 9, Kim teaches the semiconductor device of claim 1 ( as discussed above ), wherein each silicide layer ( Fig. 18 #260 and #263 ) has an impurity concentration that increases with decreasing distance ( [0112] The first layer 261 and the second layer 263 may include different materials from each other. The first layer 261 may include a material in which a part of the second doping layer 222 is silicidized. The second layer 263 may include a material in which silicon (Si) doped with the first impurity at a third concentration higher than the second concentration is silicidized ) from the active contact ( Fig. 18 #250 ).
Regarding claim 10, Kim teaches a semiconductor device ( Fig. 18 ), comprising: a substrate ( Fig. 18 substrate 100 ) that includes an active region ( Fig. 18 region of substrate that includes transistors ); an active pattern ( Fig. 18 first active pattern F1 or second active pattern F2 ) on the active region ( as discussed above ); a source/drain pattern ( Fig. 18 source/drain region 220 ) on the active pattern ( Fig. 18 F1 or F2 ); and an active contact ( Fig. 18 first source/drain contact 250 ) electrically connected ( both components Fig. 18 #250 and #220 are part of the source/drain so they are electrically connected ) to the source/drain pattern ( Fig. 18 first source/drain region 220 ), wherein a sidewall of the source/drain pattern ( Fig. 18 #220 ) includes a first surface ( Fig. 18: #220 top portion of layer is first surface ) and a second surface ( Fig. 18: #220 bottom portion of layer is second surface ), wherein the first surface intersects the second surface to form a vertex of the source/drain pattern ( Fig. 18: #220 largest bend in the middle of the region ), wherein the active contact ( Fig. 18 #250 ) includes a first extension that covers the first surface ( Fig. 18 #250_1 top portion above vertex) and a second extension that covers the second surface ( Fig. 18 #250_1 bottom portion below vertex ), wherein the first extension has a first slope and extends along the first surface ( Fig. 18 #250_1 top portion slopes out from the center of upper region), wherein the second extension has a second slope and extends along the second surface ( Fig. 18 #250_1 bottom portion slopes from the vertex to the bottom of the F1 region ), and wherein one slope of the first slope and the second slope is a positive slope ( as shown in Fig. 18 first slope is positive ), and the other slope of the first slope and the second slope is a negative slope ( as shown in Fig. 18 second slope is negative ).
Regarding claim 11, Kim teaches the semiconductor device of claim 10 ( as discussed above), further comprising: a first silicon layer ( Fig. 18 #222 ) between the active contact ( Fig. 18 #250) and the sidewall of the source/drain pattern ( Fig. 18 #220 ); and a second silicon layer ( Fig. 18 #222 ) separated from the source/drain pattern ( Fig. 18 #220 ) and across the first extension ( Fig. 18 upper portion of #250_1 ) and the second extension ( Fig. 18 bottom portion of #250_1 ).
Regarding claim 12, Kim teaches the semiconductor device of claim 11 ( as discussed above ), wherein a silicide layer ( Fig. 18 #260 ) is between the first silicon layer ( Fig. 18 #222 ) and the active contact ( Fig. 18 #250 ) and between the second silicon layer ( Fig. 18 #263 ) and the active contact ( Fig. 18 #250 ).
Regarding claim 13, Kim teaches the semiconductor device of claim 12 ( as discussed above ), wherein the silicide layer ( Fig. 18 #260 and #263 ) includes at least one of titanium-silicide, tantalum-silicide, tungsten-silicide, nickel-silicide, and cobalt-silicide ( [0112] The first layer 261 and the second layer 263 may include different materials from each other. The first layer 261 may include a material in which a part of the second doping layer 222 is silicidized. The second layer 263 may include a material in which silicon (Si) doped with the first impurity at a third concentration higher than the second concentration is silicidized; the list above consists of silicide material and Kim states the layers are silicide to this encompasses the listed options ).
Regarding claim 15, Kim teaches the semiconductor device of claim 12 ( as discussed above ), wherein the silicide layer ( Fig. 18 #260 and #263 ) has an impurity concentration that increases with decreasing distance ( [0112] The first layer 261 and the second layer 263 may include different materials from each other. The first layer 261 may include a material in which a part of the second doping layer 222 is silicidized. The second layer 263 may include a material in which silicon (Si) doped with the first impurity at a third concentration higher than the second concentration is silicidized ) from the active contact ( Fig. 18 #250 ).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 5 is rejected under U.S.C. 103 as being unpatentable over Kim et al.; US 2023/0011153 A1; 02/2022 in view of Chang et al.; US 2024/0222455 A1; 02/2023
Claim 5: Kim discloses the semiconductor device of claim 1 ( as discussed above ).
Kim does not appear to disclose each silicide layer includes at least one of titanium-silicide, tantalum-silicide, tungsten-silicide, nickel-silicide, and cobalt-silicide.
Chang teaches each silicide layer ( Fig. 9: silicide layer SA1 ) includes at least one of titanium-silicide, tantalum-silicide, tungsten-silicide, nickel-silicide, and cobalt-silicide ([0038] the silicide layer SA1 and the silicide layer SA2 may include metal silicide, such as cobalt-silicide, nickel-silicide, or other suitable metal silicide materials ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Chang with Kim to implement each silicide layer includes at least one of titanium-silicide, tantalum-silicide, tungsten-silicide, nickel-silicide, and cobalt-silicide because this would minimize contact resistance between silicon and metal interconnects, reduce parasitic resistance, and enhance thermal stability.
Claims 6 – 8, 14, 16-17, and 20 are rejected under U.S.C. 103 as being unpatentable over Kim et al.; US 2023/0011153 A1; 02/2022 in view of Wang et al.; US 2020/0035787 A1; 01/2019
Claim 6: Kim discloses the semiconductor device of claim 1 ( as discussed above ).
Kim does not appear to disclose the active contact includes a conductive pattern and a barrier pattern that surrounds the conductive pattern, and wherein the barrier pattern is between the conductive pattern and the first layer and between the conductive pattern and the second layer.
However, Wang teaches the active contact ( Fig. 19A #200 ) includes a conductive pattern ( Fig. 19A #2001/2002 ) and a barrier pattern ( Fig. 19A #241 ) that surrounds the conductive pattern ( as shown in Fig. 19A #241 is between #200 and #222 ), and wherein the barrier pattern ( Fig. 19A #241 ) is between the conductive pattern ( Fig. 19A #2001/2002 ) and the first layer ( Fig. 19A #225 ) and between the conductive pattern ( Fig. 19A #2011/2012 ) and the second layer ( Fig. 19A #225 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Wang with Kim to implement the active contact includes a conductive pattern and a barrier pattern that surrounds the conductive pattern, and wherein the barrier pattern is between the conductive pattern and the first layer and between the conductive pattern and the second layer because this approach may prevent metal diffusion, improve adhesion, and maintain low-resistance Ohmic contacts in highly integrated circuits.
Claim 7: Kim and Wang disclose the semiconductor device of claim 6 ( as discussed above ).
Kim does not appear to disclose the barrier pattern covers a top surface and opposite sidewalls of each silicide layer.
However, Wang teaches the barrier pattern ( Fig. 19A #241 ) covers a top surface and opposite sidewalls ( Fig. 19A: SW1 and SW2 ) of each silicide layer ( Fig. 19A #222 ) .
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Wang with Kim to implement the barrier pattern covers a top surface and opposite sidewalls of each silicide layer because this approach can be used to prevent atomic diffusion.
Claim 8: Kim and Wang disclose the semiconductor device of claim 1 ( as discussed above ).
Kim does not appear to disclose further comprising a stop layer on a sidewall of the second layer, wherein the stop layer includes SiN.
However, Wang teaches further comprising a stop layer ( Fig. 19A #150 and #215 ) on a sidewall of the second layer ( Fig. 19A #225 on right side of the figure ), wherein the stop layer includes SiN ( [0054] The CESL 150 is made of a silicon nitride based material, such as SiN and SiON, and has a thickness in a range from about 2 nm to about 20 nm in some embodiments ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Wang with Kim to implement a stop layer on a sidewall of the second layer, wherein the stop layer includes SiN because this acts as an etch stop to precisely control material removal depth.
Claim 14: Kim discloses the semiconductor device of claim 12 ( as discussed above ).
Kim does not appear to disclose the active contact includes a conductive pattern and a barrier pattern that surrounds the conductive pattern, and wherein the barrier pattern is between the silicide layer and the conductive pattern.
However, Wang teaches the active contact ( Fig. 19A #200 ) includes a conductive pattern ( Fig. 19A #2001/2002 ) and a barrier pattern ( Fig. 19A #241 ) that surrounds the conductive pattern ( as shown in Fig. 19A #241 is between #200 and #222 ), and wherein the barrier pattern ( Fig. 19A #241 ) is between the conductive pattern ( Fig. 19A #2001/2002 ) and the first layer ( Fig. 19A #225 ) and between the silicide layer ( Fig 19A #222 ) and the conductive pattern ( Fig. 19A #2001/2002 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Wang with Kim to implement the active contact includes a conductive pattern and a barrier pattern that surrounds the conductive pattern, and wherein the barrier pattern is between the silicide layer and the conductive pattern because this approach would be used to prevent metal atoms from migrating into the silicon.
Claim 16: Kim discloses a method of fabricating a semiconductor device ( Fig. 18 ), the method comprising: forming an active pattern (Fig. 18 #250 ) on a substrate ( Fig. 18 substrate 100 ); forming a source/drain pattern ( Fig. 18: source/drain region 220 ) on the active pattern ( Fig. 18 #250 ); forming a first silicon layer ( Fig. 11: second doping layer 122 ), a sacrificial layer ( [0101] the exposed sacrificial layer ( 20 of Fig. 11 )) on the first silicon layer ( Fig. 11 #122 ), and a second silicon layer ( Fig. 11: first capping layer 123 ) on the sacrificial layer ( Fig. 11 #20 ), the first silicon layer ( Fig. 11 #122; same as Fig. 18 #222 ) extending from a top surface of the source/drain pattern ( Fig. 18 #220 ) to a sidewall of the source/drain pattern ( as shown in Fig. 18 );
Kim does not appear to disclose forming a stop layer on the second silicon layer; forming a first interlayer dielectric layer on the active pattern and a second interlayer dielectric layer on the first interlayer dielectric layer; etching the first and second interlayer dielectric layers to form a recess hole; partially removing the stop layer and the second silicon layer that are exposed by the recess hole; removing the sacrificial layer exposed by the recess hole; doping impurities into the first and second silicon layers exposed by the recess hole; forming a silicide layer by depositing a metallic material on the first and second silicon layers that are exposed by the recess hole; and forming an active contact in the recess hole.
However, Wang teaches forming a stop layer ( Fig. 18A: a contact-etch stop layer (CESL) 150 ) on the second silicon layer ( Fig. 19A #201 ); forming a first interlayer dielectric layer ( Fig. 14 first ILD layer 67 ) on the active pattern ( Fig. 14 source/drain epitaxial layers 60 and 62 ) and a second interlayer dielectric layer ( Fig. 18A and 18B second ILD layer 160 ) on the first interlayer dielectric layer ( Fig. 14 #67 ); etching the first and second interlayer dielectric layers ( as shown in Fig. 18A ) to form a recess hole ( Fig. 18A openings O1 and O2 ); partially removing the stop layer ( Fig. 18A #150 ) and the second silicon layer ( Fig. 18A #216 ) that are exposed by the recess hole ( Fig. 18A: O1 and O2 ); removing the sacrificial layer ( Fig. 18A #160 ) exposed by the recess hole ( Fig. 18A: O1 and O2 ); doping impurities into the first ( Fig. 19A #200 ) and second silicon layers ( Fig. 19A #201 ) exposed by the recess hole ( Fig. 19A O1 and O2 ) ; forming a silicide layer by depositing a metallic material ( Fig. 15: metal alloy layers 80 and 81; [0049] the metal alloy layer 80 and 81are silicide-germanide layers ) on the first ( Fig. 18A # ) and second silicon layers ( Fig. 19A #201 ) that are exposed by the recess hole ( Fig. 19A: O1 and O2 ); and forming an active contact ( Fig. 19A #2001 and #2011 ) in the recess hole ( Fig. 19A: O1 and O2 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Wang with Kim to implement forming a stop layer on the second silicon layer; forming a first interlayer dielectric layer on the active pattern and a second interlayer dielectric layer on the first interlayer dielectric layer; etching the first and second interlayer dielectric layers to form a recess hole; partially removing the stop layer and the second silicon layer that are exposed by the recess hole; removing the sacrificial layer exposed by the recess hole; doping impurities into the first and second silicon layers exposed by the recess hole; forming a silicide layer by depositing a metallic material on the first and second silicon layers that are exposed by the recess hole; and forming an active contact in the recess hole because it creates a lower-resistance, highly aligned active contact while mitigating overlay errors and leakage issues.
Claim 17: Kim and Wang disclose the method of claim 16 ( as discussed above ).
Kim teaches the active contact ( Fig. 18 first source/drain contact 250 ) includes a first part ( Fig. 18 250_1 covering portions of element 220 except the top portion of element 220 ) that extends from the top surface of the source/drain pattern ( Fig. 18 #220 ) to the sidewall of the source/drain pattern ( Fig. 18 side of #220 ) and covers the sidewall of the source/drain pattern ( as shown in Fig. 18 250_1 touches 220 ), and wherein the first part ( Fig. 18 #250_1 ) is between the first silicon layer ( Fig. 18 #222 in the F1 region ) and the second silicon layer ( Fig. 18 #222 in the F2 region ).
Claim 20: Kim and Wang disclose the semiconductor device of claim 20 ( as discussed above ).
Kim teaches the silicide layer ( Fig. 18 #260 and #263 ) has an impurity concentration that increases with decreasing distance ( [0112] The first layer 261 and the second layer 263 may include different materials from each other. The first layer 261 may include a material in which a part of the second doping layer 222 is silicidized. The second layer 263 may include a material in which silicon (Si) doped with the first impurity at a third concentration higher than the second concentration is silicidized ) from the active contact ( Fig. 18 #250 ).
Claim 18 is rejected under U.S.C. 103 as being unpatentable over Kim et al.; US 2023/0011153 A1; 02/2022 in view of Wang et al.; US 2020/0035787 A1; 01/2019 as it relates to claim 16 and further in view of Xie et al.; US 2024/0321959 A1; 03/2023
Claim 18: Kim and Wang disclose the method of claim 16 ( as discussed above ).
Kim does not appear to disclose the sacrificial layer includes silicon-germanium (SiGe).
However, Xie teaches the sacrificial layer ( Fig. 2: sacrificial layer 110 ) includes silicon-germanium (SiGe) ( [0048] each sacrificial layer 110 may be a silicon-germanium semiconductor alloy ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Xie with Kim and Wang to implement the sacrificial layer includes silicon-germanium (SiGe) because the material allows for precise removal without damaging the final device structure.
Claim 19 is rejected under U.S.C. 103 as being unpatentable over Kim et al.; US 2023/0011153 A1; 02/2022 in view of Wang et al.; US 2020/0035787 A1; 01/2019 as it relates to claim 16 and further in view of Chang et al.; US 2024/0222455 A1; 02/2023
Claim 19: Kim and Wang disclose the method of claim 16 ( as discussed above ),
Neither Kim nor Wang appear to disclose the silicide layer includes at least one of titanium-silicide, tantalum-silicide, tungsten-silicide, nickel-silicide, and cobalt-silicide.
However, Chang teaches the silicide layer ( Fig. 9: silicide layer SA1 ) includes at least one of titanium-silicide, tantalum-silicide, tungsten-silicide, nickel-silicide, and cobalt-silicide ([0038] the silicide layer SA1 and the silicide layer SA2 may include metal silicide, such as cobalt-silicide, nickel-silicide, or other suitable metal silicide materials ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Chang with Kim and Wang to implement the silicide layer includes at least one of titanium-silicide, tantalum-silicide, tungsten-silicide, nickel-silicide, and cobalt-silicide because these specific materials reduce contact resistance, improve thermal stability, and enable self-aligned silicide processes.
Conclusion
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/K.N.F./Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
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