Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 9-17, and 22-23 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Lee (US 20230290767 A1).
Regarding claim 1, Lee discloses a chip, comprising: a first cell (left cell in the upper portion of Fig. 6C) comprising: a first diffusion region (ACT) extending in a first direction (X); and first gates (GL) formed over the first diffusion region (Shown), wherein each of the first gates is elongated and extends in a second direction (Y) perpendicular to the first direction; a second cell (right cell in the upper portion of Fig. 6C) comprising: a second diffusion region (ACT) extending in the first direction; and second gates (GL) formed over the second diffusion region, wherein each of the second gates is elongated and extends in the second direction (Shown); a first contact (CA_C in bottom portion of Fig. 6C) extending in the second direction over the first diffusion region and the second diffusion region (Shown), wherein the first cell comprises a first portion (upper portion of CA_C) of the first contact and the second cell comprises a second portion (lower portion of CA_C) of the first contact; a first via disposed on the first contact (Upper V0 disposed on first contact) between the first diffusion region and the second diffusion region (V0 is shown between left and right ACT regions), and a rail (M1(VDD)) extending in the first direction over the first via, wherein the first via couples the first contact to the rail (Shown).
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Regarding claim 2, Lee discloses a second via disposed on the second portion of the first contact (Lower V0 disposed on first contact); a first metal path extending in the first direction over the second via (M1(VSS); para. 80 "A power interconnection layer 180P may correspond to power interconnection line patterns M1(VDD) and M1(VSS)"; para. 94 "The interconnection layers 180 may include a power interconnection layer 180P…. Each of the interconnection layers 180 may include a barrier layer 182 and a conductive layer 184. The barrier layer 182 includes, for example, at least one of titanium.... The conductive layer 184 may include, for example, at least one of... copper"), wherein the second via couples the first contact to the first metal path (Shown); and second metal path extending in the second direction over the first metal path and the rail (See attached figure), wherein the second metal path is coupled to the first metal path and the rail (Fig. 7A shows gate 130 being coupled to interconnects 180; para. 80 "the gate structure 130 may correspond to the gate pattern GL").
Regarding claim 9, Lee discloses wherein the second cell further comprises: a second contact (See attached figure) extending in the second direction over the second diffusion region (Shown); and a third contact (See attached figure) disposed extending in the second direction over the second diffusion
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region (Shown).
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Regarding claim 10, Lee discloses further comprising: a third via coupling the second contact to the first metal path; and a fourth via coupling the third contact to the first metal path (See attached figure).
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Regarding claim 11, Lee discloses wherein a first one of the second gates is between the first contact and the second contact, and a second one of the second gates is between the second contact and the third contact (See attached figure).
Regarding claim 12, Lee discloses wherein the second diffusion region is a n-type diffusion region (Fig. 7A, comprises 110, 105, and 120; para. 85 "the source/drain regions 120 may include N-type doped silicon (Si) and/or P-type doped silicon germanium") and the gates are coupled to a supply voltage (Fig. 6C shows second gates coupled to M1(VDD); Para. 79 "The interconnection layers 180 may include a power interconnection layer 180P applying a power supply voltage/a ground voltage"; para. 80 "A power interconnection layer 180P may correspond to power interconnection line patterns M1(VDD) and M1(VSS)"; therefore M1(VSS) corresponds to 180P, which may apply a supply voltage).
Regarding claim 13, Lee discloses wherein the rail comprises a ground rail (Para. 79 "The interconnection layers 180 may include a power interconnection layer 180P applying a power supply voltage/a ground voltage"; para. 80 "A power interconnection layer 180P may correspond to power interconnection line patterns M1(VDD) and M1(VSS)"; therefore M1(VDD) corresponds to 180P, which may apply a ground potential).
Regarding claim 14, Lee discloses wherein the second diffusion region is a p-type diffusion region (Fig. 7A, comprises 110, 105, and 120; para. 85 "the source/drain regions 120 may include N-type doped silicon (Si) and/or P-type doped silicon germanium") and the second gates are coupled to a ground potential (Fig. 6C shows second gates coupled to M1(VDD); Para. 79 "The interconnection layers 180 may include a power interconnection layer 180P applying a power supply voltage/a ground voltage"; para. 80 "A power interconnection layer 180P may correspond to power interconnection line patterns M1(VDD) and M1(VSS)"; therefore M1(VSS) corresponds to 180P, which may apply a ground potential).
Regarding claim 15, Lee discloses wherein the rail comprises a voltage supply rail (Para. 79 "The interconnection layers 180 may include a power interconnection layer 180P applying a power supply voltage/a ground voltage"; para. 80 "A power interconnection layer 180P may correspond to power interconnection line patterns M1(VDD) and M1(VSS)"; therefore M1(VDD) corresponds to 180P, which may apply a supply voltage).
Regarding claim 16, Lee discloses wherein the first cell further comprises: a second contact (See attached figure) extending in the second direction over the first diffusion region (Shown); and a third contact (See attached figure) disposed extending in the second direction over the first diffusion region
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(Shown).
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Regarding claim 17, Lee discloses wherein: the first gates are coupled to an input (Fig. 6C shows first gates coupled to gate contacts CB of the first cell; see attached figure) of the first cell; and the second contact and the third contact are coupled to an output of the first cell (Fig. 6C shows second and third contacts coupled to contact patterns CA; Figs. 7A-B indicate that CA corresponds to contact structure 150, which is shown connecting to source/drain regions 120 which function as outputs).
Regarding claim 22, Lee discloses wherein the first diffusion region is a n-type diffusion region (Fig. 7A, comprises 110, 105, and 120; para. 85 "the source/drain regions 120 may include N-type doped silicon (Si) and/or P-type doped silicon germanium") and the rail is a ground rail (Para. 79 "The interconnection layers 180 may include a power interconnection layer 180P applying… a ground voltage").
Regarding claim 23, Lee discloses wherein the first diffusion region is a p-type diffusion region (Fig. 7A, comprises 110, 105, and 120; para. 85 "the source/drain regions 120 may include N-type doped silicon (Si) and/or P-type doped silicon germanium") and the rail is a voltage supply rail (Para. 79 "The interconnection layers 180 may include a power interconnection layer 180P applying a power supply voltage").
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 18-21 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20230290767 A1) as applied to claims 1-2, 9-17, and 22-23 above, and further in view of Kondo (US 20040120197 A1).
Regarding claim 18, Lee discloses the chip of claim 17. However, Lee does not explicitly disclose further comprising a data path coupled to the output of the first cell.
On the other hand, Kondo discloses further comprising a data path coupled to the output of a cell (Para. 143 "Data transfers for read and write are performed between this memory cell unit 13 and the bit lines BL and /BL via the access transistors Q5 and Q6"). It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Lee according to the teachings of Kondo such that a data path would be coupled to the output of the first cell, in order to allow for the basic operations of the memory device.
Regarding claim 19, Kondo discloses further comprising a memory array (Fig. 10, 131), wherein the data path is coupled between the output of the first cell and the memory array (Fig. 10 shows inputs/outputs of cell 140 being connected to bit lines and word lines comprised by the memory array).
Regarding claim 20, Lee discloses the chip of claim 17. However, Lee does not disclose further comprising a data path coupled to the input of the first cell.
On the other hand, Kondo discloses further comprising a data path coupled to the input of a cell (Para. 143 "Data transfers for read and write are performed between this memory cell unit 13 and the bit lines BL and /BL via the access transistors Q5 and Q6"). It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Lee according to the teachings of Kondo such that a data path would be coupled to the input of the first cell, in order to allow for the basic operations of the memory device.
Regarding claim 21, Kondo discloses further comprising a memory array (Fig. 10, 131), wherein the data path is coupled between the input of the first cell and the memory array (Fig. 10 shows inputs/outputs of cell 140 being connected to bit lines and word lines comprised by the memory array).
Allowable Subject Matter
Claims 3-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 3, the prior art of record fails to disclose the first metal path and the rail are formed from a first metal layer; and the second metal path is formed from a second metal layer above the first metal layer.
Regarding claim 4, the prior art of record fails to disclose a third via disposed on the first portion of the first contact; and a third metal path extending in the first direction over the third via, wherein the third via couples the first contact to the third metal path.
For this reason claims 5-8 are also objected to as dependents of claim 4.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMUEL J SMITH whose telephone number is (703)756-5706. The examiner can normally be reached M-F 8-5 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at (571) 272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/S.J.S./Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
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