Prosecution Insights
Last updated: July 17, 2026
Application No. 18/492,625

3D ARRAY STRUCTURES AND PROCESSES

Non-Final OA §102
Filed
Oct 23, 2023
Priority
Oct 22, 2022 — provisional 63/418,534 +9 more
Examiner
DAS, PINAKI
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Neo Semiconductor Inc.
OA Round
1 (Non-Final)
91%
Grant Probability
Favorable
1-2
OA Rounds
9m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 91% — above average
91%
Career Allowance Rate
40 granted / 44 resolved
+22.9% vs TC avg
Moderate +5% lift
Without
With
+5.2%
Interview Lift
resolved cases with interview
Typical timeline
3y 6m
Avg Prosecution
34 currently pending
Career history
84
Total Applications
across all art units

Statute-Specific Performance

§103
79.0%
+39.0% vs TC avg
§102
15.8%
-24.2% vs TC avg
§112
4.3%
-35.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 44 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Group I, Species I, Modification I and claim 1 in the reply filed on 4/6/2026 is acknowledged. Claim 2 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group II, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 4/6/2026. Information Disclosure Statement Acknowledgement is made of Applicant's Information Disclosure Statement (IDS) from PTO-1449. The IDS has been considered. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hsu et al. (US 2020/0152502 A1). Re Claim 1, Hsu teaches a word line staircase structure (Fig. 7F), comprising: a plurality of word line layers (word lines “WL”, Fig. 7F, para [0098]) alternately deposited with a plurality of insulating layers (insulating layers 701, Figs. 7E-7F, para [0098]) to form a stack; a first word line stairstep (marked “1st WL step” in annotated Fig. 7F below) that includes all the layers of the stack (see Fig. 7F); one or more additional word line stairsteps (marked “2nd and 3rd WL steps” in annotated Fig. 7F below), wherein each successive additional word line stairstep is formed to include less layers of the stack than a preceding word line stairstep to form the word line staircase structure (see Fig. 7F); and multiple contact holes (contact holes 710, Figs. 7E-7F, paras [0102] – [0103]) formed in each word line stairstep to contact multiple word line layers within that word line stairstep (see Figs. 7E-7F, paras [0102] – [0103]). PNG media_image1.png 371 625 media_image1.png Greyscale Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to PINAKI DAS whose telephone number is (703)756-5641. The examiner can normally be reached M-F 8-5 EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JULIO MALDONADO can be reached at (571)272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /P.D./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
Read full office action

Prosecution Timeline

Oct 23, 2023
Application Filed
Apr 28, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12677451
BOTTOM DIELECTRIC ISOLATION FOR VERTICALLY STACKED DEVICES
4y 3m to grant Granted Jul 07, 2026
Patent 12677441
SEMICONDUCTOR DEVICE
4y 0m to grant Granted Jul 07, 2026
Patent 12666975
SEMICONDUCTOR DEVICE
3y 10m to grant Granted Jun 23, 2026
Patent 12660459
DISPLAY PANEL AND DISPLAY DEVICE
3y 11m to grant Granted Jun 16, 2026
Patent 12635200
High-Breakdown Voltage, Low RDSON Electrical Component with Dissimilar Semiconductor Layers
3y 8m to grant Granted May 19, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
91%
Grant Probability
96%
With Interview (+5.2%)
3y 6m (~9m remaining)
Median Time to Grant
Low
PTA Risk
Based on 44 resolved cases by this examiner. Grant probability derived from career allowance rate.

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