Prosecution Insights
Last updated: July 17, 2026
Application No. 18/492,802

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Non-Final OA §112
Filed
Oct 24, 2023
Priority
Nov 08, 2022 — JP 2022-179140
Examiner
LASASSO, VICTOR JOSEPH
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Fuji Electric Co., Ltd.
OA Round
1 (Non-Final)
87%
Grant Probability
Favorable
1-2
OA Rounds
11m
Est. Remaining
88%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allowance Rate
39 granted / 45 resolved
+18.7% vs TC avg
Minimal +1% lift
Without
With
+1.3%
Interview Lift
resolved cases with interview
Typical timeline
3y 8m
Avg Prosecution
16 currently pending
Career history
55
Total Applications
across all art units

Statute-Specific Performance

§103
77.4%
+37.4% vs TC avg
§102
16.0%
-24.0% vs TC avg
§112
6.6%
-33.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 45 resolved cases

Office Action

§112
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Embodiment 1 as seen in Fig. 1 in the reply filed on March 13, 2026 is acknowledged. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Regarding Claim 1, the phrase, “a semiconductor substrate” in line 3 of Claim 1 is used, but the phrase, “the semiconductor substrate” in line 7 of Claim 1 is used to refer to a different substrate than that seen in line 3. Similarly, the phrase, “the semiconductor substrate” is repeated in line 8 of claim 1 to refer to a different substrate. This is seen as indefinite. The phrase, “an initial characteristic” in line 3 of Claim 1 is used, but the phrase, “the initial characteristic” in line 7, the phrase, “the initial characteristic” is used to refer to a different characteristic than that referenced in line 3, and it is unclear whether the phrase “the initial characteristic” in line 7 refers to “an initial characteristic” as introduced in line 3 or if it would be a characteristic of “a substrate for manufacture” as seen in line 8. The phrase, “the doping region in a substrate for evaluation” is seen in line 6, but the doping region is a characteristic of the semiconductor substrate seen in line 3 of the claim, and it is indefinite what is being described as “a substrate for evaluation” and “a semiconductor substrate” are assumed to refer to different elements. It is unclear if the claim is referring to a semiconductor substrate as seen in line 3 or if it is referring to a separate substrate for evaluation as seen in line 6. The phrase, “the semiconductor substrate” as seen in line 7 of the claim is seen, but this phrase is first used in reference to “a semiconductor substrate” as seen in line 3 of the claim. It is unclear if this claim is referring to the original semiconductor substrate as seen in line 3, or if the substrate being referenced is a substrate for evaluation as referenced in claim 6. The phrase, “the doping region” is seen in line 10 of the claim, and it is unclear whether “the doping region” in line 10 of the claim refers to a semiconductor substrate as seen in line 3, or if “the doping region” in line 10 of the claim would be meant to refer to a characteristic of a substrate for evaluation as seen in line 7 of the claim. The phrase, “the first process condition” is seen in line 12 of the claim, and it is unclear whether this limitation refers to “a set first process condition” as seen in line 6 of the claim or if the phrase refers to “a process condition” as seen in line 2 of the claim. The phrase, “a process of manufacturing the semiconductor device by using the substrate of manufacture” as seen in lines 14-15 of the claim appear to the reference “a semiconductor substrate” as seen in line 3 of the claim as well as “a substrate of manufacture” in lines 7-8 of the claim. It is unclear whether this is a manufacturing step for “a substrate for manufacture” as seen in lines 7-8 or a manufacturing step for “a semiconductor substrate” as seen in line 3. The 112(b) indefiniteness deficiencies render the application unable to be examined in view of prior art. Claims 2-20 are dependent upon Claim 1, and, therefore, inherit these deficiencies. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to VICTOR J LASASSO whose telephone number is (703)756-5668. The examiner can normally be reached M-F 8-5 EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at (571) 272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /V.J.L./Examiner, Art Unit 2898 /JESSICA S MANNO/SPE, Art Unit 2898
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Prosecution Timeline

Oct 24, 2023
Application Filed
Jul 02, 2026
Non-Final Rejection mailed — §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12685049
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
4y 3m to grant Granted Jul 14, 2026
Patent 12684887
PHOTODETECTION DEVICE AND METHOD FOR MANUFACTURING PHOTODETECTION DEVICE
4y 0m to grant Granted Jul 14, 2026
Patent 12672402
LIGHT EMITTING DEVICE
4y 0m to grant Granted Jun 30, 2026
Patent 12666989
SEMICONDUCTOR PACKAGE
4y 2m to grant Granted Jun 23, 2026
Patent 12642148
SEMICONDUCTOR PACKAGE INCLUDING REDISTRIBUTION STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
4y 1m to grant Granted May 26, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
87%
Grant Probability
88%
With Interview (+1.3%)
3y 8m (~11m remaining)
Median Time to Grant
Low
PTA Risk
Based on 45 resolved cases by this examiner. Grant probability derived from career allowance rate.

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