DETAILED ACTION
Examiner’s Note
The prior arts cited in PTO-892 but not used in the current rejection are related to the claimed novelty.
Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular paragraphs, columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. See MPEP 2141.02 VI.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Election/Restrictions
Applicant’s election without traverse of species A/fig. 1-9, reflected in claims 1-20 in the reply filed on 02/23/2026 is acknowledged.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3 and 7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by LEE MYEONG DONG et al. (KR 20220144517 A, hereinafter Lee‘517).
Regarding independent claim 1, Lee‘517 teaches, “A semiconductor device (fig. 1-35, related description) comprising:
a substrate (100, fig. 33) including a plurality of active areas (106) defined by a device isolation layer (104);
a plurality of bit lines (150) extending on the substrate (100) in a first horizontal direction;
a plurality of insulation fences (174) that are spaced apart from each other in the first horizontal direction and are between two adjacent bit lines (150) among the plurality of bit lines on the substrate;
a plurality of buried contacts (194a, 194b) that are between the two adjacent bit lines (150) among the plurality of bit lines and are arranged alternately with the plurality of insulation fences (174) along the first horizontal direction on the substrate, the plurality of buried contacts (194a, 194b) being connected to the plurality of active areas (106), respectively; and
a plurality of insulating layers (184a), each of which is between a respective one of the plurality of insulation fences (174) and a respective one of the plurality of buried contacts (194a, 194b)”.
Regarding claim 2, Lee‘517 further teaches, “The semiconductor device of claim 1, wherein each of the plurality of buried contacts (194a, 194b, fig. 33) comprises a pair of first sidewalls spaced apart from each other in the first horizontal direction and a pair of second sidewalls spaced apart from each other in a second horizontal direction that crosses the first horizontal direction, and each of the plurality of insulating layers (184a) is on a respective one of the pair of first sidewalls of the plurality of buried contacts (194a, 194b)”.
Regarding claim 3, Lee‘517 further teaches, “The semiconductor device of claim 2, wherein the plurality of insulating layers (184a) are not on the pair of second sidewalls of the plurality of buried contacts (194a, 194b)”.
Regarding claim 7, Lee‘517 further teaches, “The semiconductor device of claim 1, further comprising:
a word line (112) in a lower portion of a word line trench (108) extending in a second horizontal direction crossing the first horizontal direction in the substrate;
a word line capping layer (114) in an upper portion of the word line trench (108) and on an upper surface of the word line (112); and
a plurality of spacers (160) on respective sidewalls of the plurality of bit lines (150).
Claims 1-3, 7-9, 11-13, 15-16, 18 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mun et al. (US 20220059543 A1, Mun‘543).
Regarding independent claim 1, Mun‘543 teaches, “A semiconductor device (fig. 1-34; ¶ [0026] - ¶ [0245]) comprising:
a substrate (201, fig. 5, 6A) including a plurality of active areas (203) defined by a device isolation layer (202);
a plurality of bit lines (213) extending on the substrate (201) in a first horizontal direction;
a plurality of insulation fences (216, silicon nitride, fig. 6A-6B, ¶ [0093]) that are spaced apart from each other in the first horizontal direction and are between two adjacent bit lines (213) among the plurality of bit lines on the substrate (201);
a plurality of buried contacts (222, fig. 6A) that are between the two adjacent bit lines (213) among the plurality of bit lines and are arranged alternately with the plurality of insulation fences (216) along the first horizontal direction on the substrate, the plurality of buried contacts (222) being connected to the plurality of active areas (203), respectively; and
a plurality of insulating layers (220), each of which is between a respective one of the plurality of insulation fences (216) and a respective one of the plurality of buried contacts (222)”.
Regarding claim 2, Mun‘543 further teaches, “The semiconductor device of claim 1, wherein each of the plurality of buried contacts (222) comprises a pair of first sidewalls spaced apart from each other in the first horizontal direction and a pair of second sidewalls spaced apart from each other in a second horizontal direction that crosses the first horizontal direction, and each of the plurality of insulating layers (220) is on a respective one of the pair of first sidewalls of the plurality of buried contacts (222)”.
Regarding claim 3, Mun‘543 further teaches, “The semiconductor device of claim 2, wherein the plurality of insulating layers (220) are not on the pair of second sidewalls of the plurality of buried contacts (222)”.
Regarding claim 7, Mun‘543 further teaches, “The semiconductor device of claim 1, further comprising: a word line (207) in a lower portion of a word line trench (205) extending in a second horizontal direction crossing the first horizontal direction in the substrate (201); a word line capping layer (208) in an upper portion of the word line trench (205) and on an upper surface of the word line (207); and a plurality of spacers (219) on respective sidewalls of the plurality of bit lines (213)”.
Regarding claim 8, Mun‘543 further teaches, “The semiconductor device of claim 7, wherein an upper surface of the word line capping layer (208, FIG. 6b) comprises a plurality of recesses (accommodating element 212), and the plurality of insulation fences (216) are respectively on the plurality of recesses, and the semiconductor device further comprises a string insulating layer (217) in at least one recess among the plurality of recesses, and the string insulating layer (217) is vertically overlapped by one of the plurality of spacers (219) and is on a sidewall of one the plurality of insulation fences (216)”.
Regarding claim 9, Mun‘543 further teaches, “The semiconductor device of claim 8, wherein the string insulating layer (217) is between two buried contacts (222) that are adjacent to each other in the first horizontal direction, a first end of the string insulating layer (217) is connected to a first buried contact (222) among the two buried contacts, and a second end of the string insulating layer opposite the first end is connected to a second buried contact among the two buried contacts (222)”.
Regarding independent claim 11, Mun‘543 teaches, “A semiconductor device (fig. 1-34; ¶ [0026] - ¶ [0245]) comprising:
a substrate (201, fig. 5, 6A) including a plurality of active areas (203) defined by a device isolation layer (202);
a plurality of bit lines (213) extending on the substrate (201) in a first horizontal direction;
a plurality of spacers (219, ‘protective spacer’, ‘silicon oxide’, ¶ [0096]) on respective sidewalls of the plurality of bit lines;
a plurality of insulation fences (216, silicon nitride, fig. 6A-6B, ¶ [0093]) that are spaced apart from each other in the first horizontal direction and are between two bit lines (213) among the plurality of bit lines on the substrate (201), each of the plurality of bit lines (213) contacting (indirectly) a respective pair of the plurality of spacers (219);
a plurality of buried contacts (222, fig. 6A) that are between the two bit lines (213) among the plurality of bit lines and are arranged alternately with the plurality of insulation fences (216) along the first horizontal direction on the substrate, the plurality of buried contacts (222) being connected to the plurality of active areas (203), respectively;
a plurality of insulating layers (220) between a respective one of the plurality of insulation fences (216) and a respective one of the plurality of buried contacts (222); and
a string insulating layer (217) on a lower sidewall of at least one insulation fence (216) among the plurality of insulation fences and under one of the plurality of spacers (219)”.
Regarding claim 12, Mun‘543 further teaches, “The semiconductor device of claim 11, wherein each of the plurality of insulation fences (216, fig. 5, 6A-6B) comprises a pair of first sidewalls spaced apart from each other in the first horizontal direction and a pair of second sidewalls spaced apart from each other in a second horizontal direction that crosses the first horizontal direction, and each of the plurality of insulating layers (220) is on a respective one of the pair of first sidewalls of the plurality of insulation fences (216)”.
Regarding claim 13, Mun‘543 further teaches, “The semiconductor device of claim 12, wherein each of the plurality of buried contacts (213) comprises a pair of first sidewalls spaced apart from each other in the first horizontal direction and a pair of second sidewalls spaced apart from each other in the second horizontal direction, and the plurality of insulating layers (220, fig. 6B) are not on the pair of second sidewalls of the plurality of buried contacts (222), and the pair of second sidewalls of each of the plurality of buried contacts (222) are respectively in (indirect) contact with two spacers of the plurality of spacers (219)”.
Regarding claim 15, Mun‘543 further teaches, “The semiconductor device of claim 11, further comprising:
a word line (207) in a lower portion of a word line trench (205) extending in a second horizontal direction crossing the first horizontal direction in the substrate; and
a word line capping layer (208) in an upper portion of the word line trench and on an upper surface of the word line (207),
wherein an upper surface of the word line capping layer (208) comprises a plurality of recesses (accommodating element 212), and
the plurality of insulation fences (216) are respectively on (‘ON’ is a broad limitataion) the plurality of recesses”.
Regarding claim 16, Mun‘543 further teaches, “The semiconductor device of claim 11, wherein the string insulating layer (217) is between two buried contacts (222) adjacent to each other in the first horizontal direction,
a first end of the string insulating layer (217) is connected to a first buried contact among the two buried contacts, and
a second end of the string insulating layer (217) opposite the first end is connected to a second buried contact (222) among the two buried contacts”.
Regarding independent claim 18, Mun‘543 teaches, “A semiconductor device (fig. 1-34; ¶ [0026] - ¶ [0245]) comprising:
a substrate (201, fig. 5, 6A) including a plurality of active areas (203) defined by a device isolation layer (202);
a plurality of bit lines (213) extending on the substrate (201) in a first horizontal direction;
a plurality of spacers (219, ‘protective spacer’, ‘silicon oxide’, ¶ [0096]) on respective sidewalls of the plurality of bit lines;
a word line (207, fig. 6B) in a lower portion of a word line trench extending in a second horizontal direction crossing the first horizontal direction in the substrate (201);
a word line capping layer (208) in an upper portion of the word line trench and on an upper surface of the word line (207);
a plurality of insulation fences (216, silicon nitride, fig. 6A-6B, ¶ [0093]) that are spaced apart from each other in the first horizontal direction and are between two bit lines (213) among the plurality of bit lines on the substrate (201), each of the plurality of bit lines (213) contacting (indirectly) a respective pair of the plurality of spacers (219);
a plurality of buried contacts (222, fig. 6A) that are between the two bit lines (213) among the plurality of bit lines and are arranged alternately with the plurality of insulation fences (216) along the first horizontal direction on the substrate, the plurality of buried contacts (222) being connected to the plurality of active areas (203), respectively;
a plurality of insulating layers (220), each of which is between a respective one of the plurality of insulation fences (216) and a respective one of the plurality of buried contacts (222);
a string insulating layer (217) on a lower sidewall of at least one insulation fence (216) among the plurality of insulation fences and under one of the plurality of spacers (219); and
a plurality of landing pads (224) respectively on the plurality of buried contacts (222)”.
Regarding claim 20, Mun‘543 further teaches, “The semiconductor device of claim 18, wherein each of the plurality of insulation fences (216) comprises a pair of first sidewalls spaced apart from each other in the first horizontal direction and a pair of second sidewalls spaced apart from each other in the second horizontal direction, and each of the plurality of insulating layers (220) is on a respective one of the pair of first sidewalls of the plurality of insulation fences (216), and the string insulating layer (217) is on at least one of the pair of second sidewalls of the plurality of insulation fences (216)”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Lee‘517.
Regarding claim 6, ‘The semiconductor device of claim 1, wherein each of the plurality of insulating layers has a thickness of about 2 angstroms to about 20 angstroms’, Lee‘517 teaches plurality of insulating layers (184a), but may not be explicit on the thickness of the insulating layers. While the cited prior art does not explicitly disclose the particular claimed value, the teachings therein would have led one of ordinary skill in the art at the time of invention to discover the claimed value during routine experimentation and optimization. The Applicant has not presented persuasive evidence that the claimed values are for a particular purpose that is critical to the overall claimed invention (i.e., the invention would not work without the specific claimed values). Also, the applicant has not shown that the claimed values produce a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art. Thus, because it has been held that where “the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation" (see MPEP 2144.05; In re Aller, 220 F.2d 454, 456, 105 USPQ 223, 225 (CCPA 1955)), it would have been obvious to add the claimed values to the rest of the claimed invention.
Claims 10 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Mun‘543.
Regarding claims 10 and 17, ‘wherein the plurality of insulating layers comprise silicon oxide, and the string insulating layer comprises silicon oxide’, Mun‘543 teaches the plurality of insulating layers (220) and the string insulating layer (217) are made of same materials (¶ [0096]). Mun‘543 may not be explicitly mentioning as silicon oxide. However, the selection of a known element based on its suitability for its intended use supported a prima facie obviousness. Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945).
Allowable Subject Matter
Claims 4-5, 14 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding dependent claim 4, the prior arts of record do not anticipate or make obvious, inter alia, the feature of: wherein the plurality of insulation fences each have an upper surface at a higher level than upper surfaces of the plurality of buried contacts, and upper surfaces of the plurality of insulating layers are at the same level as the upper surfaces of the plurality of buried contacts.
Claim 5 is also objected as it depends on objected claim 4.
Regarding dependent claim 14, the prior arts of record do not anticipate or make obvious, inter alia, the feature of: wherein the plurality of insulation fences each have an upper surface at a higher level than upper surfaces of the plurality of buried contacts, and upper surfaces of the plurality of insulating layers are at the same level as the upper surfaces of the plurality of buried contacts.
Regarding dependent claim 19, the prior arts of record do not anticipate or make obvious, inter alia, the feature of: wherein an upper surface of the word line capping layer comprises a plurality of recesses, and the plurality of insulation fences are respectively on the plurality of recesses, and an upper surface of the string insulating layer is at a lower level than a bottom surface of the bit lines.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD M HOQUE whose telephone number is (571)272-6266 and email address is mohammad.hoque@uspto.gov. The examiner can normally be reached 9AM-7PM EST.
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/MOHAMMAD M HOQUE/Primary Examiner, Art Unit 2817
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