Prosecution Insights
Last updated: August 17, 2026
Application No. 18/492,855

SEMICONDUCTOR STRUCTURE WITH AIR SPACER AND METHOD FOR FORMING THE SAME

Final Rejection §112
Filed
Oct 24, 2023
Priority
Jul 07, 2023 — provisional 63/512,588
Examiner
YEUNG LOPEZ, FEIFEI
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
2 (Final)
81%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
78%
With Interview

Examiner Intelligence

Grants 81% — above average
81%
Career Allowance Rate
873 granted / 1075 resolved
+13.2% vs TC avg
Minimal -3% lift
Without
With
+-2.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
29 currently pending
Career history
1118
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
54.8%
+14.8% vs TC avg
§102
24.2%
-15.8% vs TC avg
§112
17.5%
-22.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1075 resolved cases

Office Action

§112
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claims 1-13 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. The original disclosure does not teach “laterally recessing the plurality second semiconductor layers…, resulting in a plurality of recesses in the plurality of inner spacers” (claim 1). The original disclosure, paragraphs [0072][0075] of 2025/0015132 A1, teaches the recesses in the inner spacers are a result of laterally recessing the inner spacers not the second semiconductor layers: [0072] An etching process is performed on the dielectric material 126 to remove portions of the dielectric material 126 outside the notches 124,…Remaining portions of the dielectric material 126 in the notches 124 form inner spacers 127, as shown in FIGS. 2E-1 and 2E-2, in accordance with some embodiments. [0075] Due to the characteristics of the etching process, the exposed surfaces of the inner spacers 127 are recessed thereby forming recesses 128′, in accordance with some embodiments. As a result, the exposed surfaces of the inner spacers 127 have concave profiles, in accordance with some embodiments. In some embodiments, the recesses 128′ are denoted as 128′_1, 128′_2 and 128′_3 from top to bottom, which are formed in the inner spacers 127_1, 127_2 and 127_3, respectively. Similarly, claim 9 recites “the inner spacer having a first recess; laterally recessing the channel layers etching the inner spacer to enlarge the first recess.” The original disclosure teaches the first recess is enlarged by etching the inner spacer not the channel layers, even though both are recessed in the same etching process. [0079] The recessed second semiconductor layers 108 have concave surfaces that are exposed from the recesses 130, in accordance with some embodiments. In the etching process, the inner spacers 127 are also recessed, thereby enlarging the recesses 128′, as shown in FIGS. 2F-1 and 2F-2, in accordance with some embodiments. The enlarged recesses 128′ are denoted as 128. The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 1 recites “laterally recessing the plurality second semiconductor layers…, resulting in a plurality of recesses in the plurality of inner spacers.” It is unclear how, and impossible, to etch the plurality second semiconductor layers only to have the inner spacers etched instead. Even if both second semiconductor layers and inner spacers are etched at the same time, recesses in the inner spacers have to be a result of the inner spacers being etched. Claim 9 recites “the inner spacer having a first recess; laterally recessing the channel layers etching the inner spacer to enlarge the first recess.” Enlarging the first recesses in the inner spacer has to be by etching the inner spacer, and not by etching the channel layers, even though they are both etched in the same process. Allowable Subject Matter Claims 14-20 are allowed. The following is an examiner’s statement of reasons for allowance: Prior art does not teach “a portion of the source/drain feature laterally protrudes into one of the plurality of nanostructures” (claim 14). Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to FEIFEI YEUNG LOPEZ whose telephone number is (571)270-1882. The examiner can normally be reached M-F: 8am to 4pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571 270 7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /FEIFEI YEUNG LOPEZ/Primary Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

Oct 24, 2023
Application Filed
Dec 19, 2025
Non-Final Rejection mailed — §112
Mar 16, 2026
Response Filed
May 19, 2026
Final Rejection mailed — §112
Jul 23, 2026
Applicant Interview (Telephonic)
Jul 23, 2026
Examiner Interview Summary

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
81%
Grant Probability
78%
With Interview (-2.7%)
2y 4m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 1075 resolved cases by this examiner. Grant probability derived from career allowance rate.

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