Prosecution Insights
Last updated: May 29, 2026
Application No. 18/492,967

CHIP PACKAGE STRUCTURE AND ELECTRONIC DEVICE

Non-Final OA §103
Filed
Oct 24, 2023
Priority
Apr 25, 2021 — CN 202110448700.7 +1 more
Examiner
NADAV, ORI
Art Unit
2811
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Huawei Technologies Co., Ltd.
OA Round
1 (Non-Final)
60%
Grant Probability
Moderate
1-2
OA Rounds
1y 2m
Est. Remaining
81%
With Interview

Examiner Intelligence

Grants 60% of resolved cases
60%
Career Allowance Rate
421 granted / 698 resolved
-7.7% vs TC avg
Strong +21% interview lift
Without
With
+20.9%
Interview Lift
resolved cases with interview
Typical timeline
3y 10m
Avg Prosecution
26 currently pending
Career history
767
Total Applications
across all art units

Statute-Specific Performance

§103
89.1%
+49.1% vs TC avg
§102
4.0%
-36.0% vs TC avg
§112
5.3%
-34.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 698 resolved cases

Office Action

§103
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA DETAILED ACTION Election/Restrictions Applicant’s election without traverse of the embodiment of figure 4 in the reply filed on 03/06/2026 is acknowledged. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1, 4, 11, 13-15 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (2016/0322453).Regarding claims 1 and 15, Bet-Shliemoun teaches in figure 1 and related text a chip package structure, comprising: a PCB 16; a chip 24 welded (with solder bumps 28) to the PCB; a package cover 30 disposed on the PCB, the chip is packaged in the package cover; a thermal interface material layer 32 covering the chip and attached to an inner top surface of the package cover; and a heat sink 20 disposed on the PCB, wherein an assembly space is formed between the heat sink and the PCB, the chip 24 and the package cover 30 are both located in the assembly space, a contact plate (lower part of heat sink 20) is provided on a side, facing the package cover of the heat sink, a lower end face of the contact plate abuts against an outer top surface of the package cover 30 by using an abutting member 33. Bet-Shliemoun does not teach in figure 1 that a projection of the abutting member in a height direction of the chip package structure into a region enclosed by an edge of the outer top surface of the package cover covers the chip. Bet-Shliemoun teach in figure 3 that a projection of the abutting member 233 (at least part thereof) in a height direction of the chip package structure into a region enclosed (at least partially enclosed) by an edge of the outer top surface of the package cover 230 covers the chip. It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form a projection of the abutting member in a height direction of the chip package structure into a region enclosed by an edge of the outer top surface of the package cover covers the chip, as taught by figure 3 of Bet-Shliemoun, in Bet-Shliemoun’s device, in order to improve the structural integrity of the device. Regarding claims 4 and 18, Bet-Shliemoun teaches in figure 1 and related text that the abutting member 33 is disposed on the lower end face of the contact plate (lower part of heat sink 20) and abuts against the outer top surface of the package cover 30; and the abutting member 33 is an elastic thermal interface material member or a metal dome. Regarding claim 11, Bet-Shliemoun does not teach that the elastic thermal interface material member is an elastic phase-change metal sheet or a silicone gasket. It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the elastic thermal interface material member as an elastic phase-change metal sheet or a silicone gasket in Bet-Shliemoun’s device, in order to simplify the proessing steps of making the device by using conventional materials. Regarding claim 13, Bet-Shliemoun does not teach that the thermal interface material layer is a silicone layer or a graphene thermal pad. It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the thermal interface material layer is a silicone layer or a graphene thermal pad, in Bet-Shliemoun’s device, in order to simplify the proessing steps of making the device by using conventional materials. Regarding claim 14, Bet-Shliemoun teaches in figure 1 and related text that the heat sink further comprises a fastening post, an elastic member, and a plurality of heat sink fins disposed on the contact plate, the fastening post is disposed on the PCB, an upper end of the elastic member is connected to the fastening post, a lower end of the elastic member is connected to the contact plate, and the elastic member applies elastic force to the contact plate. Regarding claim 15, Bet-Shliemoun teaches in figures 1, 3 and related text substantially the entire claimed structure, as applied to claim 1 above, including an electronic device, comprising a mainboard 118 and a chip package structure, wherein the chip package structure is disposed on the mainboard. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ORI NADAV whose telephone number is 571-272-1660. The examiner can normally be reached between the hours of 7 AM to 4 PM (Eastern Standard Time) Monday through Friday. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached on 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). O.N. /ORI NADAV/ 3/23/2026 PRIMARY EXAMINER TECHNOLOGY CENTER 2800
Read full office action

Prosecution Timeline

Oct 24, 2023
Application Filed
Feb 25, 2025
Response after Non-Final Action
Mar 25, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12642092
CHIP PACKAGE WITH DECOUPLED THERMAL MANAGEMENT
4y 2m to grant Granted May 26, 2026
Patent 12635556
SEMICONDUCTOR DEVICE
1y 10m to grant Granted May 19, 2026
Patent 12628426
DISPLAY DEVICES
3y 0m to grant Granted May 12, 2026
Patent 12622134
ORGANIC ELECTROLUMINESCENT DEVICE, AND ELECTRONIC APPARATUS
2y 7m to grant Granted May 05, 2026
Patent 12610689
DISPLAY DEVICE
4y 7m to grant Granted Apr 21, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
60%
Grant Probability
81%
With Interview (+20.9%)
3y 10m (~1y 2m remaining)
Median Time to Grant
Low
PTA Risk
Based on 698 resolved cases by this examiner. Grant probability derived from career allowance rate.

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