DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The disclosure is objected to because of the following informalities:
(Text within parentheses is either a missing or a corrected information to character(s) in bold.)
[0037] Based on placement information of integrated circuit design 200, antenna diode 220 is spaced apart from the antenna diode 116(216) by a distance (d), which may be sufficient to satisfy a compliance check for antenna diode spacing based on the design information associated with RLM entity 206 considered in isolation.
[0037] …Due (to) this connection between chip connection 226 and input net 210, a transient high current can be delivered directly to antenna diode 220.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-18 are rejected under 35 U.S.C. 103 as being unpatentable over Kenan Yu et. al. (US 20200050731 A1) hereinafter Yu, Michael Alexander Bowen et. al. (US 20230051392 A1) hereinafter Bowen, and Po-Chao TSAO (US 20230128880 A1) hereinafter TSAO.
Regarding claim 1
Yu discloses
A method, in a data processing system including processing circuitry, of performing placement for a hierarchical integrated circuit design, the method comprising:
(Yu, p. 1, [0005] “FIG. 2 is process flow diagram illustrating aspects of an example integrated circuit design method in accordance with some embodiments.”)
(Yu, p. 1, [0014] “FIG. 1 is a block diagram illustrating an example of a processing system 100 in accordance with some embodiments disclosed herein. The processing system 100 may be used to implement an EDA system in accordance with various processes discussed herein. The processing system 100 includes a processing unit 110, such as a desktop computer, a workstation, a laptop computer, a dedicated unit customized for a particular application, a smart phone or tablet, etc.”)
(Yu, p. 1, [0013] “Electronic Design Automation (EDA) tools and methods facilitate the design, partition, and placement of microelectronic integrated circuits on a semiconductor substrate.”)
(Yu, p. 2, [0023] “In a hierarchical design, the functions of the integrated circuit design are allocated space on the semiconductor substrate. Each of the individual functions is then partitioned into the various macro circuits which are often predesigned and placed in the standard cell library of the EDA system.”)
in a hierarchical integrated circuit design including at least an upper hierarchy level, an intermediate hierarchy level, and a lower hierarchy level, said lower hierarchy level including a design entity including at an antenna diode,
(Yu, p. 2, [0023] “In a hierarchical design, the functions of the integrated circuit design are allocated space on the semiconductor substrate. Each of the individual functions is then partitioned into the various macro circuits which are often predesigned and placed in the standard cell library of the EDA system.”)
(Yu, p. 3, [0030] “Still further, if the wires connecting the antenna diode are located in higher metal layers than the metal layers connecting the buffer, the antenna protection function of this diode will fail. This problem can be exacerbated because such interface issues are found at the chip level, and not at the hierarchical block level where they are fixed.”)
the processing circuitry performing placement for integrated circuitry bounded by the design entity, wherein performing placement includes:
(Yu, p. 2, [0022] “In some examples, software code is executed by the CPU 120 to analyze a user design to create a physical integrated circuit layout. The software code may be accessed by the CPU 120 via the bus 130 from the memory 122, mass storage device 124, or the like, or remotely through the network interface 140. Further, in some examples, the physical integrated circuit layout is created based on a functional integrated circuit design, which may be received though the I/O interface 128 and/or stored in the memory 122 or 124 in accordance with various methods and processes implemented by the software code.”)
Yu does not teach
the lower level determining whether or not an antenna cell containing the antenna diode has any adjoining cell containing a diffusion region connected to a chip package pin
and based on a determination that the antenna cell has an adjoining cell containing a diffusion region connected to a chip package pin,
the processing circuitry automatically padding the antenna cell with sufficient padding to satisfy a minimum antenna cell spacing rule and assigning the antenna cell location within a floorplan of the integrated circuit design
However Bowen discloses
the lower level determining whether or not an antenna cell containing the antenna diode has any adjoining cell containing a diffusion region connected to a chip package pin
(Bowen, p. 1, [0010] “FIG. 3 is a block diagram of a hierarchical macro having multiple child macros and a parent macro according to one or more embodiments of the invention;”)
(Bowen, p. 3, [0030] “… In embodiments, the shape information files 324A, 324B, and 326 can define one or more connection characteristics that can be accessed by the design verification tool 140 to discover antenna conditions that may result in violating an antenna rule of the rules 150 when the route 306 is connected or modified. For example, metal, via, gate area, and/or diffusion area can be defined with respect to the source pin 310 of child macro 304A in child shape information file 324A such that upon connecting or checking a connection to the route 306, the potential impacts can be determined by the design verification tool 140. Similarly, metal, via, gate area, and/or diffusion area can be defined with respect to the sink pin 320 of child macro 304B in child shape information file 324B for analysis by the design verification tool 140.”)
(Bowen, p. 3, [0031] “Upon detecting a violation of an antenna rule, the design verification tool 140 can adjust one or more aspects of the hierarchical macro 300. This can include adding antenna cells to the net in the parent or adjusting the path of the route 306 to break up a long signal path and reduce the metal area causing the antenna fail.”)
Yu and Bowen do not teach
and based on a determination that the antenna cell has an adjoining cell containing a diffusion region connected to a chip package pin,
the processing circuitry automatically padding the antenna cell with sufficient padding to satisfy a minimum antenna cell spacing rule and assigning the antenna cell location within a floorplan of the integrated circuit design
However TSAO discloses
and based on a determination that the antenna cell has an adjoining cell containing a diffusion region connected to a chip package pin,
(TSAO, p. 4, [0046] “As shown in the first cell 10-1 of FIG. 3A, the first diffusion region 201 is separated from the third diffusion region 203 by the isolation region 102 (such as STI). The first diffusion region 201 has the opposite conductivity type of the third diffusion region 203. In one example, the first diffusion region 201 contains n-type dopants and has n-type conductivity, and the third diffusion region 203 contains p-type dopants and has p-type conductivity. In some embodiments, the first diffusion region 201 and the third diffusion region 203 are spaced apart from each other in the second direction D2 (such as the Y-direction) and extend in the first direction D1 (such as the X-direction).”)
(TSAO, p. 7, [0071] “As shown in FIG. 3B, according to an initial structure of the semiconductor device 100S-I, the diffusions regions of the adjacent cells will be separated from each other after a patterning process is performed. The spacing between the diffusions regions of the adjacent cells corresponds to the position of the dummy layer 511(/the dummy layer 521). Accordingly, if the initial cut pattern of the initial layout is implemented, the first diffusion region 201 of the first cell 10-1 will be insulatively separated from the second diffusion region 202 of the second cell 10-2, and the third diffusion region 203 of the first cell 10-1 will be insulatively separated from the fourth diffusion region 204 of the second cell 10-2 by an isolation layer (not shown) that corresponds to the position of the dummy layer 511(/the dummy layer 521).”)
the processing circuitry automatically padding the antenna cell with sufficient padding to satisfy a minimum antenna cell spacing rule and assigning the antenna cell location within a floorplan of the integrated circuit design
(TSAO, p. 4, [0046] “As shown in the first cell 10-1 of FIG. 3A, the first diffusion region 201 is separated from the third diffusion region 203 by the isolation region 102 (such as STI). The first diffusion region 201 has the opposite conductivity type of the third diffusion region 203. In one example, the first diffusion region 201 contains n-type dopants and has n-type conductivity, and the third diffusion region 203 contains p-type dopants and has p-type conductivity. In some embodiments, the first diffusion region 201 and the third diffusion region 203 are spaced apart from each other in the second direction D2 (such as the Y-direction) and extend in the first direction D1 (such as the X-direction).”)
(TSAO, p. 1, [0011] “FIG. 2 illustrates a flow of an exemplified layout design modification method for a semiconductor device, in accordance with some embodiments of the present disclosure.”)
(TSAO, p. 4, [0040] “In some embodiments, an IC design system (not shown) that includes a processer and a computer-readable storage medium is provided.”)
(TSAO, p. 7, [0071] “As shown in FIG. 3B, according to an initial structure of the semiconductor device 100S-I, the diffusions regions of the adjacent cells will be separated from each other after a patterning process is performed. The spacing between the diffusions regions of the adjacent cells corresponds to the position of the dummy layer 511(/the dummy layer 521). Accordingly, if the initial cut pattern of the initial layout is implemented, the first diffusion region 201 of the first cell 10-1 will be insulatively separated from the second diffusion region 202 of the second cell 10-2, and the third diffusion region 203 of the first cell 10-1 will be insulatively separated from the fourth diffusion region 204 of the second cell 10-2 by an isolation layer (not shown) that corresponds to the position of the dummy layer 511(/the dummy layer 521).”)
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains combine the teachings of Yu, Bowen and of TSAO to yield predictable result of integrated circuit design protecting it from electrostatic discharge while meeting all the design requirements.
Regarding claim 2
Yu, Bowen, and TSAO teaches all features of claim 1 as disclosed above.
Yu and Bowen do not teach
The method of Claim 1, wherein automatically padding the antenna cell includes updating a design of the antenna cell to include the padding.
However TSAO discloses
The method of Claim 1, wherein automatically padding the antenna cell includes updating a design of the antenna cell to include the padding.
(TSAO, p. 4, [0046] “As shown in the first cell 10-1 of FIG. 3A, the first diffusion region 201 is separated from the third diffusion region 203 by the isolation region 102 (such as STI).”)
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains combine the teachings of Yu, Bowen and of TSAO to yield predictable result of integrated circuit design protecting it from electrostatic discharge while meeting all the design requirements.
Regarding claim 3
Yu, Bowen, and TSAO teaches all features of claim 1 as disclosed above.
Yu and Bowen do not teach
The method of Claim 1, wherein automatically padding the antenna cell includes surrounding the antenna cell with the padding.
However TSAO discloses
The method of Claim 1, wherein automatically padding the antenna cell includes surrounding the antenna cell with the padding.
(TSAO, p. 4, [0046] “As shown in the first cell 10-1 of FIG. 3A, the first diffusion region 201 is separated from the third diffusion region 203 by the isolation region 102 (such as STI). … In some embodiments, the first diffusion region 201 and the third diffusion region 203 are spaced apart from each other in the second direction D2 (such as the Y-direction) and extend in the first direction D1 (such as the X-direction).”)
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains combine the teachings of Yu, Bowen and of TSAO to yield predictable result of integrated circuit design protecting it from electrostatic discharge while meeting all the design requirements.
Regarding claim 4
Yu, Bowen, and TSAO teaches all features of claim 1 as disclosed above.
Yu does not teach
The method of Claim 1, wherein: the automatically padding comprises automatically padding the antenna cell based on determining that an area constraint of the design entity is satisfied.
However Bowen discloses
The method of Claim 1, wherein: the automatically padding comprises automatically padding the antenna cell based on determining that an area constraint of the design entity is satisfied.
(Bowen, p. 2, [0021] “… The system 100 also includes a design verification tool 140 that can analyze the files 160 and apply verification rules 150 (also referred to as rules 150) to confirm that the macros of the design 155 comply with the verification rules 150 when one or more routes are connected between the macros. The verification rules 150 can include one or more antenna rules that define antenna conditions which cannot be violated in the final design. Such rules can include but are not limited to: a “metal area antenna rule” that imposes a maximum limit on a ratio of metal line area to connected gates area, a “perimeter antenna rule” that imposes a maximum limit on a ratio of the metal line perimeter connected gates area and a via or contact area rule that imposes a maximum limit to the ratio of the via or contact area to the connected gates area. Other conditions and rules are contemplated.”)
(Bowen, p. 3, [0030] “… In embodiments, the shape information files 324A, 324B, and 326 can define one or more connection characteristics that can be accessed by the design verification tool 140 to discover antenna conditions that may result in violating an antenna rule of the rules 150 when the route 306 is connected or modified. For example, metal, via, gate area, and/or diffusion area can be defined with respect to the source pin 310 of child macro 304A in child shape information file 324A such that upon connecting or checking a connection to the route 306, the potential impacts can be determined by the design verification tool 140. Similarly, metal, via, gate area, and/or diffusion area can be defined with respect to the sink pin 320 of child macro 304B in child shape information file 324B for analysis by the design verification tool 140.”)
(Bowen, p. 5, [0043] “Next, as shown at decision block 810, the method 800 includes determining whether an antenna condition of the route violates the antenna rule. For example, the design verification tool 140 can compare a computed value of an antenna condition for route 306 or route 331 to one or more thresholds as defined in the rules 150.”)
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains combine the teachings of Yu, Bowen and of TSAO to yield predictable result of integrated circuit design protecting it from electrostatic discharge while meeting all the design requirements, which include all the restrictions, constraints and thresholds for various quantities.
Regarding claim 5
Yu, Bowen, and TSAO teaches all features of claim 4 as disclosed above.
Yu and Bowen do not teach
The method of Claim 4, further comprising:
based on determining that the area constraint of the design entity is not satisfied, placing the antenna cell without padding in the floorplan of the integrated circuit design.
However TSAO discloses
based on determining that the area constraint of the design entity is not satisfied, placing the antenna cell without padding in the floorplan of the integrated circuit design.
(TSAO, p. 6, [0061] “In FIG. 3B, an abutment arrangement using single diffusion break (SDB) layout design is exemplified in this embodiment. Single diffusion break (SDB) acts as an efficient area-scaling enabler for current CMOS technology nodes. In the abutment arrangement, the dummy layer 511 of the first cell 10-1 overlaps the dummy layer 521 of the second cell 10-2 in the SDB layout design. In addition, in the abutment arrangement, the dummy layer 511 (or the dummy layer 521) overlaps the first part 2011 of the first diffusion region 201, the second part 2021 of the second diffusion region 202, the third part 2031 of the third diffusion region 203 and the fourth part 2041 of the fourth diffusion region 204. The first part 2011 of the first diffusion region 201 abuts the second part 2021 of the second diffusion region 202. The third part 2031 of the third diffusion region 203 abuts the fourth part 2041 of the fourth diffusion region 204, as shown in FIG. 3B.”)
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains combine the teachings of Yu, Bowen and of TSAO to yield predictable result of integrated circuit design protecting it from electrostatic discharge while meeting all the design requirements, which include all the restrictions, constraints and thresholds for various quantities.
Regarding claim 6
Yu, Bowen, and TSAO teaches all features of claim 4 as disclosed above and Yu further discloses
The method of Claim 1, wherein the diffusion region is an antenna diode.
(Yu, p. 4, [0041] “… FIG. 5 illustrates an example of a first standard layout cell 500 in which the first circuit 410 is an input buffer 510, and the antenna protection circuit 420 comprises a diode 520 connected between the input terminal 412 and the second voltage terminal 418. … Thus, the antenna diode 520 is connected in a reverse bias condition, with its cathode connected to the input terminal 412 and its anode connected to the VSS or ground terminal 418.”)
(Yu, p. 4, [0046] “The PMOS transistor 622 includes source/drain regions 730, 732, and the PMOS transistor 626 includes source/drain regions 734, 736, which are formed by respective P-diffusions arranged in the N-well region 706. The NMOS transistor 620 forming the antenna diode 520 includes source/drain regions 740, 742.”)
Regarding claim 7
Yu discloses
A program product, comprising
a storage device
(Yu, p. 1, [0014] “… The processing unit 110 also includes a central processing unit (CPU) 120, memory 122, a mass storage device 124, a video adapter 126, and an I/O interface 128 connected to a bus 130.”)
and program code stored within the storage device and executable by processing circuitry of a data processing system
(Yu, p. 2, [0022] “In some examples, software code is executed by the CPU 120 to analyze a user design to create a physical integrated circuit layout. The software code may be accessed by the CPU 120 via the bus 130 from the memory 122, mass storage device 124, or the like, or remotely through the network interface 140.”)
to cause the data processing system to perform placement for a hierarchical integrated circuit design including at least an upper hierarchy level, an intermediate hierarchy level, and a lower hierarchy level, said lower hierarchy level including a design entity including at an antenna diode,
(Yu, p. 2, [0022] “In some examples, software code is executed by the CPU 120 to analyze a user design to create a physical integrated circuit layout. The software code may be accessed by the CPU 120 via the bus 130 from the memory 122, mass storage device 124, or the like, or remotely through the network interface 140.”)
(Yu, p. 1, [0004] “FIG. 1 is a block diagram illustrating aspects of an example processing system in accordance with some embodiments.”)
(Yu, p. 1, [0013] “Electronic Design Automation (EDA) tools and methods facilitate the design, partition, and placement of microelectronic integrated circuits on a semiconductor substrate.”)
(Yu, p. 2, [0023] “In a hierarchical design, the functions of the integrated circuit design are allocated space on the semiconductor substrate. Each of the individual functions is then partitioned into the various macro circuits which are often predesigned and placed in the standard cell library of the EDA system.”)
(Yu, p. 3, [0030] “Still further, if the wires connecting the antenna diode are located in higher metal layers than the metal layers connecting the buffer, the antenna protection function of this diode will fail. This problem can be exacerbated because such interface issues are found at the chip level, and not at the hierarchical block level where they are fixed.”)
wherein the program code causes the data processing system to perform placement for integrated circuitry bounded by the design entity by
(Yu, p. 2, [0022] “In some examples, software code is executed by the CPU 120 to analyze a user design to create a physical integrated circuit layout. The software code may be accessed by the CPU 120 via the bus 130 from the memory 122, mass storage device 124, or the like, or remotely through the network interface 140.”)
Yu does not teach
determining whether or not an antenna cell containing the antenna diode has any adjoining cell containing a diffusion region connected to a chip package pin
and based on a determination that the antenna cell has an adjoining cell containing a diffusion region connected to a chip package pin,
automatically padding the antenna cell with sufficient padding to satisfy a minimum antenna cell spacing rule and assigning the antenna cell location within a floorplan of the integrated circuit design.
However Bowen discloses
determining whether or not an antenna cell containing the antenna diode has any adjoining cell containing a diffusion region connected to a chip package pin
(Bowen, p. 1, [0010] “FIG. 3 is a block diagram of a hierarchical macro having multiple child macros and a parent macro according to one or more embodiments of the invention;”)
(Bowen, p. 3, [0030] “… In embodiments, the shape information files 324A, 324B, and 326 can define one or more connection characteristics that can be accessed by the design verification tool 140 to discover antenna conditions that may result in violating an antenna rule of the rules 150 when the route 306 is connected or modified. For example, metal, via, gate area, and/or diffusion area can be defined with respect to the source pin 310 of child macro 304A in child shape information file 324A such that upon connecting or checking a connection to the route 306, the potential impacts can be determined by the design verification tool 140. Similarly, metal, via, gate area, and/or diffusion area can be defined with respect to the sink pin 320 of child macro 304B in child shape information file 324B for analysis by the design verification tool 140.”)
(Bowen, p. 3, [0031] “Upon detecting a violation of an antenna rule, the design verification tool 140 can adjust one or more aspects of the hierarchical macro 300. This can include adding antenna cells to the net in the parent or adjusting the path of the route 306 to break up a long signal path and reduce the metal area causing the antenna fail.”)
Yu and Bowen do not teach
and based on a determination that the antenna cell has an adjoining cell containing a diffusion region connected to a chip package pin,
automatically padding the antenna cell with sufficient padding to satisfy a minimum antenna cell spacing rule and assigning the antenna cell location within a floorplan of the integrated circuit design.
However TSAO discloses
and based on a determination that the antenna cell has an adjoining cell containing a diffusion region connected to a chip package pin,
(TSAO, p. 4, [0046] “As shown in the first cell 10-1 of FIG. 3A, the first diffusion region 201 is separated from the third diffusion region 203 by the isolation region 102 (such as STI). The first diffusion region 201 has the opposite conductivity type of the third diffusion region 203. In one example, the first diffusion region 201 contains n-type dopants and has n-type conductivity, and the third diffusion region 203 contains p-type dopants and has p-type conductivity. In some embodiments, the first diffusion region 201 and the third diffusion region 203 are spaced apart from each other in the second direction D2 (such as the Y-direction) and extend in the first direction D1 (such as the X-direction).”)
(TSAO, p. 7, [0071] “As shown in FIG. 3B, according to an initial structure of the semiconductor device 100S-I, the diffusions regions of the adjacent cells will be separated from each other after a patterning process is performed. The spacing between the diffusions regions of the adjacent cells corresponds to the position of the dummy layer 511(/the dummy layer 521). Accordingly, if the initial cut pattern of the initial layout is implemented, the first diffusion region 201 of the first cell 10-1 will be insulatively separated from the second diffusion region 202 of the second cell 10-2, and the third diffusion region 203 of the first cell 10-1 will be insulatively separated from the fourth diffusion region 204 of the second cell 10-2 by an isolation layer (not shown) that corresponds to the position of the dummy layer 511(/the dummy layer 521).”)
automatically padding the antenna cell with sufficient padding to satisfy a minimum antenna cell spacing rule and assigning the antenna cell location within a floorplan of the integrated circuit design.
(TSAO, p. 4, [0046] “As shown in the first cell 10-1 of FIG. 3A, the first diffusion region 201 is separated from the third diffusion region 203 by the isolation region 102 (such as STI). The first diffusion region 201 has the opposite conductivity type of the third diffusion region 203. In one example, the first diffusion region 201 contains n-type dopants and has n-type conductivity, and the third diffusion region 203 contains p-type dopants and has p-type conductivity. In some embodiments, the first diffusion region 201 and the third diffusion region 203 are spaced apart from each other in the second direction D2 (such as the Y-direction) and extend in the first direction D1 (such as the X-direction).”)
(TSAO, p. 7, [0071] “As shown in FIG. 3B, according to an initial structure of the semiconductor device 100S-I, the diffusions regions of the adjacent cells will be separated from each other after a patterning process is performed. The spacing between the diffusions regions of the adjacent cells corresponds to the position of the dummy layer 511(/the dummy layer 521). Accordingly, if the initial cut pattern of the initial layout is implemented, the first diffusion region 201 of the first cell 10-1 will be insulatively separated from the second diffusion region 202 of the second cell 10-2, and the third diffusion region 203 of the first cell 10-1 will be insulatively separated from the fourth diffusion region 204 of the second cell 10-2 by an isolation layer (not shown) that corresponds to the position of the dummy layer 511(/the dummy layer 521).”)
(TSAO, p. 1, [0011] “FIG. 2 illustrates a flow of an exemplified layout design modification method for a semiconductor device, in accordance with some embodiments of the present disclosure.”)
(TSAO, p. 4, [0040] “In some embodiments, an IC design system (not shown) that includes a processer and a computer-readable storage medium is provided.”)
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains combine the teachings of Yu, Bowen and of TSAO to yield predictable result of integrated circuit design protecting it from electrostatic discharge while meeting all the design requirements.
Regarding claim 8
Yu, Bowen, and TSAO teaches all features of claim 7 as disclosed above.
Yu and Bowen do not teach
The program product of Claim 7, wherein automatically padding the antenna cell includes updating a design of the antenna cell to include the padding.
However TSAO discloses
The program product of Claim 7, wherein automatically padding the antenna cell includes updating a design of the antenna cell to include the padding.
(TSAO, p. 4, [0046] “As shown in the first cell 10-1 of FIG. 3A, the first diffusion region 201 is separated from the third diffusion region 203 by the isolation region 102 (such as STI).”)
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains combine the teachings of Yu, Bowen and of TSAO to yield predictable result of integrated circuit design protecting it from electrostatic discharge while meeting all the design requirements.
Regarding claim 9
Yu, Bowen, and TSAO teaches all features of claim 7 as disclosed above.
Yu and Bowen do not teach
The program product of Claim 7, wherein automatically padding the antenna cell includes surrounding the antenna cell with the padding.
However TSAO discloses
The program product of Claim 7, wherein automatically padding the antenna cell includes surrounding the antenna cell with the padding.
(TSAO, p. 4, [0046] “As shown in the first cell 10-1 of FIG. 3A, the first diffusion region 201 is separated from the third diffusion region 203 by the isolation region 102 (such as STI). … In some embodiments, the first diffusion region 201 and the third diffusion region 203 are spaced apart from each other in the second direction D2 (such as the Y-direction) and extend in the first direction D1 (such as the X-direction).”)
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains combine the teachings of Yu, Bowen and of TSAO to yield predictable result of integrated circuit design protecting it from electrostatic discharge while meeting all the design requirements.
Regarding claim 10
Yu, Bowen, and TSAO teaches all features of claim 7 as disclosed above
Yu does not teach
The program product of Claim 7, wherein:
automatically padding the antenna cell comprises automatically padding the antenna cell based on determining that an area constraint of the design entity is satisfied.
However Bowen discloses
automatically padding the antenna cell comprises automatically padding the antenna cell based on determining that an area constraint of the design entity is satisfied.
(Bowen, p. 2, [0021] “… The system 100 also includes a design verification tool 140 that can analyze the files 160 and apply verification rules 150 (also referred to as rules 150) to confirm that the macros of the design 155 comply with the verification rules 150 when one or more routes are connected between the macros. The verification rules 150 can include one or more antenna rules that define antenna conditions which cannot be violated in the final design. Such rules can include but are not limited to: a “metal area antenna rule” that imposes a maximum limit on a ratio of metal line area to connected gates area, a “perimeter antenna rule” that imposes a maximum limit on a ratio of the metal line perimeter connected gates area and a via, or contact area rule that imposes a maximum limit to the ratio of the via or contact area to the connected gates area. Other conditions and rules are contemplated.”)
(Bowen, p. 3, [0030] “… In embodiments, the shape information files 324A, 324B, and 326 can define one or more connection characteristics that can be accessed by the design verification tool 140 to discover antenna conditions that may result in violating an antenna rule of the rules 150 when the route 306 is connected or modified. For example, metal, via, gate area, and/or diffusion area can be defined with respect to the source pin 310 of child macro 304A in child shape information file 324A such that upon connecting or checking a connection to the route 306, the potential impacts can be determined by the design verification tool 140. Similarly, metal, via, gate area, and/or diffusion area can be defined with respect to the sink pin 320 of child macro 304B in child shape information file 324B for analysis by the design verification tool 140.”)
(Bowen, p. 5, [0043] “Next, as shown at decision block 810, the method 800 includes determining whether an antenna condition of the route violates the antenna rule. For example, the design verification tool 140 can compare a computed value of an antenna condition for route 306 or route 331 to one or more thresholds as defined in the rules 150.”)
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains combine the teachings of Yu, Bowen and of TSAO to yield predictable result of integrated circuit design protecting it from electrostatic discharge while meeting all the design requirements, which include all the restrictions, constraints and thresholds for various quantities.
Regarding claim 11
Yu, Bowen, and TSAO teaches all features of claim 10 as disclosed above.
Yu and Bowen do not teach
The program product of Claim 10, wherein the program code causes the data processing system to perform:
based on determining that the area constraint of the design entity is not satisfied, placing the antenna cell without padding in the floorplan of the integrated circuit design.
However TSAO discloses
based on determining that the area constraint of the design entity is not satisfied, placing the antenna cell without padding in the floorplan of the integrated circuit design.
(TSAO, p. 6, [0061] “In FIG. 3B, an abutment arrangement using single diffusion break (SDB) layout design is exemplified in this embodiment. Single diffusion break (SDB) acts as an efficient area-scaling enabler for current CMOS technology nodes. In the abutment arrangement, the dummy layer 511 of the first cell 10-1 overlaps the dummy layer 521 of the second cell 10-2 in the SDB layout design. In addition, in the abutment arrangement, the dummy layer 511 (or the dummy layer 521) overlaps the first part 2011 of the first diffusion region 201, the second part 2021 of the second diffusion region 202, the third part 2031 of the third diffusion region 203 and the fourth part 2041 of the fourth diffusion region 204. The first part 2011 of the first diffusion region 201 abuts the second part 2021 of the second diffusion region 202. The third part 2031 of the third diffusion region 203 abuts the fourth part 2041 of the fourth diffusion region 204, as shown in FIG. 3B.”)
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains combine the teachings of Yu, Bowen and of TSAO to yield predictable result of integrated circuit design protecting it from electrostatic discharge while meeting all the design requirements, which include all the restrictions, constraints and thresholds for various quantities.
Regarding claim 12
Yu, Bowen, and TSAO teaches all features of claim 4 as disclosed above and Yu further discloses
The program product of Claim 7, wherein the diffusion region is an antenna diode.
(Yu, p. 4, [0041] “… FIG. 5 illustrates an example of a first standard layout cell 500 in which the first circuit 410 is an input buffer 510, and the antenna protection circuit 420 comprises a diode 520 connected between the input terminal 412 and the second voltage terminal 418. … Thus, the antenna diode 520 is connected in a reverse bias condition, with its cathode connected to the input terminal 412 and its anode connected to the VSS or ground terminal 418.”)
(Yu, p. 4, [0046] “The PMOS transistor 622 includes source/drain regions 730, 732, and the PMOS transistor 626 includes source/drain regions 734, 736, which are formed by respective P-diffusions arranged in the N-well region 706. The NMOS transistor 620 forming the antenna diode 520 includes source/drain regions 740, 742.”)
Regarding claim 13
Yu discloses
A data processing system, comprising
(Yu, p. 1, [0015] “… The CPU 120 may comprise any type of electronic data processor, and the memory 122 may comprise any type of system memory, such as static random access memory (SRAM), dynamic random access memory (DRAM), or read-only memory (ROM).”)
(Yu, p. 1, [0004] “FIG. 1 is a block diagram illustrating aspects of an example processing system in accordance with some embodiments.”)
processing circuitry
(Yu, p. 1, [0014] “FIG. 1 is a block diagram illustrating an example of a processing system 100 in accordance with some embodiments disclosed herein.”)
and a storage device communicatively coupled to the processing
(Yu, p. 1, [0014] “… The processing unit 110 also includes a central processing unit (CPU) 120, memory 122, a mass storage device 124, a video adapter 126, and an I/O interface 128 connected to a bus 130.”)
and program code stored within the storage device and executable by the processing circuitry of the data processing system
(Yu, p. 2, [0022] “In some examples, software code is executed by the CPU 120 to analyze a user design to create a physical integrated circuit layout. The software code may be accessed by the CPU 120 via the bus 130 from the memory 122, mass storage device 124, or the like, or remotely through the network interface 140.”)
to cause the data processing system to perform placement for a hierarchical integrated circuit design including at least an upper hierarchy level, an intermediate hierarchy level, and a lower hierarchy level, said lower hierarchy level including a design entity including at an antenna diode
(Yu, p. 2, [0022] “In some examples, software code is executed by the CPU 120 to analyze a user design to create a physical integrated circuit layout. The software code may be accessed by the CPU 120 via the bus 130 from the memory 122, mass storage device 124, or the like, or remotely through the network interface 140.”)
(Yu, p. 1, [0004] “FIG. 1 is a block diagram illustrating aspects of an example processing system in accordance with some embodiments.”)
(Yu, p. 1, [0013] “Electronic Design Automation (EDA) tools and methods facilitate the design, partition, and placement of microelectronic integrated circuits on a semiconductor substrate.”)
(Yu, p. 2, [0023] “In a hierarchical design, the functions of the integrated circuit design are allocated space on the semiconductor substrate. Each of the individual functions is then partitioned into the various macro circuits which are often predesigned and placed in the standard cell library of the EDA system.”)
(Yu, p. 3, [0030] “Still further, if the wires connecting the antenna diode are located in higher metal layers than the metal layers connecting the buffer, the antenna protection function of this diode will fail. This problem can be exacerbated because such interface issues are found at the chip level, and not at the hierarchical block level where they are fixed.”)
wherein the program code causes the data processing system to perform placement for integrated circuitry bounded by the design entity by
(Yu, p. 2, [0022] “In some examples, software code is executed by the CPU 120 to analyze a user design to create a physical integrated circuit layout. The software code may be accessed by the CPU 120 via the bus 130 from the memory 122, mass storage device 124, or the like, or remotely through the network interface 140.”)
Yu does not teach
determining whether or not an antenna cell containing the antenna diode has any adjoining cell containing a diffusion region connected to a chip package pin
and based on a determination that the antenna cell has an adjoining cell containing a diffusion region connected to a chip package pin,
automatically padding the antenna cell with sufficient padding to satisfy a minimum antenna cell spacing rule and assigning the antenna cell location within a floorplan of the integrated circuit design.
However Bowen discloses
determining whether or not an antenna cell containing the antenna diode has any adjoining cell containing a diffusion region connected to a chip package pin
(Bowen, p. 1, [0010] “FIG. 3 is a block diagram of a hierarchical macro having multiple child macros and a parent macro according to one or more embodiments of the invention;”)
(Bowen, p. 3, [0030] “… In embodiments, the shape information files 324A, 324B, and 326 can define one or more connection characteristics that can be accessed by the design verification tool 140 to discover antenna conditions that may result in violating an antenna rule of the rules 150 when the route 306 is connected or modified. For example, metal, via, gate area, and/or diffusion area can be defined with respect to the source pin 310 of child macro 304A in child shape information file 324A such that upon connecting or checking a connection to the route 306, the potential impacts can be determined by the design verification tool 140. Similarly, metal, via, gate area, and/or diffusion area can be defined with respect to the sink pin 320 of child macro 304B in child shape information file 324B for analysis by the design verification tool 140.”)
(Bowen, p. 3, [0031] “Upon detecting a violation of an antenna rule, the design verification tool 140 can adjust one or more aspects of the hierarchical macro 300. This can include adding antenna cells to the net in the parent or adjusting the path of the route 306 to break up a long signal path and reduce the metal area causing the antenna fail.”)
Yu and Bowen do not teach
and based on a determination that the antenna cell has an adjoining cell containing a diffusion region connected to a chip package pin,
automatically padding the antenna cell with sufficient padding to satisfy a minimum antenna cell spacing rule and assigning the antenna cell location within a floorplan of the integrated circuit design.
However TSAO discloses
and based on a determination that the antenna cell has an adjoining cell containing a diffusion region connected to a chip package pin,
(TSAO, p. 4, [0046] “As shown in the first cell 10-1 of FIG. 3A, the first diffusion region 201 is separated from the third diffusion region 203 by the isolation region 102 (such as STI). The first diffusion region 201 has the opposite conductivity type of the third diffusion region 203. In one example, the first diffusion region 201 contains n-type dopants and has n-type conductivity, and the third diffusion region 203 contains p-type dopants and has p-type conductivity. In some embodiments, the first diffusion region 201 and the third diffusion region 203 are spaced apart from each other in the second direction D2 (such as the Y-direction) and extend in the first direction D1 (such as the X-direction).”)
(TSAO, p. 7, [0071] “As shown in FIG. 3B, according to an initial structure of the semiconductor device 100S-I, the diffusions regions of the adjacent cells will be separated from each other after a patterning process is performed. The spacing between the diffusions regions of the adjacent cells corresponds to the position of the dummy layer 511(/the dummy layer 521). Accordingly, if the initial cut pattern of the initial layout is implemented, the first diffusion region 201 of the first cell 10-1 will be insulatively separated from the second diffusion region 202 of the second cell 10-2, and the third diffusion region 203 of the first cell 10-1 will be insulatively separated from the fourth diffusion region 204 of the second cell 10-2 by an isolation layer (not shown) that corresponds to the position of the dummy layer 511(/the dummy layer 521).”)
automatically padding the antenna cell with sufficient padding to satisfy a minimum antenna cell spacing rule and assigning the antenna cell location within a floorplan of the integrated circuit design.
(TSAO, p. 4, [0046] “As shown in the first cell 10-1 of FIG. 3A, the first diffusion region 201 is separated from the third diffusion region 203 by the isolation region 102 (such as STI). The first diffusion region 201 has the opposite conductivity type of the third diffusion region 203. In one example, the first diffusion region 201 contains n-type dopants and has n-type conductivity, and the third diffusion region 203 contains p-type dopants and has p-type conductivity. In some embodiments, the first diffusion region 201 and the third diffusion region 203 are spaced apart from each other in the second direction D2 (such as the Y-direction) and extend in the first direction D1 (such as the X-direction).”)
(TSAO, p. 7, [0071] “As shown in FIG. 3B, according to an initial structure of the semiconductor device 100S-I, the diffusions regions of the adjacent cells will be separated from each other after a patterning process is performed. The spacing between the diffusions regions of the adjacent cells corresponds to the position of the dummy layer 511(/the dummy layer 521). Accordingly, if the initial cut pattern of the initial layout is implemented, the first diffusion region 201 of the first cell 10-1 will be insulatively separated from the second diffusion region 202 of the second cell 10-2, and the third diffusion region 203 of the first cell 10-1 will be insulatively separated from the fourth diffusion region 204 of the second cell 10-2 by an isolation layer (not shown) that corresponds to the position of the dummy layer 511(/the dummy layer 521).”)
(TSAO, p. 1, [0011] “FIG. 2 illustrates a flow of an exemplified layout design modification method for a semiconductor device, in accordance with some embodiments of the present disclosure.”)
(TSAO, p. 4, [0040] “In some embodiments, an IC design system (not shown) that includes a processer and a computer-readable storage medium is provided.”)
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains combine the teachings of Yu, Bowen and of TSAO to yield predictable result of integrated circuit design protecting it from electrostatic discharge while meeting all the design requirements.
Regarding claim 14
Yu, Bowen, and TSAO teaches all features of claim 13 as disclosed above.
Yu and Bowen do not teach
The data processing system of Claim 13, wherein automatically padding the antenna cell includes updating a design of the antenna cell to include the padding.
However TSAO discloses
The data processing system of Claim 13, wherein automatically padding the antenna cell includes updating a design of the antenna cell to include the padding.
(TSAO, p. 4, [0046] “As shown in the first cell 10-1 of FIG. 3A, the first diffusion region 201 is separated from the third diffusion region 203 by the isolation region 102 (such as STI).”)
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains combine the teachings of Yu, Bowen and of TSAO to yield predictable result of integrated circuit design protecting it from electrostatic discharge while meeting all the design requirements.
Regarding claim 15
Yu, Bowen, and TSAO teaches all features of claim 13 as disclosed above.
Yu and Bowen do not teach
The data processing system of Claim 13, wherein automatically padding the antenna cell includes surrounding the antenna cell with the padding.
However TSAO discloses
The data processing system of Claim 13, wherein automatically padding the antenna cell includes surrounding the antenna cell with the padding.
(TSAO, p. 4, [0046] “As shown in the first cell 10-1 of FIG. 3A, the first diffusion region 201 is separated from the third diffusion region 203 by the isolation region 102 (such as STI). … In some embodiments, the first diffusion region 201 and the third diffusion region 203 are spaced apart from each other in the second direction D2 (such as the Y-direction) and extend in the first direction D1 (such as the X-direction).”)
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains combine the teachings of Yu, Bowen and of TSAO to yield predictable result of integrated circuit design protecting it from electrostatic discharge while meeting all the design requirements.
Regarding claim 16
Yu, Bowen, and TSAO teaches all features of claim 13 as disclosed above
Yu does not teach
The data processing system of Claim 13, wherein:
automatically padding the antenna cell comprises automatically padding the antenna cell based on determining that an area constraint of the design entity is satisfied.
However Bowen discloses
automatically padding the antenna cell comprises automatically padding the antenna cell based on determining that an area constraint of the design entity is satisfied.
(Bowen, p. 2, [0021] “… The system 100 also includes a design verification tool 140 that can analyze the files 160 and apply verification rules 150 (also referred to as rules 150) to confirm that the macros of the design 155 comply with the verification rules 150 when one or more routes are connected between the macros. The verification rules 150 can include one or more antenna rules that define antenna conditions which cannot be violated in the final design. Such rules can include but are not limited to: a “metal area antenna rule” that imposes a maximum limit on a ratio of metal line area to connected gates area, a “perimeter antenna rule” that imposes a maximum limit on a ratio of the metal line perimeter connected gates area and a via, or contact area rule that imposes a maximum limit to the ratio of the via or contact area to the connected gates area. Other conditions and rules are contemplated.”)
(Bowen, p. 3, [0030] “… In embodiments, the shape information files 324A, 324B, and 326 can define one or more connection characteristics that can be accessed by the design verification tool 140 to discover antenna conditions that may result in violating an antenna rule of the rules 150 when the route 306 is connected or modified. For example, metal, via, gate area, and/or diffusion area can be defined with respect to the source pin 310 of child macro 304A in child shape information file 324A such that upon connecting or checking a connection to the route 306, the potential impacts can be determined by the design verification tool 140. Similarly, metal, via, gate area, and/or diffusion area can be defined with respect to the sink pin 320 of child macro 304B in child shape information file 324B for analysis by the design verification tool 140.”)
(Bowen, p. 5, [0043] “Next, as shown at decision block 810, the method 800 includes determining whether an antenna condition of the route violates the antenna rule. For example, the design verification tool 140 can compare a computed value of an antenna condition for route 306 or route 331 to one or more thresholds as defined in the rules 150.”)
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains combine the teachings of Yu, Bowen and of TSAO to yield predictable result of integrated circuit design protecting it from electrostatic discharge while meeting all the design requirements, which include all the restrictions, constraints and thresholds for various quantities.
Regarding claim 17
Yu, Bowen, and TSAO teaches all features of claim 16 as disclosed above
Yu and Bowen do not teach
The data processing system of Claim 16, wherein the program code causes the data processing system to perform:
based on determining that the area constraint of the design entity is not satisfied, placing the antenna cell without padding in the floorplan of the integrated circuit design.
However TSAO discloses
based on determining that the area constraint of the design entity is not satisfied, placing the antenna cell without padding in the floorplan of the integrated circuit design.
(TSAO, p. 6, [0061] “In FIG. 3B, an abutment arrangement using single diffusion break (SDB) layout design is exemplified in this embodiment. Single diffusion break (SDB) acts as an efficient area-scaling enabler for current CMOS technology nodes. In the abutment arrangement, the dummy layer 511 of the first cell 10-1 overlaps the dummy layer 521 of the second cell 10-2 in the SDB layout design. In addition, in the abutment arrangement, the dummy layer 511 (or the dummy layer 521) overlaps the first part 2011 of the first diffusion region 201, the second part 2021 of the second diffusion region 202, the third part 2031 of the third diffusion region 203 and the fourth part 2041 of the fourth diffusion region 204. The first part 2011 of the first diffusion region 201 abuts the second part 2021 of the second diffusion region 202. The third part 2031 of the third diffusion region 203 abuts the fourth part 2041 of the fourth diffusion region 204, as shown in FIG. 3B.”)
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains combine the teachings of Yu, Bowen and of TSAO to yield predictable result of integrated circuit design protecting it from electrostatic discharge while meeting all the design requirements, which include all the restrictions, constraints and thresholds for various quantities.
Regarding claim 18
Yu, Bowen, and TSAO teaches all features of claim 4 as disclosed above and Yu further discloses
The data processing system of Claim 13, wherein the diffusion region is an antenna diode.
(Yu, p. 4, [0041] “… FIG. 5 illustrates an example of a first standard layout cell 500 in which the first circuit 410 is an input buffer 510, and the antenna protection circuit 420 comprises a diode 520 connected between the input terminal 412 and the second voltage terminal 418. … Thus, the antenna diode 520 is connected in a reverse bias condition, with its cathode connected to the input terminal 412 and its anode connected to the VSS or ground terminal 418.”)
(Yu, p. 4, [0046] “The PMOS transistor 622 includes source/drain regions 730, 732, and the PMOS transistor 626 includes source/drain regions 734, 736, which are formed by respective P-diffusions arranged in the N-well region 706. The NMOS transistor 620 forming the antenna diode 520 includes source/drain regions 740, 742.”)
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 7-12 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter as explained below.
Regarding the term “storage device” in claim 7; the broadest reasonable interpretation of a claim drawn to a storage, as the claim presented, covers both forms of non-transitory tangible media and transitory propagating signals per se in view of the ordinary and customary meaning of computer readable media, particularly when the specification is silent (see MPEP 2111.01). Because the broadest reasonable interpretation covers a signal per se, a rejection under 35 USC 101 is appropriate as covering non-statutory subject matter. See 1351 OG 212, Feb 23, 2010.
The Examiner suggests that the Applicant replaces “storage” in claim 7 with –computer-readable storage medium--.
Conclusion
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/R.S./Examiner, Art Unit 2851
/JACK CHIANG/Supervisory Patent Examiner, Art Unit 2851
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