Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claims 1-7 are rejected under 35 U.S.C. 103 as being unpatentable over Dabral (US 20230085890 A1) in view of Liff (US 20210098411 A1) and Chiou (US 20220068856 A1).
Regarding claim 1, Dabral discloses a semiconductor package (Fig. 14), comprising:
a redistribution substrate (302);
a first lower semiconductor chip (102A) on the redistribution substrate (vertically on);
an upper semiconductor chip (402A) on the first lower semiconductor chip (vertically on); and
a first insulating element (360 with 460) between (at least 360 is vertically between without requiring any specific overlap. See annotated figure for direction designation) the redistribution substrate and the upper semiconductor chip, wherein the first insulating element encloses the first lower semiconductor chip (horizontally encloses) in a first plane that is parallel to the redistribution substrate (See annotated figure),
wherein the first lower semiconductor chip comprises:
a first pad (112 or 138, enhanced detail provided in Fig. 1B) on a first surface of the first lower semiconductor chip (132);
a first protection layer (139, See annotated figure, enhanced detail provided in Fig. 1B) that encloses the first pad (horizontally encloses) in a second plane that is parallel to the redistribution substrate (See annotated figure);
a first penetration via (170) that penetrates the first lower semiconductor chip (vertically penetrates at least a portion) and is electrically connected to the first pad (The schematic of Fig. 1A shows vias 170 electrically connected to pads 112. This electrical routing is similarly described in [0047]: “bypass routing”);
a second pad (174) on a second surface of the first lower semiconductor chip (176, See annotated figure, enhanced detail provided in Fig. 1B) facing the upper semiconductor chip; and
a first insulating layer (177) including the second pad (horizontally including),
wherein the upper semiconductor chip is directly bonded to the second pad (directly bonded by pad 474) and the first insulating layer (directly bonded by layer 477) of the first lower semiconductor chip in a face-to-face configuration via hybrid bonding ([0087]: “hybrid bonded”),
wherein a particle size of a material comprising the first protection layer is smaller than a particle size of a material comprising the first insulating element;
wherein a bottom surface of the first insulating element (bottom surface of 460) is further away (vertically further away) from the redistribution substrate than a bottom surface of the first protection layer is.
Illustrated below is a marked and annotated figure of Fig. 14 of Dabral.
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Dabral teaches the first protection layer but fails to teach the layer including particles. Thus, Dabral fails to teach “a particle size of a material comprising the first protection layer”.
Liff discloses a first protection layer (Fig. 1D: 107), wherein a particle size of a material comprising the first protection layer is [in a range] ([0045]: “a diameter of between about 0.002 microns to about 12 microns”). Modifying the material of the first protection layer (of Dabral) by including the material/particle of Liff would arrive at the claimed material configuration. A person of ordinary skill in the art before the effective filing date would have a reasonable expectation of success doing so because: Dabral teaches a material of the first protection layer may be varied among dielectrics ([0051]: “a dielectric material such as an oxide (e.g. SiO2) or polymer”); and in each situation the material/particle is performing the function of a protection layer enclosing pads (Liff: Fig. 1D: layer 107 and pads 118; Dabral: layer 139 and pads 112/138). Liff provides a teaching to motivate one of ordinary skill in the art before the effective filing date to include the material/particle of the first protection layer in that it would improve package reliability by adjusting the thermal expansion characteristics of the layer ([0024]: “The CTE of the composite organic dielectric layer…reduce the CTE mismatch…yield and reliability are improved”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed material/particle configuration because it would improve package reliability. MPEP 2143 (I)(G).
Illustrated below is Fig. 1D of Liff.
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Dabral in view of Liff teaches the first insulating element but fails to teach the element including particles. Thus, Dabral fails to teach fails to teach “a particle size of a material comprising the first insulating element”.
Chiou discloses a first insulating element (Fig. 4: 110), with a particle size of a material comprising the first insulating element [in a range] ([0043]: “the molding material can have an average filler particle size in the range of about 5 m to about 50 m”). Modifying the material of the first insulating element (of Dabral) by including the material/particle of Chiou would arrive at the claimed material configuration. A person of ordinary skill in the art before the effective filing date would have a reasonable expectation of success doing so because: Dabral teaches a material of the first insulating element may be varied among moldings ([0076]: “Suitable materials include molding compounds, oxides, and other materials such as silicon pastes, etc.”); and in each situation the material/particle is performing the function of an insulating element enclosing chips (Chiou: Fig. 4: molding 110 and chip 50A; Dabral: molding 360 and chip 102A). Chiou provides a teaching to motivate one of ordinary skill in the art before the effective filing date to include the material/particle of the first insulating element in that it would improve package strength ([0038]: “The fillers are formed of a material that provides mechanical strength and thermal dispersion for the encapsulant”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed material/particle configuration because it would improve package strength. MPEP 2143 (I)(G).
Illustrated below is a marked and annotated figure of Fig. 4 of Chiou.
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Further regarding the claimed particle sizes: Liff and Chiou are separately relied upon to teach particle sizes. The ranges disclosed by Liff ([0045]: “a diameter of between about 0.002 microns to about 12 microns”) and Chiou ([0043]: “about 5 m to about 50 m”) arrive at the claimed size relation “wherein a particle size of a material comprising the first protection layer is smaller than a particle size of a material comprising the first insulating element” because these ranges include values overlapping the claimed size relation. For example, choosing a particle size of 0.1 micron from Liff and 10 microns from Chiou would arrive at the claimed numerical relation “smaller than”. Therefore, the claimed particle size relation lies within ranges disclosed by the prior art and is prima facie obvious. MPEP 2144.05 (I).
Regarding claim 2, Dabral in view of Liff and Chiou discloses the semiconductor package of claim 1 (Dabral: Fig. 14), wherein the upper semiconductor chip comprises:
a third pad (474) on a first surface of the upper semiconductor chip (See annotated figure) facing the first lower semiconductor chip; and
a third insulating layer (477) that encloses the third pad (horizontally encloses) in a third plane that is parallel to the redistribution substrate (See annotated figure),
wherein the second pad and the third pad are in direct contact with each other ([0085]: “a metal-metal bond as with hybrid bonding”), at an interface (a direct interface is illustrate; [0085]: “a dielectric bonding layer 477 (e.g. oxide or polymer) that bonds with the back side passivation layer 177”) where the first lower semiconductor chip and the upper semiconductor chip are in contact with each other (direct contact), and comprise a same material to form a unitary structure (these pads are united and therefore form “a unitary structure”; Dabral: [0085]: “a metal-metal bond as with hybrid bonding”).
Dabral fails to teach specific materials for the second and third pads beyond these pads being metal ([0085]: “this may be a metal-metal bond as with hybrid bonding”). Thus, Dabral in view of Liff and Chiou as previously applied fails to teach “and comprise a same material”. Nevertheless, this is a known material configuration in the prior art for pads in direct contact with each other, as taught by Chiou ([0032]: “the material of the die connectors 56, 76 (e.g., copper) intermingles, so that metal-to-metal bonds are also formed”). A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success including the “same material” configuration (of Chiou) for the second and third pads because in each situation, the pads are directly connected metal pads (Dabral: Fig. 14: pads 174/474; Chiou: Fig. 2: pads 56/76). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed material configuration because it is a known configuration of substantially similar pads. MPEP 2143 (I)(A).
Regarding claim 3, Dabral in view of Liff and Chiou discloses the semiconductor package of claim 1 (Dabral: Fig. 14), wherein the particle size of the material comprising the first insulating element is 50 to 7500 times the particle size of the material comprising the first protection layer (Choosing the same exemplary values used in the claim 1 rejection arrives at a numerical relation squarely within the claimed range. For example: the chosen particle size of the material comprising the first insulating element is 10 microns, which is 100 times the chosen particle size of the material comprising the first protection layer, which is 0.1 microns. 100 is squarely within the claimed range.). MPEP 2144.05 (I).
Regarding claim 4, Dabral in view of Liff and Chiou discloses the semiconductor package of claim 1 (Dabral: Fig. 14), wherein a width of the first lower semiconductor chip is less than a width of the upper semiconductor chip (selecting the specific embodiment disclosed in [0084]: “Alternatively, a die (e.g. 402A) can be bonded to back sides, and span, multiple dies 102A, 102B”. Note: since die 402A spans multiple chips, the underlying chip 102A must have a width “less than” chip 402A).
Regarding claim 5, Dabral in view of Liff and Chiou discloses the semiconductor package of claim 1 (Liff: Fig. 1D), wherein the first protection layer comprises at least one of oxide, nitride, or tetraethyl orthosilicate (TEOS) ([0029]: “silicon dioxide”).
Regarding claim 6, Dabral in view of Liff and Chiou discloses the semiconductor package of claim 1 (Dabral: Fig. 14), wherein the first insulating element comprises an epoxy molding compound (EMC) (Chiou: [0038]: “an epoxy or the like”).
Regarding claim 7, Dabral in view of Liff and Chiou discloses the semiconductor package of claim 1 (Dabral: Fig. 14), wherein the first surface of the first lower semiconductor chip is in direct contact with a first surface of the redistribution substrate (350, See annotated figure, direct contact is shown), and wherein the first pad of the first lower semiconductor chip is in direct contact with a redistribution pad of the redistribution substrate (312 or 338, direct contact is shown).
Claims 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Dabral, Liff, and Chiou as applied to claim 1 above, and further in view of Chen (US 20210375819 A1).
Regarding claim 8, Dabral in view of Liff and Chiou discloses the semiconductor package of claim 1 (Dabral: Fig. 14), but fails to teach variations of the chip shapes and arrangement “further comprising:
a second lower semiconductor chip between the redistribution substrate and the first lower semiconductor chip; and
a second insulating element that encloses the second lower semiconductor chip in a fourth plane that is parallel to the redistribution substrate,
wherein the second lower semiconductor chip comprises:
a fourth pad on a first surface of the second lower semiconductor chip;
a second protection layer that encloses the fourth pad in a fifth plane that is parallel to the redistribution substrate;
a second penetration via that penetrates the second lower semiconductor chip and is electrically connected to the fourth pad;
a fifth pad on a second surface of the second lower semiconductor chip facing the upper semiconductor chip; and
a second insulating layer including the fifth pad,
wherein a particle size of a material comprising the second protection layer is smaller than a particle size of a material comprising the second insulating element.”
Chen discloses a variation of chip shape and arrangement (Fig. 17) further comprising:
a second lower semiconductor chip (70-2) between the redistribution substrate (84) and the first lower semiconductor chip (70-1); and
a second insulating element (56-2) that encloses the second lower semiconductor chip (horizontally encloses) in a fourth plane that is parallel to the redistribution substrate (See annotated figure),
Modifying the chip shapes and arrangements by incorporating the variation disclosed by Chen would arrive at the claimed chip configuration because the second lower semiconductor chip (of Chen) is substantially a replicate of the first lower semiconductor chip (of Chen). For example: applying this duplication of the first semiconductor chip (of Dabral, Liff, and Chiou) would arrive at the claimed second semiconductor chip:
wherein the second lower semiconductor chip comprises:
a fourth pad (Dabral: Fig. 14: 112 or 138, enhanced detail provided in Fig. 1B) on a first surface of the second lower semiconductor chip (132);
a second protection layer (Dabral: Fig. 14: 139, See annotated figure, enhanced detail provided in Fig. 1B) that encloses the fourth pad (horizontally encloses) in a fifth plane that is parallel to the redistribution substrate (Second Plane, See annotated figure);
a second penetration via (Dabral: Fig. 14: 170) that penetrates the second lower semiconductor chip (vertically penetrates at least a portion) and is electrically connected to the fourth pad (The schematic of Fig. 1A shows vias 170 electrically connected to pads 112. This electrical routing is similarly described in [0047]: “bypass routing”);
a fifth pad (Dabral: Fig. 14: 174) on a second surface of the second lower semiconductor chip (176, See annotated figure, enhanced detail provided in Fig. 1B) facing the upper semiconductor chip; and
a second insulating layer (Dabral: Fig. 14: 177) including the fifth pad (horizontally including),
wherein a particle size of a material comprising the second protection layer (Liff: [0045]: “a diameter of between about 0.002 microns to about 12 microns”) is smaller than a particle size of a material comprising the second insulating element (Chiou: [0043]: “the molding material can have an average filler particle size in the range of about 5 m to about 50 m”. Note: the same reasoning and exemplary values applied in the claim 1 rejection are used here.).
A person of ordinary skill in the art would have had a reasonable expectation of success because:
Dabral teaches chip configuration may be varied as a design choice according to alternative package requirements ([0064]: “Alternatively” is in relation to chip configuration).
Dabral illustrates a plurality of chip configurations otherwise including substantially similar structures (at least the embodiments of Figs. 12, 14, and 15).
Chen teaches a plurality of chip configurations (at least the embodiments of Figs. 16 and 17).
A person of ordinary skill in the art before the effective filing date would have been motivated to incorporate the alternative chip configuration (of Chen) because Chen teaches chip configuration is varied as a design choice according to required package configuration ([0045]: “the formation processes of the additional tiers are added”). Therefore, the claimed chip configuration would have been obvious to one of ordinary skill in the art before the effective filing date because it is a duplication of parts according to known chip configurations. MPEP 2144.04 (VI)(B).
Regarding claim 9, Dabral in view of Liff, Chiou, and Chen discloses the semiconductor package of claim 8 (Dabral: Fig. 14), wherein a width of the second lower semiconductor chip is less than a width of the upper semiconductor chip (selecting the specific embodiment disclosed in [0084]: “Alternatively, a die (e.g. 402A) can be bonded to back sides, and span, multiple dies 102A, 102B”. Note: since die 402A spans multiple chips, the underlying chip 102A must have a width “less than” chip 402A).
Regarding claim 10, Dabral in view of Liff, Chiou, and Chen discloses the semiconductor package of claim 8 (Dabral: Fig. 14), wherein the first surface of the second lower semiconductor chip is in contact with a first surface of the redistribution substrate (direct contact), and wherein the fourth pad of the second lower semiconductor chip is in direct contact with a redistribution pad of the redistribution substrate (312 or 338, direct contact is shown).
Allowable Subject Matter
Claims 11-20 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
The primary reason for the allowable subject matter of claims 11-16 is the inclusion of the limitation “wherein the first semiconductor chip is directly bonded to the second pad and the insulating layer of the second semiconductor chip in a face-to-face configuration via hybrid bonding, and wherein a portion of a first surface of the insulating element adjacent to an interface between the protection layer and the insulating element has a concave shape that becomes closer to the first semiconductor chip as a distance from the interface increases” in combination with the other limitations in the claim. For example, prior art of record fails to teach or be reasonably combined to render obvious the claimed limitations “concave shape”, “closer”, and “distance” in combination with all other limitations in claim 11.
The primary reason for the allowable subject matter of claims 17-20 is the inclusion of the limitation “wherein the upper semiconductor chip is directly bonded to the second pad and the lower insulating layer of the lower semiconductor chip in a face-to-face configuration via hybrid bonding, wherein the insulating element comprises an epoxy molding compound (EMC), wherein the second pad and the third pad are in direct contact with each other at an interface where the lower semiconductor chip and the upper semiconductor chip are in contact with each other, and comprise a same material to form a unitary structure, and wherein a portion of a bottom surface of the insulating element adjacent to an interface between the protection layer and the insulating element has a concave shape that becomes further away from the redistribution substrate as a distance from the interface increases” in combination with the other limitations in the claim. For example, prior art of record fails to teach or be reasonably combined to render obvious the claimed limitations “concave shape”, “further away”, and “distance” in combination with all other limitations in claim 17.
Response to Arguments
Applicant's arguments filed 6/2/2026 have been fully considered but they are not persuasive.
Applicant argues:
Applicant argues with respect to claims 1-20 that “Unlike the accidental or uncontrolled uneven surfaces shown in the cited references, the claimed concave structure is a deterministically engineered feature. Crucially, this recess provides critical structural clearance that completely prevents the insulating material (EMC) from protruding and causing physical interference during subsequent integration steps-such as the subsequent fabrication of the redistribution substrate (100) or the vertical stacking of an additional lower chip (400).”. Remarks at pg. 9.
Examiner’s reply:
For claims 11-16 and 17-20: the examiner agrees with Applicant and finds the claims patentably distinct from the prior art because the prior art does not teach or suggest the concave shape claimed, and this shape could not be rendered obvious without an unreasonable amount of hindsight recreation applied as a modification to the generic polishing techniques described in the prior art.
For claims 1-10: In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., “a concave shape”) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM H ANDERSON whose telephone number is (571)272-2534. The examiner can normally be reached Monday-Friday, 8:00-5:00.
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/WILLIAM H ANDERSON/ Examiner, Art Unit 2817
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