Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/24/2023 and 1/29/2024 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Objections
Claim 12 is objected to because of the following informalities: “direct contact each other” in line 2. For the sake of compact prosecution, claim 12 is interpreted in the instant Office action as follows: “direct contact each other” is found to be a typographical error and is believed to be equivalent to “direct contact with each other”; however, no actual change to the claim language has been applied during examination of the instant set of claims. Appropriate correction is required.
Claim 17 is objected to because of the following informalities: “an lower insulating layer” in line 16. For the sake of compact prosecution, claim 17 is interpreted in the instant Office action as follows: “an lower insulating layer” is found to be a typographical error and is believed to be equivalent to “a lower insulating layer”; however, no actual change to the claim language has been applied during examination of the instant set of claims. Appropriate correction is required.
Claim 17 is objected to because of the following informalities: “first surface of the upper semiconductor chip” in line 19. For the sake of compact prosecution, claim 17 is interpreted in the instant Office action as follows: “first surface of the upper semiconductor chip” is found to be a typographical error and is believed to be equivalent to “the first surface of the upper semiconductor chip” based on antecedence in line 14; however, no actual change to the claim language has been applied during examination of the instant set of claims. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claims 1-7 are rejected under 35 U.S.C. 103 as being unpatentable over Dabral (US 20230085890 A1) in view of Liff (US 20210098411 A1) and Chiou (US 20220068856 A1).
Regarding claim 1, Dabral discloses a semiconductor package (Fig. 14), comprising:
a redistribution substrate (302);
a first lower semiconductor chip (102A) on the redistribution substrate (vertically on);
an upper semiconductor chip (402A) on the first lower semiconductor chip (vertically on); and
a first insulating element (360) between (vertically between without requiring any specific overlap. See annotated figure for direction designation) the redistribution substrate and the upper semiconductor chip, wherein the first insulating element encloses the first lower semiconductor chip (horizontally encloses) in a first plane that is parallel to the redistribution substrate (See annotated figure),
wherein the first lower semiconductor chip comprises:
a first pad (112 or 138, enhanced detail provided in Fig. 1B) on a first surface of the first lower semiconductor chip (132);
a first protection layer (139, See annotated figure, enhanced detail provided in Fig. 1B) that encloses the first pad (horizontally encloses) in a second plane that is parallel to the redistribution substrate (See annotated figure);
a first penetration via (170) that penetrates the first lower semiconductor chip (vertically penetrates at least a portion) and is electrically connected to the first pad (The schematic of Fig. 1A shows vias 170 electrically connected to pads 112. This electrical routing is similarly described in [0047]: “bypass routing”);
a second pad (174) on a second surface of the first lower semiconductor chip (176, See annotated figure, enhanced detail provided in Fig. 1B) facing the upper semiconductor chip; and
a first insulating layer (177) including the second pad (horizontally including),
wherein a particle size of a material comprising the first protection layer is smaller than a particle size of a material comprising the first insulating element.
Illustrated below is a marked and annotated figure of Fig. 14 of Dabral.
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Dabral teaches the first protection layer but fails to teach the layer including particles. Thus, Dabral fails to teach “a particle size of a material comprising the first protection layer”.
Liff discloses a first protection layer (Fig. 1D: 107), wherein a particle size of a material comprising the first protection layer is [in a range] ([0045]: “a diameter of between about 0.002 microns to about 12 microns”). Modifying the material of the first protection layer (of Dabral) by including the material/particle of Liff would arrive at the claimed material configuration. A person of ordinary skill in the art before the effective filing date would have a reasonable expectation of success doing so because: Dabral teaches a material of the first protection layer may be varied among dielectrics ([0051]: “a dielectric material such as an oxide (e.g. SiO2) or polymer”); and in each situation the material/particle is performing the function of a protection layer enclosing pads (Liff: Fig. 1D: layer 107 and pads 118; Dabral: layer 139 and pads 112/138). Liff provides a teaching to motivate one of ordinary skill in the art before the effective filing date to include the material/particle of the first protection layer in that it would improve package reliability by adjusting the thermal expansion characteristics of the layer ([0024]: “The CTE of the composite organic dielectric layer…reduce the CTE mismatch…yield and reliability are improved”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed material/particle configuration because it would improve package reliability. MPEP 2143 (I)(G).
Illustrated below is Fig. 1D of Liff.
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Dabral in view of Liff teaches the first insulating element but fails to teach the element including particles. Thus, Dabral fails to teach fails to teach “a particle size of a material comprising the first insulating element”.
Chiou discloses a first insulating element (Fig. 4: 110), with a particle size of a material comprising the first insulating element [in a range] ([0043]: “the molding material can have an average filler particle size in the range of about 5 m to about 50 m”). Modifying the material of the first insulating element (of Dabral) by including the material/particle of Chiou would arrive at the claimed material configuration. A person of ordinary skill in the art before the effective filing date would have a reasonable expectation of success doing so because: Dabral teaches a material of the first insulating element may be varied among moldings ([0076]: “Suitable materials include molding compounds, oxides, and other materials such as silicon pastes, etc.”); and in each situation the material/particle is performing the function of an insulating element enclosing chips (Chiou: Fig. 4: molding 110 and chip 50A; Dabral: molding 360 and chip 102A). Chiou provides a teaching to motivate one of ordinary skill in the art before the effective filing date to include the material/particle of the first insulating element in that it would improve package strength ([0038]: “The fillers are formed of a material that provides mechanical strength and thermal dispersion for the encapsulant”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed material/particle configuration because it would improve package strength. MPEP 2143 (I)(G).
Illustrated below is a marked and annotated figure of Fig. 4 of Chiou.
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Further regarding the claimed particle sizes: Liff and Chiou are separately relied upon to teach particle sizes. The ranges disclosed by Liff ([0045]: “a diameter of between about 0.002 microns to about 12 microns”) and Chiou ([0043]: “about 5 m to about 50 m”) arrive at the claimed size relation “wherein a particle size of a material comprising the first protection layer is smaller than a particle size of a material comprising the first insulating element” because these ranges include values overlapping the claimed size relation. For example, choosing a particle size of 0.1 micron from Liff and 10 microns from Chiou would arrive at the claimed numerical relation “smaller than”. Therefore, the claimed particle size relation lies within ranges disclosed by the prior art and is prima facie obvious. MPEP 2144.05 (I).
Regarding claim 2, Dabral in view of Liff and Chiou discloses the semiconductor package of claim 1 (Dabral: Fig. 14), wherein the upper semiconductor chip comprises:
a third pad (474) on a first surface of the upper semiconductor chip (See annotated figure) facing the first lower semiconductor chip; and
a third insulating layer (477) that encloses the third pad (horizontally encloses) in a third plane that is parallel to the redistribution substrate (See annotated figure),
wherein the second pad and the third pad are in direct contact with each other ([0085]: “a metal-metal bond as with hybrid bonding”), at an interface (a direct interface is illustrate; [0085]: “a dielectric bonding layer 477 (e.g. oxide or polymer) that bonds with the back side passivation layer 177”) where the first lower semiconductor chip and the upper semiconductor chip are in contact with each other (direct contact), and comprise a same material to form a unitary structure (these pads are united and therefore form “a unitary structure”; Dabral: [0085]: “a metal-metal bond as with hybrid bonding”).
Dabral fails to teach specific materials for the second and third pads beyond these pads being metal ([0085]: “this may be a metal-metal bond as with hybrid bonding”). Thus, Dabral in view of Liff and Chiou as previously applied fails to teach “and comprise a same material”. Nevertheless, this is a known material configuration in the prior art for pads in direct contact with each other, as taught by Chiou ([0032]: “the material of the die connectors 56, 76 (e.g., copper) intermingles, so that metal-to-metal bonds are also formed”). A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success including the “same material” configuration (of Chiou) for the second and third pads because in each situation, the pads are directly connected metal pads (Dabral: Fig. 14: pads 174/474; Chiou: Fig. 2: pads 56/76). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed material configuration because it is a known configuration of substantially similar pads. MPEP 2143 (I)(A).
Regarding claim 3, Dabral in view of Liff and Chiou discloses the semiconductor package of claim 1 (Dabral: Fig. 14), wherein the particle size of the material comprising the first insulating element is 50 to 7500 times the particle size of the material comprising the first protection layer (Choosing the same exemplary values used in the claim 1 rejection arrives at a numerical relation squarely within the claimed range. For example: the chosen particle size of the material comprising the first insulating element is 10 microns, which is 100 times the chosen particle size of the material comprising the first protection layer, which is 0.1 microns. 100 is squarely within the claimed range.). MPEP 2144.05 (I).
Regarding claim 4, Dabral in view of Liff and Chiou discloses the semiconductor package of claim 1 (Dabral: Fig. 14), wherein a width of the first lower semiconductor chip is less than a width of the upper semiconductor chip (selecting the specific embodiment disclosed in [0084]: “Alternatively, a die (e.g. 402A) can be bonded to back sides, and span, multiple dies 102A, 102B”. Note: since die 402A spans multiple chips, the underlying chip 102A must have a width “less than” chip 402A).
Regarding claim 5, Dabral in view of Liff and Chiou discloses the semiconductor package of claim 1 (Liff: Fig. 1D), wherein the first protection layer comprises at least one of oxide, nitride, or tetraethyl orthosilicate (TEOS) ([0029]: “silicon dioxide”).
Regarding claim 6, Dabral in view of Liff and Chiou discloses the semiconductor package of claim 1 (Dabral: Fig. 14), wherein the first insulating element comprises an epoxy molding compound (EMC) (Chiou: [0038]: “an epoxy or the like”).
Regarding claim 7, Dabral in view of Liff and Chiou discloses the semiconductor package of claim 1 (Dabral: Fig. 14), wherein the first surface of the first lower semiconductor chip is in direct contact with a first surface of the redistribution substrate (350, See annotated figure, direct contact is shown), and wherein the first pad of the first lower semiconductor chip is in direct contact with a redistribution pad of the redistribution substrate (312 or 338, direct contact is shown).
Claims 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Dabral, Liff, and Chiou as applied to claim 1 above, and further in view of Chen (US 20210375819 A1).
Regarding claim 8, Dabral in view of Liff and Chiou discloses the semiconductor package of claim 1 (Dabral: Fig. 14), but fails to teach variations of the chip shapes and arrangement “further comprising:
a second lower semiconductor chip between the redistribution substrate and the first lower semiconductor chip; and
a second insulating element that encloses the second lower semiconductor chip in a fourth plane that is parallel to the redistribution substrate,
wherein the second lower semiconductor chip comprises:
a fourth pad on a first surface of the second lower semiconductor chip;
a second protection layer that encloses the fourth pad in a fifth plane that is parallel to the redistribution substrate;
a second penetration via that penetrates the second lower semiconductor chip and is electrically connected to the fourth pad;
a fifth pad on a second surface of the second lower semiconductor chip facing the upper semiconductor chip; and
a second insulating layer including the fifth pad,
wherein a particle size of a material comprising the second protection layer is smaller than a particle size of a material comprising the second insulating element.”
Chen discloses a variation of chip shape and arrangement (Fig. 17) further comprising:
a second lower semiconductor chip (70-2) between the redistribution substrate (84) and the first lower semiconductor chip (70-1); and
a second insulating element (56-2) that encloses the second lower semiconductor chip (horizontally encloses) in a fourth plane that is parallel to the redistribution substrate (See annotated figure),
Modifying the chip shapes and arrangements by incorporating the variation disclosed by Chen would arrive at the claimed chip configuration because the second lower semiconductor chip (of Chen) is substantially a replicate of the first lower semiconductor chip (of Chen). For example: applying this duplication of the first semiconductor chip (of Dabral, Liff, and Chiou) would arrive at the claimed second semiconductor chip:
wherein the second lower semiconductor chip comprises:
a fourth pad (Dabral: Fig. 14: 112 or 138, enhanced detail provided in Fig. 1B) on a first surface of the second lower semiconductor chip (132);
a second protection layer (Dabral: Fig. 14: 139, See annotated figure, enhanced detail provided in Fig. 1B) that encloses the fourth pad (horizontally encloses) in a fifth plane that is parallel to the redistribution substrate (Second Plane, See annotated figure);
a second penetration via (Dabral: Fig. 14: 170) that penetrates the second lower semiconductor chip (vertically penetrates at least a portion) and is electrically connected to the fourth pad (The schematic of Fig. 1A shows vias 170 electrically connected to pads 112. This electrical routing is similarly described in [0047]: “bypass routing”);
a fifth pad (Dabral: Fig. 14: 174) on a second surface of the second lower semiconductor chip (176, See annotated figure, enhanced detail provided in Fig. 1B) facing the upper semiconductor chip; and
a second insulating layer (Dabral: Fig. 14: 177) including the fifth pad (horizontally including),
wherein a particle size of a material comprising the second protection layer (Liff: [0045]: “a diameter of between about 0.002 microns to about 12 microns”) is smaller than a particle size of a material comprising the second insulating element (Chiou: [0043]: “the molding material can have an average filler particle size in the range of about 5 m to about 50 m”. Note: the same reasoning and exemplary values applied in the claim 1 rejection are used here.).
A person of ordinary skill in the art would have had a reasonable expectation of success because:
Dabral teaches chip configuration may be varied as a design choice according to alternative package requirements ([0064]: “Alternatively” is in relation to chip configuration).
Dabral illustrates a plurality of chip configurations otherwise including substantially similar structures (at least the embodiments of Figs. 12, 14, and 15).
Chen teaches a plurality of chip configurations (at least the embodiments of Figs. 16 and 17).
A person of ordinary skill in the art before the effective filing date would have been motivated to incorporate the alternative chip configuration (of Chen) because Chen teaches chip configuration is varied as a design choice according to required package configuration ([0045]: “the formation processes of the additional tiers are added”). Therefore, the claimed chip configuration would have been obvious to one of ordinary skill in the art before the effective filing date because it is a duplication of parts according to known chip configurations. MPEP 2144.04 (VI)(B).
Regarding claim 9, Dabral in view of Liff, Chiou, and Chen discloses the semiconductor package of claim 8 (Dabral: Fig. 14), wherein a width of the second lower semiconductor chip is less than a width of the upper semiconductor chip (selecting the specific embodiment disclosed in [0084]: “Alternatively, a die (e.g. 402A) can be bonded to back sides, and span, multiple dies 102A, 102B”. Note: since die 402A spans multiple chips, the underlying chip 102A must have a width “less than” chip 402A).
Regarding claim 10, Dabral in view of Liff, Chiou, and Chen discloses the semiconductor package of claim 8 (Dabral: Fig. 14), wherein the first surface of the second lower semiconductor chip is in contact with a first surface of the redistribution substrate (direct contact), and wherein the fourth pad of the second lower semiconductor chip is in direct contact with a redistribution pad of the redistribution substrate (312 or 338, direct contact is shown).
Claims 11-16 are rejected under 35 U.S.C. 103 as being unpatentable over Dabral in view of Yu (US 20190148250 A1).
Regarding independent claim 11, Dabral discloses a semiconductor package (Fig. 14), comprising:
a first semiconductor chip (402A); a second semiconductor chip (102A) on the first semiconductor chip (vertically on); and
an insulating element (360) in a region which is defined by a first surface of the first semiconductor chip (See annotated figure for surface designation. The upper boundary of 360 is defined by a horizontal plane coplanar with the surface), wherein the insulating element encloses the second semiconductor chip (horizontally encloses) in a first plane that is parallel to a surface of the first semiconductor chip (See annotated figure),
wherein the second semiconductor chip comprises:
a first pad (112 or 138, enhanced detail provided in Fig. 1B) on a first surface of the second semiconductor chip (132);
a protection layer (139, See annotated figure, enhanced detail provided in Fig. 1B) that encloses the first pad (horizontally encloses) in a second plane that is parallel to the surface the first semiconductor chip (See annotated figure);
a penetration via (170) that penetrates the second semiconductor chip (vertically penetrates at least a portion) and is electrically connected to the first pad (The schematic of Fig. 1A shows vias 170 electrically connected to pads 112. This electrical routing is similarly described in [0047]: “bypass routing”);
a second pad (174, of chip 102A) on a second surface of the second semiconductor chip (176, See annotated figure, enhanced detail provided in Fig. 1B) facing the first semiconductor chip; and
an insulating layer (177) that encloses the second pad (horizontally including) in a third plane that is parallel to the surface of the first semiconductor chip (Fourth Plane, See annotated figure),
wherein a height of a first surface of the insulating element with respect to the first semiconductor chip decreases as a distance from the second semiconductor chip increases.
Dabral teaches the insulating element is formed upon the second semiconductor chip but lacks: details regarding the shape of the element; or details of the manufacturing technique that would produce variations in shape of the element. Thus, Dabral fails to teach “wherein a height of a first surface of the insulating element with respect to the first semiconductor chip decreases as a distance from the second semiconductor chip increases”.
Yu discloses the insulating element (Fig. 5: 130) is formed upon the second semiconductor chip (114A), wherein a height of a first surface of the insulating element with respect to the first semiconductor chip decreases as a distance from the second semiconductor chip increases (See annotated figure for height measurements). Yu further teaches the height configuration is a characteristic of the manufacturing process ([0024]: “As a result of the planarization process, a top surface of the encapsulant 130 may be uneven”).
Using the known technique of Yu when manufacturing the insulating element of Dabral would arrive at the claimed height configuration. A person of ordinary skill in the art before the effective filing date would have had predictable results including the claimed height configuration because in each situation, the same manufacturing sequence is used on similar devices in the same way: by firstly forming an insulating element; and then disposing a redistribution substrate is the insulating element (Dabral: [0075]: “routing layer 302 is formed over a reconstituted structure including dies 102 face up and embedded in a gap fill material 360”; Yu: Figs. 5-21 show a sequence disposing the redistribution substrate 160 on the insulating element 130). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed height configuration because it is a characteristic of a known technique used for manufacturing a substantially similar product in the same way. MPEP 2143 (I)(C).
Illustrated below is a marked and annotated figure of Fig. 6A of Yu.
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Regarding claim 12, Dabral in view of Yu discloses the semiconductor package of claim 11 (Dabral: Fig. 14), wherein the first surface of the insulating element (See annotated figure) and a first surface of the protection layer (132) are in direct contact each other (direct contact is shown. Note: the interpretation is consistent with Applicant’s disclosure in Figs. 1 and 10: the contact between element 280 and layer 270) at an interface therebetween (direct interface of element 360 with layer 139).
Regarding claim 13, Dabral in view of Yu discloses the semiconductor package of claim 11 (Yu: Fig. 6A),
wherein the height of the first surface of the insulating element is different from a height of a first surface of the protection layer by 1 nm to 1 µm with respect to the first semiconductor chip.
Dabral in view of Yu fails to teach specific ranges of the height difference and thus fails to teach “wherein the height of the first surface of the insulating element is different from a height of a first surface of the protection layer by 1 nm to 1 µm with respect to the first semiconductor chip”. Nevertheless, Yu does provide guidance on heights of other structures related to the insulating element height difference, and therefore establishes a scale upon which the heights may be related to. For example, Yu teaches an applied material (131) on the insulating element has a height approaching the claimed range ([0025]: “the polymer layer is at least 10 μm”) and teaches this height is greater than the height difference (Fig. 7B: 131 is filling the differences in height and has excess height, as measured by T1). Thus, since the applied material has a thickness greater than the height difference, the height difference (of the insulating element) must be less than 10 μm. This derived height difference (i.e., less than 10 μm) appears to at least approach the claimed range (i.e., “1 nm to 1 µm”). Therefore, the claimed height difference would have been obvious to one having ordinary skill in the art before the effective filing date, since a prima facie case of obviousness exists where the claimed ranges or amounts do not overlap with the prior art but are merely close. Titanium Metals Corp. of America v. Banner, 778 F.2d 775, 783, 227 USPQ 773, 779 (Fed. Cir. 1985). MPEP 2144.05 (I).
Regarding claim 14, Dabral in view of Yu discloses the semiconductor package of claim 11 (Dabral: Fig. 14), wherein a width of the first semiconductor chip is greater than a width of the second semiconductor chip (selecting the specific embodiment disclosed in [0084]: “Alternatively, a die (e.g. 402A) can be bonded to back sides, and span, multiple dies 102A, 102B”. Note: since die 402A spans multiple chips, chip 402A must have a width “greater than” underlying chip 102A).
Regarding claim 15, Dabral in view of Yu discloses the semiconductor package of claim 11 (Dabral: Fig. 14), wherein the protection layer comprises at least one of oxide, nitride, or tetraethyl orthosilicate (TEOS) ([0051]: “a dielectric material such as an oxide (e.g. SiO2)”).
Regarding claim 16, Dabral in view of Yu discloses the semiconductor package of claim 11, wherein the insulating element comprises an epoxy molding compound (EMC).
Dabral fails to teach specific materials for the insulating element beyond generic molding compounds (Dabral: [0076]: “Suitable materials include molding compounds, oxides, and other materials such as silicon pastes, etc.”). Thus, Dabral in view of Yu fails to teach “wherein the insulating element comprises an epoxy molding compound (EMC)”. Nevertheless, this is a known material configuration in the prior art for insulating materials, as taught by Yu, wherein the insulating element (Fig. 6A: 130) comprises an epoxy molding compound (EMC) ([0023]: “The encapsulant 130 may be a molding compound, epoxy, or the like”). A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success including the “epoxy molding compound” configuration (of Yu) for the insulating element because: Dabral teaches a material of the insulating element may be varied among moldings ([0076]: “Suitable materials include molding compounds, oxides, and other materials such as silicon pastes, etc.”); and in each situation the material is performing the function of an insulating element enclosing chips (Yu: Fig. 6A: molding 130 and chip 114A; Dabral: molding 360 and chip 102A). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed material configuration because it is a known configuration of substantially similar insulating elements. MPEP 2143 (I)(A).
Claims 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Dabral in view of Chiou.
Regarding independent claim 17, Dabral discloses a semiconductor package (Fig. 14), comprising:
a redistribution substrate (302);
a lower semiconductor chip (102A) on the redistribution substrate (vertically on);
an upper semiconductor chip (402A) on the lower semiconductor chip (vertically on); and an insulating element (360) between (vertically between without requiring any specific overlap. See annotated figure for direction designation) the redistribution substrate and the upper semiconductor chip, wherein the insulating element encloses the lower semiconductor chip (horizontally encloses) in a first plane that is parallel to the redistribution substrate (See annotated figure),
wherein the lower semiconductor chip comprises:
a first pad (112 or 138, enhanced detail provided in Fig. 1B) at a bottom surface of the lower semiconductor chip (132);
a protection layer (139, See annotated figure, enhanced detail provided in Fig. 1B) that encloses the first pad (horizontally encloses) in a second plane that is parallel to the redistribution substrate (See annotated figure);
a penetration via (170) that penetrates the lower semiconductor chip (vertically penetrates at least a portion) and is electrically connected to the first pad (The schematic of Fig. 1A shows vias 170 electrically connected to pads 112. This electrical routing is similarly described in [0047]: “bypass routing”);
a second pad (174, of chip 102A) on a first surface of the upper semiconductor chip facing the lower semiconductor chip (See annotated figure for surface designation. 174 is vertically directly touching upper chip 402A, thus it is “on” the first surface); and
an lower insulating layer (477) that encloses the second pad (layer 477 encloses pad 174 in directions between horizontal and vertical from the pad. Note: this interpretation is consistent with Applicant’s disclosure Fig. 1: pad 230, layer 340) in a third plane that is parallel to the redistribution substrate (See annotated figure),
wherein the upper semiconductor chip comprises:
a third pad (474) on first surface of the upper semiconductor chip facing the lower semiconductor chip (474 is part of the first surface, thus it is “on” the first surface); and
an upper insulating layer (177) that encloses the third pad (layer 177 encloses pad 474 in directions between horizontal and vertical from the pad. Note: this interpretation is consistent with Applicant’s disclosure Fig. 1: pad 330, layer 240) in a fourth plane that is parallel to the redistribution substrate (See annotated figure),
wherein the insulating element comprises an epoxy molding compound (EMC), and
wherein the second pad and the third pad are in direct contact with each other ([0085]: “a metal-metal bond as with hybrid bonding”) at an interface (a direct interface is illustrate; [0085]: “a dielectric bonding layer 477 (e.g. oxide or polymer) that bonds with the back side passivation layer 177”) where the lower semiconductor chip and the upper semiconductor chip are in contact with each other (direct contact), and comprise a same material to form a unitary structure (these pads are united and therefore form “a unitary structure”; Dabral: [0085]: “a metal-metal bond as with hybrid bonding”).
Dabral fails to teach specific materials for the insulating element beyond generic molding compounds (Dabral: [0076]: “Suitable materials include molding compounds, oxides, and other materials such as silicon pastes, etc.”). Thus, Dabral fails to teach “wherein the insulating element comprises an epoxy molding compound (EMC)”.
Chiou discloses an insulating element (Fig. 4: 110) that comprises an epoxy molding compound (EMC) ([0038]: “The molding material includes a polymer material and optionally includes fillers. The polymer material may be an epoxy or the like”). Modifying the material of the insulating element (of Dabral) by including the material of Chiou would arrive at the claimed material configuration. A person of ordinary skill in the art before the effective filing date would have a reasonable expectation of success doing so because: Dabral teaches a material of the insulating element may be varied among moldings ([0076]: “Suitable materials include molding compounds, oxides, and other materials such as silicon pastes, etc.”); and in each situation the material is performing the function of an insulating element enclosing chips (Chiou: Fig. 4: molding 110 and chip 50A; Dabral: molding 360 and chip 102A). Chiou provides a teaching to motivate one of ordinary skill in the art before the effective filing date to include the material of the insulating element in that it would enable using materials that improve package strength ([0038]: “The fillers are formed of a material that provides mechanical strength and thermal dispersion for the encapsulant”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed material configuration because it would enable improved package strength. MPEP 2143 (I)(G).
Dabral fails to teach specific materials for the second and third pads beyond these pads being metal ([0085]: “this may be a metal-metal bond as with hybrid bonding”). Thus, Dabral in view of Chiou as previously applied fails to teach “and comprise a same material”. Nevertheless, this is a known material configuration in the prior art for pads in direct contact with each other, as taught by Chiou ([0032]: “the material of the die connectors 56, 76 (e.g., copper) intermingles, so that metal-to-metal bonds are also formed”). A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success including the “same material” configuration (of Chiou) for the second and third pads because in each situation, the pads are directly connected metal pads (Dabral: Fig. 14: pads 174/474; Chiou: Fig. 2: pads 56/76). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed material configuration because it is a known configuration of substantially similar pads. MPEP 2143 (I)(A).
Regarding claim 18, Dabral in view of Chiou discloses the semiconductor package of claim 17 (Dabral: Fig. 14), wherein a width of the lower semiconductor chip is less than a width of the upper semiconductor chip (selecting the specific embodiment disclosed in [0084]: “Alternatively, a die (e.g. 402A) can be bonded to back sides, and span, multiple dies 102A, 102B”. Note: since die 402A spans multiple chips, the underlying chip 102A must have a width “less than” chip 402A).
Regarding claim 19, Dabral in vi3ew of Chiou discloses the semiconductor package of claim 17 (Dabral: Fig. 14), wherein the protection layer comprises at least one of oxide, nitride, or tetraethyl orthosilicate (TEOS) ([0051]: “a dielectric material such as an oxide (e.g. SiO2)”).
Regarding claim 20, Dabral in view of Chiou discloses the semiconductor package of claim 17 (Dabral: Fig. 14), wherein the bottom surface of the lower semiconductor chip is in direct contact with a first surface of the redistribution substrate (350, See annotated figure, direct contact is shown), and wherein the first pad of the lower semiconductor chip is in direct contact with a redistribution pad of the redistribution substrate (312 or 338, direct contact is shown).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM H ANDERSON whose telephone number is (571)272-2534. The examiner can normally be reached Monday-Friday, 8:00-5:00.
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/WILLIAM H ANDERSON/ Examiner, Art Unit 2817