The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA
DETAILED ACTION
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 32-36 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
There is no support in the elected embodiment of figures 3-4 for the claimed limitation of a “spacer”, as recited in claims 32-36.
It is noted that on 12/26/2024 applicants withdrew claims 7-9, which recite the formation of a spacer, from consideration, as being directed to a non-elected embodiment.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 16, 18 and 30-36 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (11,450,722).Regarding claims 1, 16 and 32, Kim et al. teach in figure 5 and related text a display device comprising:
a substrate having an active area DA and a non-active area NDA (see figure 1);
a light emitting diode EL in the active area, the light emitting diode having an anode AE and a cathode CE;
a drive transistor DT in the active area, the drive transistor having a first semiconductor layer 350, a source-drain electrode 350a coupled to a first side of the first semiconductor layer, a second source-drain electrode 350b coupled to a second side of the first semiconductor layer, and a first gate electrode 310;
a gate dielectric 130 positioned overlying the first semiconductor layer 350a and positioned between the first semiconductor layer 350a and the first gate electrode 310;
a first insulating layer 140 overlying the first gate electrode;
a second insulating layer 150 overlying the first insulating layer;
a switching transistor ST1 having a second semiconductor layer 450c and a second gate electrode 410 the switching transistor positioned overlying the second insulating layer;
a third insulating layer 170 overlying the second gate electrode 410;
a first metal layer 810/830/850 overlying the third insulating layer 170 and having portions positioned over the drive and switching transistors;
a first contact hole CT2/CT3 extending through the first, second and third insulating layers, the first contact hole being positioned over the drive transistor DT;
a second contact hole CT3 in the third insulating layer 170, the second contact hole CT3 being positioned over at least one side of the second semiconductor layer 450c of the switching transistor ST; and
a bank 195 overlying the third insulating layer and being disposed to expose an emission region OL of an anode AE, the bank 195 having a first flat portion (the top of the bank) overlapping an end of the anode AE at one side and a second flat portion (the bottom of the bank) surrounding the emission region of the anode AE, the first flat portion having a region higher than the second flat portion.
wherein each of the first source-drain electrode and the second source-drain electrode of the drive transistor in the first contact hole comprises the first layer and directly contacts the first semiconductor layer, and wherein a source-drain electrode of the switching transistor in the second contact hole comprises the first layer.
Kim et al. do not explicitly state forming the first and second electrodes comprise of metal and do not teach that the first contact hole continuously extending through the first, second and third insulating layers.It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the first and second electrodes of metal and to form the first contact hole continuously extending through the first, second and third insulating layers in Kim et al.’s device, in order to simplify the processing steps of making the device by using conventional materials and processes, respectively.
Furthermore, regarding the claimed limitations of forming the first and second electrodes of metal and forming the first contact hole continuously extending, these are process limitations which would not carry patentable weight in this claim drawn to a structure, because distinct structure is not necessarily produced. The formation of the second electrode as part of the first metal layer and forming a continuous one first contact hole (instead of forming two continuous first contact holes) does not produce different structures wherein one structure which is different from a structure wherein the first metal layer is not formed as part of the second electrode.
Note that a “product by process” claim is directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wertheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); and In re Marosi et al., 218 USPQ 289, all of which make it clear that it is the patentability of the final product per se which must be determined in a “product by process” claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in “product by process” claims or not. Note that the applicant has the burden of proof in such cases, as the above case law makes clear.
Regarding claims 32 and 34, prior art does not teach a spacer. It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form a spacer wherein the spacer comprises substantially the same material as the bank in prior art’s device in order to simplify the processing steps of making the device by forming the bank and the spacer in one processing step.
Regarding claims 2 and 16, Kim et al. teach in figure 5 and related text that the first region is electrically connected to the anode of the light emitting diode and the second region is having an electrical connection to the drive transistor and
wherein a first semiconductor layer 350a of the drive transistor (at lease part thereof) is horizontally spaced from a second semiconductor layer of the switching transistor ST1, and
wherein one electrode 810/830 being comprised of the first metal layer is disposed at a horizontal interval between the first semiconductor layer 350 of the drive transistor and the second semiconductor layer of the switching transistor ST1.
Regarding claims 2 and 33, Kim et al. teach in figure 5 and related text an overlap pattern 430 overlapping a gate and overlaying the second insulating layer 150, wherein the first semiconductor layer 350 is a polysilicon semiconductor and the second semiconductor layer 450 is an oxide semiconductor. Kim et al. do not explicitly state that the overlap pattern overlapping a gate line. It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the overlap pattern overlapping the gate line in prior art’s device, in order to operate the device in its intended use by connecting the gate electrode to the gate line.
Regarding claims 18 and 36, as discussed in claim 2 above, the modified device of Kim et al. teach an overlap pattern overlapping a gate line and overlaying the second insulating layer.
Kim et al. do not teach a light shielding member positioned between the substrate and the second semiconductor layer and is in the same layer as the gate electrode of the drive transistor and is comprised of a same material as the gate electrode of the drive transistor, and wherein the overlap pattern comprises a first layer in the same layer as the second semiconductor layer and a second layer in the same layer as a gate electrode of the switching transistor.
Kim et al. teach in related text that the electrodes can comprise a first layer in the same layer as the second semiconductor layer and a second layer in the same layer as a gate electrode of the switching transistor.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form a light shielding member positioned between the substrate and the second semiconductor layer and in the same layer as the gate electrode of the drive transistor and is comprised of a same material as the gate electrode of the drive transistor, and to form the overlap pattern comprises a first layer in the same layer as the second semiconductor layer and a second layer in the same layer as a gate electrode of the switching transistor, in prior art’s device in order to improve the device characteristics by using the well-known light shielding member, and in order to simplify the processing steps of making the device (by forming the light shielding member of a same material as the gate electrode of the drive transistor), respectively.
Regarding claim 35, prior art does not teach that the bank and the spacer comprise opaque material. It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the bank and the spacer comprise opaque material in prior art’s device, in order to simplify the processing steps of making the device.
Response to Arguments
1. Applicants argue that Kim does not teach that the bank having a first flat portion overlapping an end of the anode at one side and a second flat portion surrounding the emission region of the anode, the first flat portion having a region higher than the second flat portion.
1. Kim teaches in figure 5 that bank 195 having a first flat portion (the top of the bank) overlapping an end of the anode AE at one side and a second flat portion (the bottom of the bank) surrounding the emission region of the anode AE, the first flat portion having a region higher than the second flat portion.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached on 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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O.N. /ORI NADAV/
7/24/2026 PRIMARY EXAMINER
TECHNOLOGY CENTER 2800