DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
2. Applicant’s election with traverse of Invention I, identified as encompassing claims 1-15 is acknowledged.
The arguments present the opinion that there is no excess examination burden due to the number of claims to which the Examiner disagrees for reasons detailed in the requirement for restriction.
Therefore, the restriction is maintained and made final.
Note by the Examiner
3. For clarity, the reference to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented un-bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and Examiner explanations for 102 &/or 103 rejections have been provided in parenthesis.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
4. Claims 1-15 are rejected under 35 U.S.C. 102(a2) as being anticipated by Kubo et al. (US 2023/0246085 A1), hereinafter as K1
5. Regarding Claim 1, K1 discloses a semiconductor memory device (see Figs. 1-11C, 18A-E, and [0131] “Referring to FIGS. 1-14 and according to various embodiments of the first exemplary structure, a semiconductor structure comprises an alternating stack of insulating layers 32 and electrically conductive layers 46; a memory opening 49” Selected in particular as the embodiment of Fig. 18A-E) comprising:
a stack structure (elements 32,46, see [0044] “insulating layers 32” and [0107] “conductive layers 46”) on a substrate (element 9,10, see [0036] “substrate (9,10)”), extending in a first direction (first lateral direction in the cross-section of Fig. 18E), and including gate electrode layers (see [0109] “Each electrically conductive layer 46 can function as a combination of a plurality of control gate electrodes located at a same level and a word line electrically interconnecting”) and insulating layers (see [0043]) stacked alternately with each other (see Fig. 18E);
a vertical structure (elements 62, 60, see [0083] “dielectric cores 62” and [0086] “semiconductor channel 60”) including a vertical channel film (element 60) extending in a second direction (vertical direction in the cross-section of Fig. 18E) crossing the first direction and a channel insulating film (element 56, 54, 52S, see [0075] “the dielectric material liner 56”, [0072] “memory material layer 54 may include a charge storage material such as silicon nitride, polysilicon, or a metallic material (e.g., floating gate material), a ferroelectric material that can store information in the form of a ferroelectric polarization direction, or any other memory material that can store date by altering electrical resistivity”, [0171] “silicon oxide blocking dielectric layer 52S”) on the vertical channel film and having first areas (area of element 54S laterally overlapping elements 32) adjacent to the insulating layers and second areas (area of element 54S laterally contacting elements 44) adjacent to the gate electrode layers (see Fig. 18E); and
a high-k film (elements 512, 44 see [0104, 0135]) on the channel insulating film (see Fig. 18E),
wherein the high-k film includes a first high-k metal oxide film (element 512, see [0135] “dielectric metal oxide spacer layer 512 comprises, and/or consists essentially of, a dielectric metal oxide material, such as aluminum oxide”) between the first areas and the insulating layers and in contact with the first areas, and a second high-k metal oxide (element 44, see [0104] “a dielectric oxide of at least one transition metal element, a dielectric oxide of at least one Lanthanide element, a dielectric oxide of a combination of aluminum, at least one transition metal element, and/or at least one Lanthanide element” Selected as comprising lanthanum oxide) film between the second areas and the gate electrode layers and in contact with the second areas, and
the first high-k metal oxide film and the second high-k metal oxide films include different metal materials (aluminum oxide compared to lanthanum oxide).
6. Regarding Claim 2, K1 discloses the semiconductor memory device of claim 1, wherein
the channel insulating film includes a tunnel insulating film (element 56, see [0187]), a charge storing film (element 54, [0072]), and a blocking insulating film (element 52S , see [0171]) that are sequentially arranged on the vertical channel film (see Fig. 18E), and
each of the first high-k metal oxide film and the second high-k metal oxide films is in contact with the blocking insulating film (see Fig. 18E).
7. Regarding Claim 3, K1 discloses the semiconductor memory device of claim 2, wherein the blocking insulating film has a first thickness (thickness of element 52S) on the first high-k metal oxide film and includes silicon oxide (see [0171] “silicon oxide blocking dielectric layer 52S”).
8. Regarding Claim 4, K1 discloses the semiconductor memory device of claim 1, further comprising:
a passivation film (element 511’, see [0134] “silicon oxide spacer layer 511”) between the first high-k metal oxide film and the insulating layers (see Fig. 18E).
9. Regarding Claim 5, K1 discloses the semiconductor memory device of claim 4, wherein the passivation film has a second thickness (see Fig. 18E; note, the manner in which the claim is currently recited does not require any relationship between the thicknesses) on the insulating layers and includes silicon oxide (see [0134]).
10. Regarding Claim 6, K1 discloses the semiconductor memory device of claim 1, wherein the second high-k metal oxide film is arranged along a surface of the gate electrode layers and is in contact with each insulating layer of the insulating layers and the first high-k metal oxide film (see Fig. 18E).
11. Regarding Claim 7, K1 discloses the semiconductor memory device of claim 2, wherein
the first high-k metal oxide film has a third thickness (thickness of element 512) on the blocking insulating film, and
the second high-k metal oxide film has a fourth thickness (thickness of element 44; note, the manner in which the claim is currently recited does not require any relationship between the thicknesses) on the blocking insulating film.
12. Regarding Claim 8, K1 discloses the semiconductor memory device of claim 1, further comprising:
a barrier conductive film (element 46A, see [0105] “metallic barrier layer 46A”) between the gate electrode layers (element 46B, see [0106] “metallic fill material layer 46B”) and the second high-k metal oxide film (see Fig. 18E).
13. Regarding Claim 9, K1 discloses the semiconductor memory device of claim 1, wherein a difference between electronegativity of a metal atom and electronegativity of an oxygen atom of the first high-k metal oxide film is smaller than a difference between electronegativity of a metal atom and electronegativity of an oxygen atom of the second high-k metal oxide film (the first high-k metal oxide film is aluminum oxide and the second comprises lanthanum oxide which has a material property which meets the claimed limitations; further, note the material disclosed in the prior art overlaps with the Applicant’s said to have the same property).
14. Regarding Claim 10, K1 discloses the semiconductor memory device of claim 1, wherein each of the first high-k metal oxide film and the second high-k metal oxide films includes at least one of aluminum oxide (the first high-k metal oxide film is aluminum oxide), hafnium oxide, yttrium oxide, lanthanum oxide (the second high-k metal oxide film comprises lanthanum oxide), and zirconium oxide.
15. Regarding Claim 11, K1 discloses a semiconductor memory device (see Figs. 1-11C, 18A-E, and [0131] “Referring to FIGS. 1-14 and according to various embodiments of the first exemplary structure, a semiconductor structure comprises an alternating stack of insulating layers 32 and electrically conductive layers 46; a memory opening 49” Selected in particular as the embodiment of Fig. 18A-E) comprising:
a stack structure (elements 32,46, see [0044] “insulating layers 32” and [0107] “conductive layers 46”) on a substrate (element 9,10, see [0036] “substrate (9,10)”) and including gate electrode layers (see [0109] “Each electrically conductive layer 46 can function as a combination of a plurality of control gate electrodes located at a same level and a word line electrically interconnecting”) and insulating layers (see [0043]) stacked alternately with each other (see Fig. 18E);
a vertical structure (elements 62, 60, see [0083] “dielectric cores 62” and [0086] “semiconductor channel 60”) including a vertical channel film (element 60) and a channel insulating film (element 56, 54, 52S, see [0075] “the dielectric material liner 56”, [0072] “memory material layer 54 may include a charge storage material such as silicon nitride, polysilicon, or a metallic material (e.g., floating gate material), a ferroelectric material that can store information in the form of a ferroelectric polarization direction, or any other memory material that can store date by altering electrical resistivity”, [0171] “silicon oxide blocking dielectric layer 52S”) and extending in a direction (lateral direction in the cross-section view of Fig. 18E) in which the vertical structure penetrates through the stack structure (see Fig. 18E), the channel insulating film including a tunnel insulating film (element 56, see [0187]), a charge storing film (element 54, [0072]), and a blocking insulating film (element 52S , see [0171]) sequentially disposed on the vertical channel film (see Fig. 18E) and having first areas (area of element 54S laterally overlapping elements 32) adjacent to the insulating layers and second areas (area of element 54S laterally contacting elements 44) adjacent to the gate electrode layers (see Fig. 18E);
a passivation film (element 511’, see [0134] “silicon oxide spacer layer 511”) between the channel insulating film and the insulating layers (see Fig. 18E);
a first high-k metal oxide film (element 512, see [0135] “dielectric metal oxide spacer layer 512 comprises, and/or consists essentially of, a dielectric metal oxide material, such as aluminum oxide”) on the first areas and in contact with the blocking insulating film; and
a second high-k metal oxide film (element 44, see [0104] “a dielectric oxide of at least one transition metal element, a dielectric oxide of at least one Lanthanide element, a dielectric oxide of a combination of aluminum, at least one transition metal element, and/or at least one Lanthanide element” Selected as comprising lanthanum oxide) on the second areas and in contact with the blocking insulating film,
wherein the first high-k metal oxide film and the second high-k metal oxide films include different metal materials (aluminum oxide compared to lanthanum oxide).
16. Regarding Claim 12, K1 discloses the semiconductor memory device of claim 11, wherein the second high-k metal oxide film extends in a direction in which the second high-k metal oxide film penetrates through the passivation film and the first high-k metal oxide film (see Fig. 18E element 44 extends in a lateral direction to penetrate through element 511 and 512).
17. Regarding Claim 13, K1 discloses the semiconductor memory device of claim 11, further comprising:
a barrier conductive film (element 46A, see [0105] “metallic barrier layer 46A”) between the gate electrode layers (element 46B, see [0106] “metallic fill material layer 46B”) and the insulating layers and in contact with the second high-k metal oxide film (see Fig. 18E).
18. Regarding Claim 14, K1 discloses the semiconductor memory device of claim 11, wherein a difference between electronegativity of a metal atom and electronegativity of an oxygen atom of the first high-k metal oxide film is smaller than a difference between electronegativity of a metal atom and electronegativity of an oxygen atom of the second high-k metal oxide film (the first high-k metal oxide film is aluminum oxide and the second comprises lanthanum oxide which has a material property which meets the claimed limitations; further, note the material disclosed in the prior art overlaps with the Applicant’s said to have the same property).
19. Regarding Claim 15, K1 discloses the semiconductor memory device of claim 11, wherein each of the first high-k metal oxide film and the second high-k metal oxide films includes at least one of aluminum oxide (the first high-k metal oxide film is aluminum oxide), hafnium oxide, yttrium oxide, lanthanum oxide (the second high-k metal oxide film comprises lanthanum oxide), and zirconium oxide.
Conclusion
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/SAMUEL PARK/Examiner, Art Unit 2818
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