DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/24/2023 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The abstract and title are consistent with the requirements set forth in the MPEP 608.01(b) and 606, respectively.
Claim Objections
Claims 1, 10 and 16 are objected to because of the following informalities: the first instance of “3D” in the independent claims should be written in its expended for “three-dimensional (3D)” before using the abbreviation throughout the claims. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 8-9, 16 and 19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Song et al. US PGPub. 2023/0317677. Regarding claim 1, Song teaches a 3D integrated circuit structure (100, fig. 1) [0025], comprising: a redistribution layer structure (108, fig. 1) [0026]; a first semiconductor chip die (104(1), fig. 1) [0026] on the redistribution layer structure (108); a plurality of core balls (138, fig. 1) [0028] on the redistribution layer structure (108) and adjacent the first semiconductor chip die (104(1)); a molding material (130, fig. 1) [0028] surrounding the first semiconductor chip die (104(1)) and the plurality of core balls (138); an interconnection structure (128+136, fig. 1) [0027] on the molding material (130); and a second semiconductor chip die (104(2), fig. 1) [0026] on the interconnection structure (128+136), wherein a footprint of the first semiconductor chip die (104(1)) and footprints of the plurality of core balls (138) are within a footprint of the second semiconductor chip die (104(2)) (Song et al., fig. 1).
Regarding claim 8, Song teaches the 3D integrated circuit structure of claim 1, wherein the plurality of core balls (138) are adjacent one (left) side of the first semiconductor chip die (104(1)) (Song et al., fig. 1). Regarding claim 9, Song teaches the 3D integrated circuit structure of claim 1, wherein some of the plurality of core balls (138) are adjacent one (left) side of the first semiconductor chip die (104(1)), and other ones of the plurality of core balls are adjacent another (right) side of the first semiconductor chip die (104(1)) (Song et al., fig. 1).
Regarding claim 16, Song teaches a method for manufacturing a 3D integrated circuit structure (100, fig. 1) [0025], the method comprising: forming a first redistribution layer structure (108, fig. 1) [0026]; bonding a plurality of core balls (138, fig. 1) [0028] on the first redistribution layer structure (108); mounting a first semiconductor chip die (104(1), fig. 1) [0026] on the first redistribution layer structure (108); encapsulating the first semiconductor chip die (104(1)) and the plurality of core balls (138) with molding material (130, fig. 1) [0028]; and electrically coupling (via 136+128+138+108, fig. 1) a second semiconductor chip die (104(2), fig. 1) [0026] to the first semiconductor chip die (104(1)) and the plurality of core balls (138), wherein a footprint of the first semiconductor chip die (104(1)) and footprints of the plurality of core balls (138) are within a footprint of the second semiconductor chip die (104(2)) (Song et al., fig. 1). Regarding claim 19, Song teaches the method of claim 16, wherein the electrical coupling (via 136+128+138+108, fig. 1) of the second semiconductor chip die (104(2)) to the first semiconductor chip die (104(1)) and the plurality of core balls (138) comprises: forming a second redistribution layer structure (128, fig. 1) [0027] on the first semiconductor chip die (104(1)) and the plurality of core balls (138); and mounting the second semiconductor chip die (104(2)) on the second redistribution layer structure (128) (Song et al., fig. 1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over Song et al. US PGPub. 2023/0317677 as applied to claim 1 above, and further in view of Nishino et al. US PGPub. 2020/0061757. Regarding claim 2, Song does not teach the 3D integrated circuit structure of claim 1, wherein each core ball (138) comprises an inner core and a first outer conductive layer covering the inner core. However, Nishino teaches a core ball (1A, fig. 1) [0034] comprising an inner core (2A, fig. 1) [0034] and a first outer conductive layer (3A, fig. 1) [0034] covering the inner core (2A) (Nishino et al., fig. 1). At the time before the effective filing of the claimed invention, it would have been obvious to one of ordinary skill in the art to make the simple substitution of the core ball of Song with the core ball of Nishino because he core ball having inner core and outer conductive layer taught by Nishino is well known in the art and such structure is art recognized and suitable for the intended purpose of suppressing connection short-circuiting when terminal pitches are narrow( Nishino et al., [0037]) and prevent electromigration (Nishino et al., [0005]) (see MPEP 2144.07). Regarding claim 5, Nishino teaches the 3D integrated circuit structure of claim 2, wherein the inner core (2A) comprises copper or a copper alloy [0035] (Nishino et al., fig. 1, [0035]).
Regarding claim 6, Song in view of Nishino teaches the 3D integrated circuit structure of claim 2, wherein the first outer conductive layer (3A, fig. 1) [0038] comprises a SAC solder alloy including tin (Sn), silver (Ag), and copper (Cu) [0038], [0073] (Nishino et al., fig. 1, [0038]).
Regarding claim 7, Song in view of Nishino teaches the 3D integrated circuit structure of claim 2, wherein each core ball (1A) further comprises a second outer conductive layer (4, fig. 1) [0044] on the first outer conductive layer (3A) (Nishino et al., fig. 1, [0044]).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Song et al. US PGPub. 2023/0317677 in view of Nishino et al. US PGPub. 2020/0061757 as applied to claim 2 above, and further in view of Darveaux et al. US PGPub. 2020/0077510.
Regarding claim 3, Song in view of Nishino does not teach the 3D integrated circuit structure of claim 2, wherein the core ball (1A, fig. 1) further comprises an upper conductive connection member and a lower conductive connection member extending from the first outer conductive layer, wherein the upper conductive connection member and the lower conductive connection member each comprise a flat bonding surface. However, Darveaux teaches a 3D integrated circuit structure (100, fig. 6) [0055] wherein the core ball (120, fig. 6) [0055] further comprises an upper conductive connection member (142 top, fig. 6) [0061] and a lower conductive connection member (142 bottom, fig. 6) [0061] extending from the first outer conductive layer (142 portion surrounding 144, fig. 6) [0061], wherein the upper conductive connection member (142 top) and the lower conductive connection member (142 bottom) each comprise a flat bonding surface (fig. 6) (Darveaux et al., fig. 6). At the time before the effective filing of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify the core ball of Song and Nishino by adding the upper and lower connection members as taught by Darveaux because such structure is well known in the art and such material/structure is art recognized and suitable for the intended purpose of providing enhanced support that is electrically conducting and prevent collapse of the structure (Darveaux et al., [0063]) (see MPEP 2144.07).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Song et al. US PGPub. 2023/0317677 in view of Nishino et al. US PGPub. 2020/0061757 as applied to claim 2 above, and further in view of Pagaila et al. US PGPub. 2010/0237495.
Regarding claim 4, Song in view of Nishino does not teach the 3D integrated circuit structure of claim 2, wherein the inner core (2A) comprises a plastic material including a thermoplastic resin, a thermosetting resin, or a polymer material. However, Pagaila teaches a 3D integrated circuit (fig. 10) [0112], wherein the inner core (298, fig. 10) [0112) comprises a plastic material including a thermoplastic resin, a thermosetting resin, or a polymer material [0112] (Pagaila et al., fig. 10, [0112]). At the time before the effective filing of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify the core ball of Song and Nishino by using a polymer core material as taught by Pagaila because such structure is well known in the art and such material/structure is art recognized and suitable for the intended purpose of providing reduces stress junctions (Pagaila et al., [0112]) (see MPEP 2144.07).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Song et al. US PGPub. 2023/0317677 in view of Pagaila et al. US PGPub. 2010/0237495. Regarding claim 17, Song does not teach the method of claim 16, wherein the bonding of the plurality of core balls (138) on the first redistribution layer structure (108) is performed by a reflow process. However, Pagaila teaches a reflow process [0037] for bonding of the plurality of core balls (78, fig. 2C) [0037] on the first redistribution layer structure (76, fig. 2c) [0037] (Pagaila et al., fig. 2c).
At the time before the effective filing of the claimed invention, it would have been obvious to one of ordinary skill in the art to make the simple substitute of the bonding process of Song with the reflow process of Pagaila because reflow of core balls or solder balls is very well known in the art and such substitution is art recognized equivalence for the same purpose (for electrical and mechanical connection, Pagaila et al., [0037]) to obtain predictable results (see MPEP 2144.06).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Song et al. US PGPub. 2023/0317677 in view of Tsai et al. US PGPub. 2023/0057113.
Regarding claim 18, Song does not teach the method of claim 16, wherein after the encapsulating the first semiconductor chip die (104(1)) and the plurality of core balls (138), the method further comprises performing a chemical-mechanical polishing (CMP) process on the molding material (130). However, Tsai teaches a method (fig. 9-10) wherein after the encapsulating (126, fig. 9) [0037] the first semiconductor chip die (120, fig. 9) [0037] and the plurality of core balls (138), the method further comprises performing a chemical-mechanical polishing (CMP) process [0039] on the molding material (126) (Tsai et al., fig. 9-10, [0039]). At the time before the effective filing of the claimed invention, it would have been obvious to one of ordinary skill in the art to make the simple substitute of the planarizing of the encapsulation layer of Song with the CMP process as taught by Tsai because CMP is very well known in the art and such substitution is art recognized equivalence for the same purpose (grinding and polishing to reduce the overall package height) to obtain predictable results (see MPEP 2144.06).
Allowable Subject Matter
Claims 10-15 are allowed.
The following is an examiner’s statement of reasons for allowance: the prior arts of record taken alone or in combination neither anticipates nor renders obvious a 3D integrated circuit structure comprising “a first semiconductor chip die in the molding material and comprising a first surface and a second surface opposite the first surface, wherein the first surface is electrically coupled to the first redistribution layer structure and the second surface is electrically coupled to the interconnection structure” in combination with the limitation wherein “a footprint of the first semiconductor chip die and footprints of the plurality of core balls are within a footprint of the second semiconductor chip die” a recited in claim 10. Claims 11-15 are also allowed for further limiting and depending upon allowed claim 10.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claim 20 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior arts of record taken alone or in combination neither anticipates nor renders obvious a method wherein “the electrical coupling of the second semiconductor chip die to the first semiconductor chip die and the plurality of core balls is performed by hybrid bonding” as recited in claim 20 in combination with the limitation of claim 16 wherein “electrically coupling a second semiconductor chip die to the first semiconductor chip die and the plurality of core balls, wherein a footprint of the first semiconductor chip die and footprints of the plurality of core balls are within a footprint of the second semiconductor chip die.”
Conclusion
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/NDUKA E OJEH/Primary Examiner, Art Unit 2892