DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I (claims 1-12) in the reply filed on February 25, 2026 is acknowledged. Thus, claims 13-20 drawn to non-elected invention have been withdrawn from examination for patentability.
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application KR 10-2023-0012126 filed in Korean Intellectual Property Office (KIPO) on January 30, 2023 and receipt of a certified copy thereof.
Information Disclosure Statement
The information disclosure statement (IDS) filed on October 24, 2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the IDS is considered by the examiner.
Claim Objections
Claim 1 and 7 are objected to because of the following informalities:
In claim 1, line 1, “A 3D integrated circuit structure” should read --A three-dimensional (3D) integrated circuit structure--.
In claim 7, line 1, “A 3D integrated circuit structure” should read --A three-dimensional (3D) integrated circuit structure--.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5 are rejected are rejected under 35 U.S.C. 103 as being unpatentable over Hwang et al. US 2020/0105689.
Regarding claim 1, Hwang teaches a 3D integrated circuit structure (e.g., Figs. 5A-5H, [32]-[47]; also see Fig, 15 and Fig. 16 (similar embodiments to Fig. 5) and the description thereof for additional details), comprising:
a redistribution layer structure (e.g., 240, Fig. 5H);
a first semiconductor chip die (e.g., 210T, Fig. 5H) on the redistribution layer structure;
a plurality of pads (e.g., B24, Fig. 5H) on the redistribution layer structure;
a plurality of conductive posts (e.g., 230, Fig. 5H) disposed adjacent the first semiconductor chip die, wherein the plurality of conductive posts is on the plurality of pads (e.g., Fig. 5H), respectively;
a molding material (e.g., 220, Fig. 5H) that is on the first semiconductor chip die, the plurality of pads, the plurality of conductive posts, and the redistribution layer structure;
an interconnection structure (e.g., T24, 250, Fig. 5H) on the molding material; and
a second semiconductor chip die (e.g., 210B, Fig. 5H) on the interconnection structure,
wherein the second semiconductor chip die overlaps the first semiconductor chip die and the plurality of conductive posts in a vertical direction (e.g., Fig. 5H).
Hwang does not explicitly teach a plurality of sacrificial pads.
Hwang, however, recognizes that the plurality of pads B24 may be utilized to protect the structure from various techniques such as laser drilling, various etching processes, waterjet drilling, ultrasonic drilling, or the like, performed to form the through holes TH (in which the plurality of conductive posts 230 are disposed) (e.g., Fig. 5B, [37]; Fig. 5F), which pertains to the techniques to form the through holes (in which the conductive posts are disposed) and expose the sacrificial pads in Applicant’s original disclosure (e.g., Figs. 11-12 and [100]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the pads of Hwang may function as sacrificial pads for the purpose of protecting the structure from damages that might be caused by various subsequent processes for example.
Regarding claim 2, Hwang teaches the 3D integrated circuit structure of claim 1, wherein a width of an uppermost portion of a conductive post among the plurality of conductive posts is greater than or equal to a width of a lowermost portion of the conductive pos (e.g., Fig. 5H, [37]).
Regarding claim 3, Hwang teaches the 3D integrated circuit structure of claim 1, wherein the plurality of conductive posts include a hardened conductive paste (e.g., [42], [59], [64]).
Regarding claim 4, Hwang teaches the 3D integrated circuit structure of claim 1, wherein the plurality of sacrificial pads include a conductive material, and the conductive material includes aluminum, tungsten, and/or an alloy thereof (e.g., [42]).
Regarding claim 5, Hwang teaches the 3D integrated circuit structure of claim 1, wherein the plurality of conductive posts are adjacent a side surface of the first semiconductor chip die (e.g., Fig. 5H).
Claims 1 and 6-11 are rejected are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. US 2018/0138083.
Regarding claim 1, Kim teaches a 3D integrated circuit structure (e.g., Fig. 22, [135]-[136]; also see Fig. 11 (manufacturing method of the package of Fig. 9 relating to the package of Fig. 22) and the description thereof for additional details), comprising:
a redistribution layer structure (e.g., 140, Fig. 22);
a first semiconductor chip die (e.g., 121, Fig. 22) on the redistribution layer structure;
a plurality of pads (e.g., 122P, 123P, Fig. 22) on the redistribution layer structure;
a plurality of conductive posts (e.g., 122v, 123v, Fig. 22) disposed adjacent the first semiconductor chip die, wherein the plurality of conductive posts is on the plurality of pads (e.g., Fig. 22), respectively;
a molding material (e.g., 130, Fig. 22) that is on the first semiconductor chip die, the plurality of pads, the plurality of conductive posts, and the redistribution layer structure;
an interconnection structure (e.g., 112, 113, Fig. 22) on the molding material; and
a second semiconductor chip die (e.g., 123, Fig. 22) on the interconnection structure,
wherein the second semiconductor chip die overlaps the first semiconductor chip die and the plurality of conductive posts in a vertical direction (e.g., Fig. 22).
Kim does not explicitly teach a plurality of sacrificial pads.
Kim, however, recognizes that the plurality of pads 122P, 123P may be utilized to protect the structure from various techniques such as laser drilling, or the like, performed to form the holes (in which the plurality of conductive posts 122v, 123v are disposed) (e.g., Fig. 11B, [111]), which pertains to the techniques to form the through holes (in which the conductive posts are disposed) and expose the sacrificial pads in Applicant’s original disclosure (e.g., Figs. 11-12 and [100]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the pads of Kim may function as sacrificial pads for the purpose of protecting the structure from damages that might be caused by various subsequent processes for example.
Regarding claim 6, Kim teaches the 3D integrated circuit structure of claim 1, wherein a first subset of conductive posts (e.g., 122v, 123v at the left side of the semiconductor chip die 121, Fig. 22) of the plurality of conductive posts are adjacent a first side surface of the first semiconductor chip die, and a second subset of conductive posts (e.g., 122v, 123v at the right side of the semiconductor chip die 121, Fig. 22) of the plurality of conductive posts are adjacent a second side surface of the first semiconductor chip die.
Regarding claim 7, Kim teaches a 3D integrated circuit structure (e.g., Fig. 22, [135]-[136]; also see Fig. 11 (manufacturing method of the package of Fig. 9 relating to the package of Fig. 22), comprising:
a first redistribution layer structure (e.g., 140, Fig. 22);
a molding material (e.g., 130, Fig. 22) on the first redistribution layer structure;
an interconnection structure (e.g., 110, Fig. 22) on the molding material;
a first semiconductor chip die (e.g., 121, Fig. 22) in the molding material, wherein the first semiconductor chip die is electrically connected to the first redistribution layer structure and the interconnection structure (e.g., Fig. 22, [81]);
a plurality of pads (e.g., 122P, 123P, Fig. 22) in the molding material, wherein the plurality of pads are electrically connected to the first redistribution layer structure (e.g., Fig. 22);
a plurality of conductive posts (e.g., 122v, 123v, Fig. 22) in the molding material, wherein the plurality of conductive posts are adjacent the first semiconductor chip die (e.g., Fig. 22), and wherein the plurality of conductive posts are electrically connected to the plurality of pads and the interconnection structure (e.g., through 140, Fig. 22); and
a second semiconductor chip die (e.g., 123, Fig. 22) on the interconnection structure,
wherein the second semiconductor chip die overlaps the first semiconductor chip die and the plurality of conductive posts in a vertical direction (e.g., Fig. 22).
Kim does not explicitly teach a plurality of sacrificial pads.
Kim, however, recognizes that the plurality of pads 122P, 123P may be utilized to protect the structure from various techniques such as laser drilling, or the like, performed to form the holes (in which the plurality of conductive posts 122v, 123v are disposed) (e.g., Fig. 11B, [111]), which pertains to the techniques to form the through holes (in which the conductive posts are disposed) and expose the sacrificial pads in Applicant’s original disclosure (e.g., Figs. 11-12 and [100]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the pads of Kim may function as sacrificial pads for the purpose of protecting the structure from damages that might be caused by various subsequent processes for example.
Regarding claim 8, Kim teaches the 3D integrated circuit structure of claim 7, wherein the interconnection structure includes a second redistribution layer structure (e.g., 112 of 110, Fig. 22).
Regarding claim 9, Kim teaches the 3D integrated circuit structure of claim 7, wherein the interconnection structure includes a bump (e.g., 113, 112, Fig. 22). Kim does not explicitly teach a micro-bump. It is well known in the art that components of semiconductor devices have been miniaturized in micro/nano scale to increase their integration degree. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the bumps of Kim may be in micro/nano scale for the purpose of increasing the integration degree of the circuit structure for example.
Regarding claim 10, Kim teaches the 3D integrated circuit structure of claim 7, wherein the interconnection structure includes upper bonding pads and lower bonding pads (e.g., 112b, 113b, Fig. 22).
Regarding claim 11, Kim teaches the 3D integrated circuit structure of claim 10, wherein the upper bonding pads and the lower bonding pads are directly in contact with each other, respectively (e.g., Fig. 22).
Claim 12 is rejected are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. US 2018/0138083 in view of Hung et al. US 2015/0132892.
Regarding claim 12, Kim teaches the 3D integrated circuit structure of claim 7 as discussed above.
Kim does not explicitly teach wherein the first semiconductor chip die includes a through silicon via (TSV).
Kim, however, recognizes that the chip dies are connected through the conductive posts in a vertical direction rather than through wire bonding (e.g., [83]).
Hung teaches that wherein the first semiconductor chip die includes a through silicon via (TSV) (e.g., 106, [14], [17], [18]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of Kim to include wherein the first semiconductor chip die includes a through silicon via (TSV) as suggested by Hung for the purpose of enhancing the connection of the chip dies for example (e.g., Hung, [37]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Bo Bin Jang whose telephone number is (571) 270-0271. The examiner can normally be reached on M-F from 9:00 AM to 6:00 PM EST.
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/BO B JANG/Primary Examiner, Art Unit 2818 March 7, 2026