DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to an Application filed on 10/24/2023.
Currently, claims 1-20 are examined as below.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
Acknowledgment is made of applicant's Information Disclosure Statements (IDS) filed on 10/24/2023 and 10/16/2024. The IDS has been considered.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested:
(Marked-Up Version) Semiconductor Devices Having Improved Degree of Integration and Electrical Characteristics
(Clean Version) Semiconductor Devices Having Improved Degree of Integration and Electrical Characteristics
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-12, 14 and 19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Independent claim 1 is indefinite, because:
(1) The limitation “lower surfaces of the first source/drain regions” in lines 18-19 renders the claim indefinite. It is unclear whether such lower surfaces are the same ones as recited earlier in the claim. The limitation will be interpreted as the same lower surfaces.
(2) The limitation “upper surfaces of the second source/drain regions” in lines 19-20 renders the claim indefinite. It is unclear whether such upper surfaces are the same ones as recited earlier in the claim. The limitation will be interpreted as the upper surfaces.
Claim 14 is indefinite, because:
(1) The limitation “lower surfaces of the first source/drain regions” in line 2 renders the claim indefinite. It is unclear whether such lower surfaces are the same ones as recited in the base claim 13. The limitation will be interpreted as the same lower surfaces.
(2) The limitation “upper surfaces of the second source/drain regions” in lines 2-3 renders the claim indefinite. It is unclear whether such upper surfaces are the same ones as recited in the base claim 13. The limitation will be interpreted as the upper surfaces.
Claim 19 is indefinite, because the limitation “lower surfaces of the first source/drain regions” renders the claim indefinite. It is unclear whether such lower surfaces are the same ones as recited in the base claim 18. The limitation will be interpreted as the same lower surfaces.
Note the dependent claims 2-12 necessarily inherit the indefiniteness of the claims on which they depend.
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
Claims 13, 15-18 and 20 are allowed.
Regarding independent claim 13, US 2023/0073078 A1 to Rachmady et al. (“Rachmady”) in Figs. 1a-1c teaches a semiconductor device (Fig. 1a & ¶ 24, integrated circuit structure includes semiconductor bodies 101a), comprising:
insulating patterns 111 (Fig. 1a & ¶ 27, isolation structures 111) extending in a first direction x (Figs. 1a-1c & ¶ 29, x-dimension);
a device isolation layer 121 (Figs. 1a-1c & ¶ 27, isolation structure 121) on side surfaces of the insulating patterns 111;
gate structures 116-118, 122-124 (Fig. 1a & ¶ 27, gate structures 116-118 and 122-124) crossing the insulating patterns 111 and extending in a second direction z (Figs. 1a-1c & ¶ 29, z-dimension; Figs. 1a-1c, ¶ 29 & ¶ 2 disclose the structures 116-118, 122-124 extend in z-dimension);
source/drain regions 109-110, 113-114 (Fig. 1a & ¶ 25-¶ 26, source region 109, drain region 110, source region 113 and drain region 114) on (i.e., in proximity to) the insulating patterns 111 on at least one side of the gate structures 116-118, 122-124; and
contact structures 131, 115 (Fig. 1a & ¶ 26, contacts 131, 115) connected to the source/drain regions 109-110, 113-114, wherein
the source/drain regions 109-110, 113-114 include first source/drain regions 109-110 (Fig. 1a & ¶ 25, source region 109 and drain region 110) and second source/drain regions 113-114 (Fig. 1a & ¶ 26, source region 113 and drain region 114) spaced apart from the first source/drain regions 109-110 in a vertical direction y (Figs. 1a-1c & ¶ 29, y-dimension), perpendicular to the first direction x (Figs. 1a-1c) and to the second direction z (Figs. 1a-1c).
However, the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 13, a via structure between the gate structures and between the source/drain regions; the via structure extends from a same level as lower surfaces of the first source/drain regions to a same level as upper surfaces of the second source/drain regions, and in a cross-section thereof in the second direction, the via structure includes a portion in which a width of the via structure decreases from an upper surface of each of the first source/drain regions toward a lower surface of each of the second source/drain regions in the vertical direction, and includes a portion in which a width of the via structure increases and then decreases from an upper surface of each of the second source/drain regions toward a lower surface of each of the second source/drain regions in the vertical direction.
Therefore, independent claim 13 is allowed.
Claims 15-17 are allowed, because they depend from the allowed claim 13.
Regarding independent claim 18, Rachmady in Figs. 1a-1c teaches a semiconductor device (Fig. 1a & ¶ 24, integrated circuit structure includes semiconductor bodies 101a), comprising:
insulating patterns 111 (Fig. 1a & ¶ 27, isolation structures 111) extending in a first direction x (Figs. 1a-1c & ¶ 29, x-dimension);
a device isolation layer 121 (Figs. 1a-1c & ¶ 27, isolation structure 121) surrounding the insulating patterns 111;
a plurality of channel layers 101a (Fig. 1a & ¶ 24, semiconductor bodies 101a are parts of channel regions) on (i.e., in proximity to) the insulating patterns 111 spaced apart from each other in a vertical direction y (Figs. 1a-1c & ¶ 29, y-dimension, perpendicular to an upper surface of the device isolation layer 121 (Fig. 1a);
barrier layers 105c (Fig. 1a & ¶ 25, gate spacers 105c) on the insulating patterns 111 spaced apart from each other in the vertical direction y (Figs. 1a-1c);
gate structures 116-118, 122-124 (Fig. 1a & ¶ 27, gate structures 116-118 and 122-124) crossing the insulating patterns 111 and surrounding the plurality of channel layers 101a (Fig. 1a), respectively, and extending in a second direction z (Figs. 1a-1c & ¶ 29, z-dimension; Figs. 1a-1c, ¶ 29 & ¶ 2 disclose the structures 116-118, 122-124 extend in z-dimension);
source/drain regions 109-110, 113-114 (Fig. 1a & ¶ 25-¶ 26, source region 109, drain region 110, source region 113 and drain region 114) on (i.e., in proximity to) the insulating patterns 111 on at least one side of the gate structures 116-118, 122-124; and
contact structures 131, 115 (Fig. 1a & ¶ 26, contacts 131, 115) connected to the source/drain regions 109-110, 113-114, wherein
the barrier layers 105c include an upper barrier layer 105c (Fig. 1a & ¶ 25, gate spacer 105c) above an uppermost channel layer 101a (Fig. 1a & ¶ 24, semiconductor body 101a is a part of channel regions) among the plurality of channel layers 101a (Fig. 1a), a lower barrier layer 105c (Fig. 1a & ¶ 25, gate spacer 105c) below a lowermost channel layer 101a (Fig. 1a & ¶ 24, semiconductor body 101a is a part of channel regions) among the plurality of channel layers 101a, and intermediate barrier layers 105c (Fig. 1a & ¶ 25, gate spacers 105c) alternating with the plurality of channel layers 101a,
the source/drain regions 109-110, 113-114 include first source/drain regions 109-110 (Fig. 1a & ¶ 25, source region 109 and drain region 110) and second source/drain regions 113-114 (Fig. 1a & ¶ 26, source region 113 and drain region 114) spaced apart from the first source/drain regions 109-110 in the vertical direction y (Figs. 1a-1c).
However, the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 18, a via structure between the gate structures and between the source/drain regions; the via structure extends from a same level as lower surfaces of the first source/drain regions to a same level as upper surfaces of the second source/drain regions, and in a cross-section thereof in the second direction, a maximum width of the via structure is above the intermediate barrier layers and below the upper barrier layer or on a level higher than the lower barrier layer and lower than the intermediate barrier layers.
Therefore, independent claim 18 is allowed,
Claim 20 is allowed, because claim 20 depends from the allowed claim 18.
Claims 1-12, 14 and 19 are rejected, but would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
PNG
media_image1.png
843
629
media_image1.png
Greyscale
Regarding independent claim 1, US 2023/0073078 A1 to Rachmady et al. (“Rachmady”) in Figs. 1a-1c teaches a semiconductor device (Fig. 1a & ¶ 24, integrated circuit structure includes semiconductor bodies 101a), comprising:
insulating patterns 111 (Fig. 1a & ¶ 27, isolation structures 111) extending in a first direction x (Figs. 1a-1c & ¶ 29, x-dimension);
a device isolation layer 121 (Figs. 1a-1c & ¶ 27, isolation structure 121) on side surfaces of the insulating patterns 111;
gate structures 116-118, 122-124 (Fig. 1a & ¶ 27, gate structures 116-118 and 122-124) crossing the insulating patterns 111 and extending in a second direction z (Figs. 1a-1c & ¶ 29, z-dimension; Figs. 1a-1c, ¶ 29 & ¶ 2 disclose the structures 116-118, 122-124 extend in z-dimension);
source/drain regions 109-110, 113-114 (Fig. 1a & ¶ 25-¶ 26, source region 109, drain region 110, source region 113 and drain region 114) on (i.e., in proximity to) the insulating patterns 111 on at least one side of the gate structures 116-118, 122-124; and
contact structures 131, 115 (Fig. 1a & ¶ 26, contacts 131, 115) connected to the source/drain regions 109-110, 113-114, wherein
the source/drain regions 109-110, 113-114 include first source/drain regions 109-110 (Fig. 1a & ¶ 25, source region 109 and drain region 110) and second source/drain regions 113-114 (Fig. 1a & ¶ 26, source region 113 and drain region 114) spaced apart from the first source/drain regions 109-110 in a vertical direction y (Figs. 1a-1c & ¶ 29, y-dimension), perpendicular to the first direction x (Figs. 1a-1c) and the second direction z (Figs. 1a-1c), and
the contact structures 131, 115 include a first contact structure 131 (Fig. 1a & ¶ 26, contacts 131) contacting lower surfaces of the first source/drain regions 109-110, and a second contact structure 115 (Fig. 1a & ¶ 26, contacts 115) contacting upper surfaces of the second source/drain regions 113-114.
However, the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 1, a via structure between the gate structures and between the source/drain regions; the via structure extends from a same level as lower surfaces of the first source/drain regions to a same level as upper surfaces of the second source/drain regions, and in a cross-section thereof in the second direction, the via structure includes a portion in which a width of the via structure increases and then decreases or decreases and then increases in the vertical direction.
Therefore, independent claim 1 would be allowable.
Claims 2-12 would be allowable, because they depend from the allowable claim 1.
Claim 14 would be allowable, because claim 14 depends from the allowed claim 13.
Claim 19 would be allowable, because claim 19 depends from the allowed claim 18.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2023/0037957 A1 to Thomas et al.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MIKKA LIU whose telephone number is (571)272-2568. The examiner can normally be reached on 9AM-5AM EST M-F.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached on 571-272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/M.L./Examiner, Art Unit 2817
/RATISHA MEHTA/Primary Examiner, Art Unit 2817