Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the application No. 18/493,267 filed on October 24, 2023.
Priority
3. Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
4. Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Specification
5. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: “Semiconductor Device Comprising Trench Gate Along with Separation Layers for Reliability and Productivity”.
Claim Objections
6. Claims 12, 19 are objected to because of the following informalities: In the following, the claims should be recited to avoid indefiniteness due to lack of antecedent basis, and/or to perform grammatical error correction:
12. (Currently Amended) A semiconductor device, comprising:
a substrate including an active region between device separation layers;
a word line intersecting and overlapping the active region;
a word line capping layer covering a top surface of the word line;
a plurality of bit lines interacting and overlapping the active region and extending in a different direction from an extension direction of the word line;
a plurality of buried contacts each connected to the active region;
a plurality of direct contacts each connecting the active region to a corresponding one of the plurality of bit lines;
a fence pattern on top of the word line capping layer; and
a landing pad connected to a corresponding one of the plurality of buried contacts,
wherein the fence pattern is within a fence pattern trench, the fence pattern trench being at a corresponding space between the plurality of bit lines and between the plurality of buried contacts,
a top surface of the word line capping layer is recessed along a bottom surface of the fence pattern trench,
the fence pattern includes a first fence pattern, a second fence pattern, and a third fence pattern stacked sequentially within the fence pattern trench,
the first fence pattern and the third fence pattern include a first material,
the second fence pattern includes a second material having different permittivity from the first material, and
at least one of a length of the first fence pattern, a length of the second fence pattern, and a length of the third fence pattern is
19. (Currently Amended) The semiconductor device of claim 16, wherein:
the first fence pattern is along a lateral surface of the fence pattern trench,
the second fence pattern has a lower surface and a lateral surface surrounded by the first fence pattern,
the third fence pattern is on the first fence pattern and the second fence pattern,
the first fence pattern and the third fence pattern include a first material,
the second fence pattern includes a second material having higher permittivity than the first material,
the first fence pattern and the second fence pattern overlap the first conductive layer and the second conductive layer, and
the third fence pattern overlaps the third conductive layer.
Appropriate corrections are needed.
Claim Rejections - 35 USC § 102
7. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
8. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
9. Claims 1-5, 8, 11-13, 16-17 are rejected under 35 U.S.C. 102(a)(1)/ (a)(2) as being anticipated by Jang et al. (US 2022/0262803 A1).
Regarding independent claim 1, Jang et al. teaches a semiconductor device, comprising (Figs. 1, 23):
a substrate (100, para [0024]) including an active region (active region: ACT, para [0026]) between device separation layers (105, para [0024]);
a word line (112/113, para [0028], [0040]: WL) intersecting and overlapping the active region (ACT);
a word line capping layer (114, para [0040]) covering a top surface of the word line (WL);
a plurality of bit lines (BL, see Fig. 1) interacting and overlapping the active region (ACT) and extending in a different direction (first direction D1 and the second direction D2) from an extension direction of the word line (WL);
a plurality of buried contacts (BC, para [0024]) each connected to the active region (ACT);
a plurality of direct contacts (DC, para [0024]) each connecting the active region (ACT) to a corresponding one of the plurality of bit lines (BL);
a fence pattern (170, para [0024]) on top of the word line capping layer (114); and
a landing pad (LP, para [0024]) connected to a corresponding one of the plurality of buried contacts (BC),
wherein the fence pattern (170) is within a fence pattern trench (TR, para [0060]), the fence pattern trench (TR) being at a corresponding space between the plurality of bit lines (BL) and between the plurality of buried contacts (BC),
a top surface of the word line capping layer (114) is recessed along a bottom surface of the fence pattern trench (TR),
the fence pattern (170, para [0061]) includes a first fence pattern (170S, para [0066]) and a second fence pattern (170F: 170F_1, para [0067]) on the first fence pattern (170S),
the first fence pattern (170S) includes a first material (silicon oxide, para [0079]), and
the second fence pattern (170F: 170F_1) includes a second material (silicon oxynitride, para [0139]) different from the first material (silicon oxide vs silicon oxynitride).
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Regarding claim 2, Jang et al. teaches wherein (Fig. 23):
permittivity of the first material (170S: silicon oxide and its well-known permittivity is 3.9) is different (silicon oxide vs. silicon oxynitride) from permittivity of the second material (170F: silicon oxynitride and its well-known permittivity is 7).
Regarding claim 3, Jang et al. teaches wherein (Fig. 2: A-A cross-section of Fig. 1): each of the plurality of bit lines (BL: 140) includes a first conductive layer (141, para [0047]), a second conductive layer (142, para [0047]), and a third conductive layer (143, para [0047]) sequentially stacked, and
the first fence pattern (Fig. 3: B-B cross-section of Fig. 1: 170S) overlaps at least a portion of each of the first conductive layer (141), the second conductive layer (142), and the third conductive layer (143).
Regarding claim 4, Jang et al. teaches wherein (Figs. 2-3): the permittivity of the first material (170S: silicon oxide and its well-known permittivity is 3.9) is smaller than the permittivity of the second material (170F: silicon oxynitride and its well-known permittivity is 7),
a top surface of the first fence pattern (170S) is at a same level as or at a higher level than a top surface of the third conductive layer (143), and
the second fence pattern (170F) does not overlap the third conductive layer (143).
Regarding claim 5, Jang et al. teaches wherein (Figs. 2-3): the permittivity of the first material (170S: silicon oxide and its well-known permittivity is 3.9) is smaller than the permittivity of the second material (170F: silicon oxynitride and its well-known permittivity is 7),
a top surface of the first fence pattern (170S) is between a top surface of the third conductive layer (143) and a lower surface of the third conductive layer (143), and
the second fence pattern (170F) overlaps the third conductive layer (143).
Regarding claim 8, Jang et al. teaches wherein (Fig. 23): a lower surface of the first fence pattern (170S) includes a curved surface, and
the lower surface of the first fence pattern (170S) is at a lower level than a top surface of the active region (ACT).
Regarding claim 11, Jang et al. teaches wherein (Fig. 23):
the first material (silicon oxide, para [0079]) includes at least one of SiO2, SiBN, SiCN, or a low dielectric constant (low-k) material, and the second material (silicon oxynitride, para [0139]) includes at least one of silicon nitride or silicon nitric oxide.
Regarding independent claim 12, Jang et al. teaches a semiconductor device, comprising (Figs. 1, 23):
a substrate (100, para [0024]) including an active region (ACT: shown in the figure below) between device separation layers (105, para [0024]);
a word line (112/113, para [0040]: WL) intersecting and overlapping the active region (ACT);
a word line capping layer (114, para [0040]) covering a top surface of the word line (WL);
a plurality of bit lines (BL, see Fig. 1) interacting and overlapping the active region (ACT) and extending in a different direction (D1/D4) from an extension direction of the word line (WL);
a plurality of buried contacts (BC, para [0024]) each connected to the active region (ACT);
a plurality of direct contacts (DC, para [0024]) each connecting the active region (ACT) to a corresponding one of the plurality of bit lines (BL);
a fence pattern (170, para [0024]) on top of the word line capping layer (114); and
a landing pad (LP, para [0024]) connected to a corresponding one of the plurality of buried contacts (BC),
wherein the fence pattern (170) is within a fence pattern trench (TR, para [0060]),
the fence pattern trench (TR) being at a corresponding space between the plurality of bit lines (BL) and between the plurality of buried contacts (BC),
a top surface of the word line capping layer (114) is recessed along a bottom surface of the fence pattern trench (TR),
the fence pattern (170) includes a first fence pattern (170S, para [0061]), a second fence pattern (170F_1), and a third fence pattern (170F_2) stacked sequentially within the fence pattern trench (TR),
the first fence pattern (170: 170S) and the third fence pattern (170: 170F_2) include a first material (silicon, para [0139]),
the second fence pattern (170: 170F_1) includes a second material (nitride) having different permittivity from the first material, and
at least one of a length of the first fence pattern (170S: 3rd length), a length of the second fence pattern (170F_1, 2nd length), and a length of the third fence pattern (170F_2, 1st length) is different (shown in the following figure).
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Regarding claim 13, Jang et al. teaches wherein (Fig. 2):
each of the plurality of bit lines (BL, see Fig. 2) includes a first conductive layer (141), a second conductive layer (142), and a third conductive layer (143) sequentially stacked, and
the second fence pattern (170F_1, see Fig. 3) overlaps at least a portion of each of the first conductive layer (141), the second conductive layer (142), and the third conductive layer (143).
Regarding independent claim 16, Jang et al. teaches a semiconductor device, comprising (Figs. 1, 23):
a substrate (100, para [0024]) including an active region (ACT: shown in the following figure) between device separation layers (105, para [0024]);
a word line (112/113: WL, para [0040]) intersecting and overlapping the active region (ACT);
a word line capping layer (114, para [0040]) covering a top surface of the word line (WL);
a plurality of bit lines (BL, see Fig. 1) interacting and overlapping the active region (ACT) and extending in a different direction from an extension direction of the word line (WL);
a plurality of buried contacts (BC, para [0024]) each connected to the active region (ACT);
a plurality of direct contacts (DC, para [0024]) each connecting the active region (ACT) to a corresponding one of the plurality of bit lines (BL);
a fence pattern (170, para [0024]) on top of the word line capping layer (114); and
a landing pad (LP, para [0024]) connected to a corresponding one of the plurality of buried contacts (BC),
wherein the fence pattern (170) is within a fence pattern trench (TR, para [0060]), the fence pattern trench (TR) being at a corresponding space between the plurality of bit lines (BL, see Fig. 1) and between the plurality of buried contacts (BC),
a top surface of the word line capping layer (114) is recessed along a bottom surface of the fence pattern trench (TR),
each of the plurality of bit lines (BL): 140, see Fig. 2) includes a first conductive layer (141), a second conductive layer (142), and a third conductive layer (143) stacked sequentially,
the fence pattern (170) includes a first fence pattern (170S), a second fence pattern (170F_1), and a third fence pattern (170F_2),
at least one of the first fence pattern (170S, silicon oxide), the second fence pattern (170F_1, silicon oxynitride), and the third fence pattern (170F_2, silicon nitride) includes a different material, and
at least one of a width of the first fence pattern (170S), a width of the second fence pattern (170F_1), and a width of the third fence pattern (170F_2) is different (see the annotated figure below).
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Regarding claim 17, Jang et al. teaches wherein (Fig. 23):
the first fence pattern (170S) is along a lateral surface of the fence pattern trench (TR),
the second fence pattern (170F_1) has a lower surface and a lateral surface surrounded by the first fence pattern (170S),
the third fence pattern (170F_2) is on the first fence pattern (170S) and the second fence pattern (170F_1),
the first fence pattern (170: 170S) and the third fence pattern (170: 170F_2) include a first material (oxide, para [0139]),
the second fence pattern (170: 170F_1) includes a second material (nitride) having lower permittivity than the first material, and
the second fence pattern (170F_1) overlaps the first conductive layer (141), the second conductive layer (142), and the third conductive layer (143).
Claim Rejections - 35 USC § 103
10. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
11. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
12. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
13. The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
a. Determining the scope and contents of the prior art.
b. Ascertaining the differences between the prior art and the claims at issue.
c. Resolving the level of ordinary skill in the pertinent art.
d. Considering objective evidence present in the application indicating obviousness or non-obviousness.
14. Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Jang et al. (US 2022/0262803 A1) as applied to claim 1 above.
Regarding claim 9, Jang et al. teaches all of the limitations of claim 1 from which this claim depends.
Jang et al. discloses a certain length (i.e. vertical height according to Fig. 23) ratio (ratio between the vertical length of 170S and the vertical length of 170F_1) of the first fence pattern (170S) and the second fence pattern (170F_1).
However, Jang et al. is explicitly silent of disclosing the length ratio of the first fence pattern (170S) and the second fence pattern (170F_1) is 1:1. It would have been obvious to select intended ‘length ratio of the first fence pattern and the second fence pattern’ so that the length ratio to be within the quoted range, to prevent unwanted particles and optimize the device size. In addition, to an ordinary artisan practicing the invention, absent evidence of disclosure of criticality for the range giving unexpected results, it is not inventive to discover optimal or workable ranges by routine experimentation. In re Aller, 220 F. 2d 454, 105 USPQ 233, 235 (CCPA 1955). Furthermore, the specification contains no disclosure of either the critical nature of the claimed length ratio or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen length ratio or upon another variable recited in a claim, the Applicant must show that the chosen length ratio is critical. See In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ 2d 1934, 1936 (Fed. Cir. 1990).
Regarding claim 10, Jang et al. teaches all of the limitations of claim 9 from which this claim depends.
Jang et al. discloses a certain length (according to Fig. 23) of each of the first fence pattern (170S) and a length of the second fence pattern (170F).
However, Jang et al. is explicitly silent of disclosing each of the length of the first fence pattern (170S) and the length of the second fence pattern (170F) is 400 Å to 600 Å. It would have been obvious to select intended ‘lengths of the first fence pattern and the second fence pattern’ so that the lengths to be within the quoted range, to optimize the device size. In addition, to an ordinary artisan practicing the invention, absent evidence of disclosure of criticality for the range giving unexpected results, it is not inventive to discover optimal or workable ranges by routine experimentation. In re Aller, 220 F. 2d 454, 105 USPQ 233, 235 (CCPA 1955). Furthermore, the specification contains no disclosure of either the critical nature of the claimed lengths or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen lengths or upon another variable recited in a claim, the Applicant must show that the chosen lengths are critical. See In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ 2d 1934, 1936 (Fed. Cir. 1990).
Allowable Subject Matter
15. Claims 6, 7, 14, 15, 18, 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 6 recites ….the permittivity of the first material is greater than the permittivity of the second material,
a top surface of the first fence pattern is at a same level as a lower surface of the third conductive layer or at a lower level than the lower surface of the third conductive layer, and
the second fence pattern overlaps the third conductive layer.
Claim 7 recites ….the permittivity of the first material is greater than the permittivity of the second material,
a top surface of the first fence pattern is between a top surface of the third conductive layer and a lower surface of the third conductive layer, and
the second fence pattern overlaps the third conductive layer.
Claim 14 recites ….the permittivity of the first material is greater than the permittivity of the second material,
the first fence pattern and the third fence pattern do not overlap the first conductive layer, the second conductive layer, and the third conductive layer, and
the second fence pattern overlaps the first conductive layer, the second conductive layer, and the third conductive layer.
Claim 15 recites ….the permittivity of the first material is greater than the permittivity of the second material,
the first fence pattern overlaps the first conductive layer and the second conductive layer,
the second fence pattern overlaps the third conductive layer, and
the third fence pattern does not overlap the first conductive layer, the second conductive layer, and the third conductive layer.
Claim 18 recites ….the first fence pattern is on a bottom surface of the fence pattern trench,
the second fence pattern is along a lateral surface of the fence pattern trench on the first fence pattern,
the third fence pattern is on the first fence pattern, and a lateral surface of the third fence pattern is surrounded by the second fence pattern,
the first fence pattern and the second fence pattern include a first material,
the third fence pattern includes a second material having lower permittivity than the first material, and
the third fence pattern overlaps the third conductive layer.
Claim 19 recites ….the first fence pattern is along a lateral surface of the fence pattern trench,
the second fence pattern has a lower surface and a lateral surface surrounded by the first fence pattern,
the third fence pattern is on the first fence pattern and the second fence pattern,
the first fence pattern and the third fence pattern include a first material,
the second fence pattern includes a second material having higher permittivity than the first material,
the first fence pattern and the second fence pattern overlap the first conductive layer and the second conductive layer, and
the third fence pattern overlaps the third conductive layer.
The prior art, Jang et al. (US 2022/0262803 A1) does not disclose the permittivity of the first material is greater than the permittivity of the second material of the fence pattern. In addition, the prior art also silent about the first fence pattern and the third fence pattern include a first material, the second fence pattern includes a second material having higher permittivity than the first material. Therefore, none of the prior art of references quoted in PTO-892, discloses the limitations of the dependent claims as stated above.
Examiner’s Note
16. Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular paragraphs and/or columns/lines in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. See MPEP 2141.02 VI.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
17. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DIDARUL MAZUMDER whose telephone number is (571)272-8823. The examiner can normally be reached M-F 9-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
18. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DIDARUL A MAZUMDER/Primary Examiner, Art Unit 2812