Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested:
“Silicon Carbide Device With lifetime killer region Under A Drift Region”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 are rejected under 35 U.S.C. 103 as being unpatentable over Utsumi et al. (US 2018/0097069 A1) in view Yoshida et al. (US 2017/0373141 A1).
Regarding independent claim 1: Utsumi teaches (e.g., Fig. 1) a silicon carbide semiconductor device comprising:
a drift layer ([0055]: 2) of a first conductivity-type ([0055]: n-type) provided on a top surface side of a silicon carbide substrate ([0051]: 1) of the first conductivity-type ([0051]: n-type);
a base region ([0052]: 6) of a second conductivity-type ([0052]: a p-type base region 6) provided on a top surface side of the drift layer (2);
a main region of the first conductivity-type ([0052]: 8) provided on the top surface side of the drift layer (2) so as to be in contact with the base region (6);
an insulated gate electrode structure ([0052]: 11/12) provided to be in contact with the main region (8) and the base region (6).
Utsumi does not expressly teach
a lifetime killer region provided to cover a bottom surface of the drift layer.
Yoshida teaches (e.g., Figs. 1A-1B) a silicon carbide semiconductor device comprising a drift layer ([0046]: 1);
Yoshida further teaches a lifetime killer region ([0047]: 32) provided to cover a bottom surface of the drift layer (Fig. 1A; [0046]-[0047]: lifetime killer region 32 is formed on the backside of the drift region, thus it covers the bottom surface of the drift layer 1).
It would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to include in the device of Utsumi, the lifetime killer region provided to cover the bottom surface of the drift layer, as taught by Yoshida, for the benefits of reducing the carriers ejected during FWD reverse recovery operation (Yishida: [0045]).
Regarding claim 2: Utsumi and Yoshida teach the claim limitation of the silicon carbide semiconductor device of claim 1, on which this claim depends,
wherein the lifetime killer region has a recombination center made by a point defect (Yoshida: [0047]).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Utsumi et al. (US 2018/0097069 A1) in view Yoshida et al. (US 2017/0373141 A1) as applied above and further in view of Kinoshita (US 2020/0295129 A1).
Regarding claim 5: Utsumi and Yoshida teach the claim limitation of the silicon carbide semiconductor device of claim 1, on which this claim depends, wherein:
the lifetime killer region is flat from the active region (Yoshida: Fig. 1A, [0047]: the lifetime killer region 32 is flat throughout the whole substrate).
Utsumi as modified by Yoshida does not expressly teach that
a mesa groove is provided in an edge termination region provided at a circumference of an active region provided with the insulated gate electrode structure;
and the lifetime killer region is flat from the active region to the edge termination region.
Kinoshita teaches (e.g., Fig. 2 and reference to Figs. 1-6) a silicon carbide semiconductor device comprising
a mesa groove provided in an edge termination region ([0051] and [0053]: 30) provided at a circumference of an active region ([0032] and [0051]: 20) provided with an insulated gate electrode structure ([0050], [0066] and [0068]: 9/10).
It would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to include in the device of Utsumi as modified by Yoshida, the a mesa groove being provided in an edge termination region provided at a circumference of an active region provided with the insulated gate electrode structure, as taught by Kinoshita, for the benefits of mitigating electric field on a base front surface side of a drift region and that sustains withstand voltage (Kinoshita: [0032]).
Since, the lifetime killer region is disclosed as being flat everywhere throughout the substrate by Utsumi as modified by Yoshida,
it would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to enable the disclosure of Utsumi as modified by Yoshida, and arrive at “the lifetime killer region is flat from the active region to the edge termination region” for the benefits mentioned above.
Allowable Subject Matter
Claims 3-4 and 6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 3: the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features, a silicon carbide semiconductor device comprising:
“wherein a peak position of a concentration of the point defect in a depth direction is located inside the buffer layer”.
Regarding claim 4: the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features, a silicon carbide semiconductor device comprising:
“wherein a peak position of a concentration of the point defect in a depth direction is located inside the silicon carbide substrate under an interface between the silicon carbide substrate and the drift layer”.
Regarding claim 6: the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features, a silicon carbide semiconductor device comprising:
“the lifetime killer region in the edge termination region is provided at a deeper position than the lifetime killer region in the active region”.
Claims 7-15 are allowable.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 7: the most relevant prior art references (e.g., Fig. 1 of US 2018/0097069 A1 to Utsumi et al., Fig. 1A of US 2017/0373141 A1 to Yoshida et al., and Figs. 1-6 of US 2020/0295129 A1 to Kinoshita substantially teach the method of manufacturing a silicon carbide semiconductor device, comprising:
epitaxially growing a drift layer of a first conductivity-type on a top surface side of a silicon carbide substrate of the first conductivity-type;
forming a base region of a second conductivity-type on a top surface side of the drift layer;
forming a main region of the first conductivity-type on the top surface side of the drift layer so as to be in contact with the base region;
forming a gate insulating film so as to be in contact with the base region and the main region;
forming a gate electrode so as to be in contact with the base region and the main region with the gate insulating film interposed: as shown above.
However, none of the prior art references either singly or in proper combination discloses or fairly suggests, along with the other claimed features, a method of manufacturing a silicon carbide semiconductor device comprising:
“forming a lifetime killer region at a depth covering a bottom surface of the drift layer by irradiating the top surface side of the drift layer with a lifetime killer after the epitaxially growing the drift layer and before the forming the gate insulating film”.
Claims 8-15 depend from claim 7, and therefore, are allowable for the same reason as claim 7.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HERVE-LOUIS Y ASSOUMAN whose telephone number is (571)272-2606. The examiner can normally be reached M-F: 08:30 AM-5:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, DAVIENNE MONBLEAU can be reached at 571-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/HERVE-LOUIS Y ASSOUMAN/ Examiner, Art Unit 2812