DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on February 20, 2026 has been entered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 14 and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jeon et al. (U.S. PG Pub 2021/0319747).
Regarding Claim 14, Jeon et al. teaches a display device comprising: a display panel (Figure 1, Element 100. Paragraph 36) comprising:
a display area (Figure 1, Element 110. Paragraph 37) including:
a plurality of pixels (Figure 1, Element P. Paragraph 39), each of the plurality of pixels (Figure 1, Element P. Paragraph 39) comprising:
a light-emitting element (Figure 6, Element OLED. Paragraph 127);
a first transistor (Figure 6, Element T1. Paragraph 114) which controls a driving current (Figure 6, Element ELVDD. Paragraph 115) which flows in the light-emitting element (Figure 6, Element OLED. Paragraph 127);
a second transistor (Figure 6, Element T2. Paragraph 116) which supplies a data voltage (Figure 6, Element Vdata. Paragraph 116) to a first electrode of the first transistor (Figure 6, Element T1. Paragraph 114);
a third transistor (Figure 6, Element T3. Paragraphs 117 - 119) electrically connecting a second electrode (Figure 6, Element N3. Paragraph 114) of the first transistor (Figure 6, Element T1. Paragraph 114) and a gate electrode (Figure 6, Element N1. Paragraph 114) of the first transistor (Figure 6, Element T1. Paragraph 114); and
a fourth transistor (Figure 6, Element T4. Paragraphs 121 - 123) which discharges the gate electrode (Figure 6, Element N1. Paragraph 114) of the first transistor (Figure 6, Element T1. Paragraph 114) with a first initialization voltage (Figure 6, Element Vinit1. Paragraph 130);
a first gate line (Figure 6, Element SLn. Paragraph 120) connected to a gate electrode of the third transistor (Figure 6, Element T3. Paragraphs 117 - 119), the first gate line (Figure 6, Element SLn. Paragraph 120) which receives a first gate signal (Figure 6, Element Sn. Paragraph 120);
a second gate line (Figure 6, Element SLn-1. Paragraph 124) connected to a gate electrode of the fourth transistor (Figure 6, Element T4. Paragraphs 121 - 123), the second gate line (Figure 6, Element SLn-1. Paragraph 124) which receives a second gate signal (Figure 6, Element Sn-1. Paragraph 124);
a first bias voltage line (Figure 6, Element SLn. Paragraph 120) which supplies a first bias voltage (Figure 6, Element Sn. Paragraph 120) to a bias electrode of the third transistor (Figure 6, Element T3. Paragraphs 117 - 119);
a second bias voltage line (Figure 6, Element IVL1. Paragraphs 122 - 123) which supplies a second bias voltage (Figure 6, Element Vinit1. Paragraph 130) different from the first bias voltage (Figure 6, Element Sn. Paragraph 120) to a bias electrode of the fourth transistor (Figure 6, Element T4. Paragraphs 121 - 123), and
a first initialization voltage (Figure 6, Element Vinit1. Paragraph 130) line which supplies an initialization voltage (Figure 6, Element Vinit1. Paragraph 130) to an electrode of the fourth transistor (Figure 6, Element T4. Paragraphs 121 - 123); and
a non-display area (Figure 1, Element not labeled, but is the remainder of Element 100 that is outside Element 110. Paragraph 37) surrounding the display area (Figure 1, Element 110. Paragraph 37).
Regarding Claim 16, Jeon et al. teaches the display device of claim 14 (See Above), wherein the first bias voltage (Figure 6, Element Sn. Paragraph 120) line (Figure 6, Element SLn. Paragraph 120) is electrically insulated from a gate electrode of the third transistor (Figure 6, Element T3. Paragraphs 117 - 119), and the second bias voltage (Figure 6, Element Vinit1. Paragraph 130) line (Figure 6, Element IVL1. Paragraphs 122 - 123) is electrically insulated from a gate electrode of the fourth transistor (Figure 6, Element T4. Paragraphs 121 - 123).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Jeon et al. (U.S. PG Pub 2021/0319747) in view of Kwon et al. (U.S. PG Pub 2019/0059156).
Regarding Claim 15, Jeon et al. teaches the display device of claim 14 (See Above). Jeon et al. is silent with regards to further comprising a circuit board which supplies voltages and signals to the display panel, wherein the display panel further comprises a display pad unit connected to the circuit board, and wherein the non-display area comprises a bias lead line electrically connecting the first bias voltage line or the second bias voltage line to the display pad unit.
Kwon et al. teach further comprising a circuit board (Figures 1 and 2, Element 120. Paragraph 23) which supplies voltages and signals to the display panel (Figures 1 and 2, Element 110. Paragraph 23), wherein the display panel (Figures 1 and 2, Element 110. Paragraph 23) further comprises a display pad unit (Figure 1, Element MA. Paragraph 26) connected to the circuit board (Figures 1 and 2, Element 120. Paragraph 23), and wherein the non-display area (Figure 1, Element BA. Paragraph 26) comprises a bias lead line electrically connecting the first bias voltage line (Paragraph 55) or the second bias voltage line to the display pad unit (Figure 1, Element MA. Paragraph 26).
It would have been obvious to a person of ordinary skill in the art to modify the teachings of the display device of Jeon et al. with the non-display panel of Kwon et al. The motivation to modify the teachings of Jeon et al. with the teachings of Kwon et al. is to provide a display device capable of minimizing short circuits between pads, as taught by Kwon et al. (Paragraph 5).
Allowable Subject Matter
Claim 1 – 12 and 17 – 20 are allowed.
The following is an examiner’s statement of reasons for allowance: The prior art of record fails to teach at least “wherein the semiconductor area of the fourth transistor in the first pixel and the semiconductor area of the fourth transistor in the second pixel are symmetrical with respect to semiconductor area of the fourth-first transistor” in combination with the limitations of Claim 1. Claims 2 – 13 and 22 – 23 inherit these reasons for allowance.
The following is an examiner’s statement of reasons for allowance: The prior art of record fails to teach at least “a first initialization voltage line which supplies a first initialization voltage to the plurality of pixels; a second initialization voltage line which supplies a second initialization voltage different from the first initialization voltage to the plurality of pixels;…wherein the fourth transistor discharges the gate electrode of the first transistor with the first initialization voltage;…the seventh transistor electrically connects the first electrode of the light emitting element and the second initialization voltage line, wherein the first and second initialization voltage lines are disposed between immediately neighboring rows of some of the plurality of rows and are not disposed between immediately neighboring rows of some others of the plurality of rows in a manner that pixels arranged in a same column and respectively disposed in the immediately neighboring rows of the some others of the plurality of rows among the plurality of pixels directly face each other” of Claim 17 in combination with the other limitations of Claim 17. Claims 18 – 20 inherit these reasons for allowance.
The examiner notes that the applicant’s explanation of the above limitation is accepted. The applicant has disclosed (See Remarks (July 31, 2025), Page 25 of 27):
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Given the applicant’s interpretation of the limitation “are not disposed between immediately neighboring rows of some others of the plurality of rows in a manner that pixels arranged in a same column and respectively disposed in the immediately neighboring rows of the some others of the plurality of rows among the plurality of pixels directly face each other” is being interpreted as the pixels in immediately neighboring rows are disposed without the insertion of any other lines and/or components.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
All other arguments are considered moot in light of the new grounds of rejection presented above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Kim et al. (U.S. PG Pub 2021/0125543) teach a pixel circuit and driving timings similar to the instant invention.
Shi et al. (U.S. PG Pub 2022/0328603) and Liu et al. (U.S. PG Pub 2023/0317011) teach a pixel circuit similar to the instant pixel circuit.
Ebisuno et al. (U.S. PG Pub 2018/0040682) teach a pixel circuit with fourth electrode connections for some of the transistors in the pixel circuit, similar to the instant invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDREW B SCHNIREL whose telephone number is (571)270-7690. The examiner can normally be reached Monday - Friday, 10 - 6 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Boddie can be reached at 571-272-0666. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/A.B.S/Examiner, Art Unit 2625
/WILLIAM BODDIE/Supervisory Patent Examiner, Art Unit 2625