DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Group I, claims 1-19 in the reply filed on 6/1/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claim 20 has been withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 6/1/2026.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 13-14 and 15-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 13 recites the limitations "the step of separating" and "the portion" in line 2. Claim 14 recites the limitation "the step of forming flash memory" in line 1. Claim 15 recites the limitation "the plurality of stress defects" in line 5. There is insufficient antecedent basis for these limitations in the claims.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 7 and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Baer, US 2009/0056513 .
Regarding claim 1, Baer discloses; a method of processing a semiconductor wafer comprising semiconductor dies, the semiconductor wafer having an active surface and a { 111 } crystalline plane orientation parallel to the active surface, the method comprising: forming one or more stress defects (Fig. 1-8 and [0042]; maximal stress along cleavage plane at dotted line 3) at a depth of the wafer corresponding to a final thickness of the wafer; and cleaving the wafer in a { 111 } plane (Fig. 1-8 and [0036]; (111) plane is the cleavage plane at dotted line 3) of the one or more stress defects by crack propagation from the one or more stress defects (Fig. 1-8 and [0042]; maximal stress along cleavage plane at dotted line 3).
Regarding claim 7, Baer discloses; the step of forming one or more stress defects comprises the step of forming a plurality of stress defects in the { 111 } plane (Fig. 1-8 and [0036]; (111) plane is the cleavage plane at dotted line 3).
Regarding claim 15, Baer discloses; a method of processing a semiconductor wafer comprising semiconductor dies, the semiconductor wafer having an active surface the method comprising: forming a plurality of stress points in a plane having a { 111 } crystalline orientation (Fig. 1-8 and [0036]; (111) plane is the cleavage plane at dotted line 3) at a depth of the wafer corresponding to a final thickness of the wafer; and cleaving the wafer in the { 111 } plane of the plurality of stress defects by crack propagation between the plurality of stress defects (Fig. 1-8 and [0042]; maximal stress along cleavage plane at dotted line 3).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2-5, 8-12 and 14-18 are rejected under 35 U.S.C. 103 as being unpatentable over Wu, US 2023/0411169, in view of Baer, US 2009/0056513.
Regarding claim 1, Wu discloses; a method of processing a semiconductor wafer comprising semiconductor dies, the semiconductor wafer having an active surface and a { 111 } crystalline plane orientation parallel to the active surface, the method comprising: forming one or more stress defects (Fig. 1-11 and [0031, 0042]; stealth lasing generate localized pinpoint hole 150 at x-y plane 156) at a depth of the wafer corresponding to a final thickness of the wafer; and cleaving the wafer in a plane of the one or more stress defects by crack propagation from the one or more stress defects (Fig. 1-11 and [0042]; cracks will naturally propagate between the holes in the [1,1,0] crystalline plane, thus effectively severing a first portion 100a from a second portion 100b at an x-y plane 156). Wu substantially discloses the invention including the step of thinning a semiconductor wafer by a horizontal stealth lasing process at [1,1,0] crystalline plane but is silent about { 111 } plane. However, Baer teaches that (111) plane is the cleavage plane at dotted line 3 (Fig. 1-8 and [0036]). It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify Wu by cleaving at { 111 } plane instead of [1,1,0] crystalline plane so that to provide a silicon wafer production method that involves no wasted silicon due to saw kerf and produces wafers that are intrinsically smooth enough to require little or no additional polishing. ([0008-0009]).
Regarding claim 2, Wu discloses; the step of forming one or more stress defects comprises the step of forming the one or more stress defects by a laser forming the stress defects within an interior of the wafer by stealth lasing (Fig. 1-11 and [0031, 0042]; stealth lasing generates localized pinpoint hole 150 at x-y plane 156).
Regarding claim 3, Wu discloses; the step of forming one or more stress defects by a laser forming the stress defects within an interior of the wafer by stealth lasing comprises the step of penetrating the wafer with a laser through a major planar surface of the wafer (Fig. 1-11 and [0048]; horizontal stealth lasing step 212 and/or the vertical stealth lasing step 214).
Regarding claim 4, Wu discloses; the step of forming one or more stress defects by a laser forming the stress defects within an interior of the wafer by stealth lasing comprises the step of penetrating the wafer with a laser through an outer circumference of the of the wafer (Fig. 1-11 and [0048]; horizontal stealth lasing step 212).
Regarding claim 5, Wu discloses; the step of forming one or more stress defects comprises the step of forming the one or more stress defects by a laser forming the stress defects around an outer circumference of the wafer (Fig. 1-11 and [0048]; horizontal stealth lasing step 212).
Regarding claim 8, Wu discloses; the step of forming one or more stress defects comprises the step of forming the stress defects at one or more discrete points (Fig. 1-11 and [0031, 0042]; stealth lasing generates localized pinpoint hole 150 at x-y plane 156).
Regarding claim 9, Wu discloses; the step of forming one or more stress defects comprises the step of forming the stress defects at a plurality of discrete points (Fig. 1-11 and [0031, 0042]; stealth lasing generates localized pinpoint hole 150 at x-y plane 156).
Regarding claim 10, Wu discloses; the step of forming one or more stress defects comprises the step of forming the stress defects in a continuous line (Fig. 1-11 and [0031, 0042]; stealth lasing generates localized pinpoint hole 150 at x-y plane 156 at r1,r2 and r3).
Regarding claim 11, Wu discloses; the step of forming one or more stress defects comprises the step of forming the stress defects in a curved pattern (Fig. 1-11 and [0031, 0042]; stealth lasing generates localized pinpoint hole 150 at x-y plane 156 at curved r1,r2 and r3).
Regarding claim 12, Wu discloses; the step of forming one or more stress defects comprises the step of forming the stress defects in a straight line (Fig. 1-11 and [0041]; the localized pinpoint holes 150 formed in rows along straight lines through the wafer).
Regarding claim 14, Wu discloses; the step of forming flash memory integrated circuits in the active surface of the wafer (Fig. 1-11 and [0025]; the semiconductor dies 106 for example be flash memory dies such as 2D NAND flash memory or 3D flash memory).
Regarding claim 15, Wu discloses; a method of processing a semiconductor wafer comprising semiconductor dies, the semiconductor wafer having an active surface the method comprising: forming a plurality of stress points (Fig. 1-11 and [0031, 0042]; stealth lasing generate localized pinpoint hole 150 at x-y plane 156) in a plane having crystalline orientation at a depth of the wafer corresponding to a final thickness of the wafer; and cleaving the wafer in the plane of the plurality of stress defects by crack propagation between the plurality of stress defects (Fig. 1-11 and [0042]; cracks will naturally propagate between the holes in the [1,1,0] crystalline plane, thus effectively severing a first portion 100a from a second portion 100b at an x-y plane 156). Wu substantially discloses the invention including the step of thinning a semiconductor wafer by a horizontal stealth lasing process at [1,1,0] crystalline plane but is silent about { 111 } plane. However, Baer teaches that (111) plane is the cleavage plane at dotted line 3 (Fig. 1-8 and [0036]). It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify Wu by cleaving at { 111 } plane instead of [1,1,0] crystalline plane so that to provide a silicon wafer production method that involves no wasted silicon due to saw kerf and produces wafers that are intrinsically smooth enough to require little or no additional polishing ([0008-0009]).
Regarding claim 16, Wu discloses; the step of engaging a major planar surface of the wafer, opposite the active surface of the wafer, with a vacuum tip to remove a portion of the wafer after said step of cleaving the wafer (Fig. 1-11 and [0043]; removal of the portion 110b of wafer 100 by a vacuum chuck 158 after the stealth horizontal lasing process of step 212).
Regarding claim 17, Wu discloses; the step of forming one or more stress defects comprises the step of forming the one or more stress defects by a laser forming the stress defects within an interior of the wafer by stealth lasing (Fig. 1-11 and [0031, 0042]; stealth lasing generates localized pinpoint hole 150 at x-y plane 156).
Regarding claim 18, Wu discloses; the step of forming one or more stress defects comprises the step of forming the one or more stress defects by a laser forming the stress defects around an outer circumference of the wafer (Fig. 1-11 and [0048]; horizontal stealth lasing step 212).
Claim(s) 6 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Wu, US 2023/0411169, in view of Baer, US 2009/0056513 as applied to claims 1, 2-5, 8-12 and 14-18 above, and further in view of NOMARU, US 2021/0316476.
Regarding claims 6 and 19, Wu substantially discloses the invention including the step of thinning a semiconductor wafer by a horizontal stealth lasing process at [1,1,0] crystalline plane but is silent about the step of forming the one or more stress defects by a saw blade forming the stress defects around an outer circumference of the wafer. However, NOMARU teaches that modified layer 100 is engraved by use of a cutting unit 40 includes a cutting blade 42 from the side surface 20c of the ingot 20, to cause a crack extending from the modified layer 100 to the inside to grow (Fig. 3 and [0039]). It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify Wu in view of Baer by forming the one or more stress defects by a saw blade forming the stress defects around an outer circumference of the wafer so that to provide a wafer forming method by which wafers can be efficiently formed from a semiconductor ingot and the amount of the semiconductor ingot to be thrown away can be reduced ([0008]).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Baer, US 2009/0056513 as applied to claims 1, 7 and 15 above, and further in view of Wu, US 2023/0411169.
Regarding claim 13, Baer substantially discloses the invention including allows the fracture to propagate across the desired cleavage plane, thereby completely severing the wafer from the rest of the ingot but is silent about the portion of the wafer including the active surface has a thickness of between 25 microns and 36 microns. However, Wu teaches that the semiconductor die has a thickness between the first and second major surfaces of between 25 microns and 36 microns (Claim 7). It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify Baer by separating the portion of the wafer including the active surface has a thickness of between 25 microns and 36 microns so that In order to maximize storage capacity for a given form factor storage device, semiconductor dies, and the wafers from which they are made, are being fabricated to ever-decreasing thicknesses ([0002]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AZM PARVEZ whose telephone number is (571)272-1447. The examiner can normally be reached M-F 9-6 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, DREW RICHARDS can be reached at (571)272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/AZM PARVEZ/
Examiner
Art Unit 2892
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892
Prosecution Insights