Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
Applicant’s election of Invention I, claims 1-10 in the reply filed on 12/29/25 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)). Claims 11-20 are withdrawn from further consideration by the examiner. The requirement is still deemed proper and is therefore made FINAL.
Information Disclosure Statement
The information disclosure statements filed 1/24/25 have been considered.
Oath/Declaration
Oath/Declaration filed on 11/30/23 has been considered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-6, 8-9 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Ong et al. (U.S. Patent Publication No. 2023/0209798).
Referring to figures 4-10, Ong et al. teaches a gate all around (GAA) field effect transistor (GAA FET) (130), comprising: a substrate (101); a nanosheet structure (260) on the substrate; a source/drain (SD) region (275) in the substrate and coupled to a first end of the nanosheet structure; a drain/source (DS) region (275) in the substrate and coupled to a second end opposite the first end of the nanosheet structure; a metal gate (285) on the nanosheet structure to define a plurality of channels between the source/drain region and the drain/source region; and a trench oxide (605) blocking a bottom channel of the plurality of channels (see figure 7).
Regarding to claim 2, the metal gate (285) horizontally surrounds the nanosheet structure (260) on four sides (see figures 4-7).
Regarding to claim 3, in which the trench oxide (301/605) is coupled to a portion of the metal gate (285, see figure 7).
Regarding to claim 4, the trench oxide (301/605) extends through the substrate (101, see figure (7a)3.
Regarding to claim 5, the trench oxide comprises silicon nitride (SiN) (see paragraph# 68).
Regarding to claim 6, the trench oxide comprises silicon oxide (SiO2) (see paragraph# 68).
Regarding to claim 8, the nanosheet structure comprises silicon (see paragraph# 48).
Regarding to claim 9, gate spacers (411) between the metal gate (285) and the SD region and the DS region (275, see figure 7a).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ong et al. (U.S. Patent Publication No. 2023/0209798) applied in claim(s) 1-6, 8-9 above in view of Huang et al. (U.S. Patent Publication No. 2022/0045052).
Referring to figures 4-10, Ong et al. teaches a gate all around (GAA) field effect transistor (GAA FET) (130), comprising: a substrate (101); a nanosheet structure (260) on the substrate; a source/drain (SD) region (275) in the substrate and coupled to a first end of the nanosheet structure; a drain/source (DS) region (275) in the substrate and coupled to a second end opposite the first end of the nanosheet structure; a metal gate (285) on the nanosheet structure to define a plurality of channels between the source/drain region and the drain/source region; and a trench oxide (605) blocking a bottom channel of the plurality of channels (see figure 7).
However, the reference does not clearly teach a backside power rail coupled to the substrate (in claim 7).
Huang et al. teaches a semiconductor device having a backside power rail (130) coupled to the substrate (102, see figure, paragraph# 29).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to form a backside power rail coupled to the substrate in Ong et al. as taught by Huang et al. because it is known in the semiconductor to to deliver power
Claim 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ong et al. (U.S. Patent Publication No. 2023/0209798) applied in claim(s) 1-6, 8-9 above in view of Chen et al. (U.S. Patent Publication No. 2023/0282751).
Referring to figures 4-10, Ong et al. teaches a gate all around (GAA) field effect transistor (GAA FET) (130), comprising: a substrate (101); a nanosheet structure (260) on the substrate; a source/drain (SD) region (275) in the substrate and coupled to a first end of the nanosheet structure; a drain/source (DS) region (275) in the substrate and coupled to a second end opposite the first end of the nanosheet structure; a metal gate (285) on the nanosheet structure to define a plurality of channels between the source/drain region and the drain/source region; and a trench oxide (605) blocking a bottom channel of the plurality of channels (see figure 7).
However, the reference does not clearly teach the SD region and the DS region comprise boron-doped silicon germanium (SiGe:B) for P-type FET (PFET) devices, and phosphorus doped silicon (Si:P) for N-type FET (NFET) devices (in claim 10).
Chen et al. teaches the SD region and the DS region (250/252) comprise boron-doped silicon germanium (SiGe:B) for P-type FET (PFET) devices, and phosphorus doped silicon (Si:P) for N-type FET (NFET) devices (see paragraph# 54, figures 13-14).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to form the SD region and the DS region comprise boron-doped silicon germanium (SiGe:B) for P-type FET (PFET) devices, and phosphorus doped silicon (Si:P) for N-type FET (NFET) devices in Ong et al. as taught by Chen et al. because choosing an optimum material for a layer is known in the semiconductor art to form a device with desired conductivity.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thanh Nguyen whose telephone number is (571) 272-1695, or by Email via address Thanh.Nguyen@uspto.gov. The examiner can normally be reached on Monday-Thursday from 6:00AM to 3:30PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Yara Green, can be reached on (571) 270-3035. The fax phone number for this Group is (571) 273-8300.
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/THANH T NGUYEN/Primary Examiner, Art Unit 2893
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