Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-7, 20-22 and 24 are rejected under 35 U.S.C 103 as being unpatentable over Fujita et al. (US 2019/0084080 A1) in view of Hiraiwa et al. (US 2012/0261678 A1).
Regarding independent claim 1: Fuji teaches (e.g., Figs. 2-4; [0005]-[0008]) a method of manufacturing a semiconductor chip ([0011]-[0044]), comprising:
forming first modified regions ([0038]-[0039]: LM2) in a semiconductor substrate ([0019]-[0020]: 10 with surfaces F1 and F2) along a first direction (horizontal direction) at a first depth ([0022]: depth of modified crystal LM2 closer to surface F1);
forming second modified regions ([0037]-[0039]: LM1) in the semiconductor substrate along a second direction (longitudinal direction) different from the first direction at a second depth ([0019]-[0022]: LM1 is located at a different depth closer to surface F2) different from the first depth (Fig. 2; [0019]-[0022]: traces from the process); and
dicing the semiconductor substrate into semiconductor chips using the first and second modified regions ([0024]-[0025], [0029], [0034]-[0037] and [0040]-[0043]),
the semiconductor substrate has a first surface (bottom surface, F1) and a second surface (top surface, F2) that are opposite to each other;
wherein the first modified regions ([0038]-[0039]: LM2) are located closer to the first surface (bottom surface, F1) than the second modified regions ([0037]-[0039]: LM1).
Fuji does not expressly teach that no modified region is located between the first surface and the second modified regions.
Hiraiwa teaches (e.g., Fig. 1) a method of manufacturing a semiconductor chip comprising a second modified regions ([0049]-[0050]: 52), a first surface ([0042] and [0047]: bottom surface 11b);
Hiraiwa further teaches that no modified region is located between the first surface ([0042] and [0047]: bottom surface 11b) and the second modified regions ([0049]-[0050]: 52).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the method of Fuji, the method
wherein there is no modified region located between the first surface and the second modified regions,
as taught by Hiraiwa, for the benefits of reducing the amount of energy applied during the dicing process and better controlling the etched regions.
Regarding claim 3: Fujita teaches the claim limitation of the method of claim 2, on which this claim depends,
wherein the semiconductor substrate includes:
a semiconductor base ([0040]-[0043]: substrate 10 provides a semiconductor base including LM2/LC1/LM1/LC2) providing the second surface (upper surface); and
an active layer ([0016] and [0034]-[0035]: 15) formed on the semiconductor base, the active layer ([0016] and [0034]-[0035]: 15) provides the first surface (F1).
Regarding claim 4: Fujita teaches the claim limitation of the method of claim 1, on which this claim depends,
wherein the first modified regions (LM2) and the second modified regions (LM1) include crystal structures different from crystal structures of the semiconductor substrate (Fig. 4; [0020]-[0024], [0037] and [0039]-[0040]: modified portions 122 and 121 include crystal structures different semiconductor substrate 10; [0023]-[0024] and [0038]).
Regarding claim 5: Fujita teaches the claim limitation of the method of claim 1, on which this claim depends,
Although Fujita does not expressly teach that dicing the semiconductor substrate includes:
growing cracks accompanying the first modified regions and the second modified regions to reach opposite surfaces of the semiconductor substrate; and
expanding the semiconductor substrate so that the semiconductor chips are separated from the semiconductor substrate by the cracks.
Fujita teaches using the first modified regions ([0039]:122) and the second modified regions ([0039]: 121) to reach opposite surfaces of the semiconductor substrate (10); and
expanding the semiconductor substrate so that the semiconductor chips are separated from the semiconductor substrate by both modified regions ([0030], [0040]-[0041] and [0043]: the cleavage faces LC1 and LC2 are used as the crack expanding the semiconductor substrate so that the semiconductor chips are separated from the semiconductor substrate by the cleavage faces).
Therefore, it would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to enable the teachings of Fujita and arrive at : “dicing the semiconductor substrate includes: growing cracks accompanying the first modified regions and the second modified regions to reach opposite surfaces of the semiconductor substrate; and expanding the semiconductor substrate so that the semiconductor chips are separated from the semiconductor substrate by the cracks” because using the cleavage faces necessarily creates cracks, even if the term cracks, has not been used expressly, the cleavage surfaces created by the modified regions, are used to guide the dicing process, so as to control the dicing process, while using the modified regions as gettering sites, thus reduce undesired impurities in the device layer.
Regarding claim 6: Fujita teaches the claim limitation of the method of claim 1, on which this claim depends,
wherein the first modified regions ([0020]-[0023]: LM1;LM2) are formed by irradiating laser light in the semiconductor substrate from the surface of the semiconductor substrate, and modifying portions of the semiconductor substrate where the laser light is focused, by the laser light ([0020]-[0024] and [0038]-[0039]).
Regarding claim 7: Fujita teaches the claim limitation of the method of claim 1, on which this claim depends,
wherein each of the semiconductor chips ([0020]-[0024]) is separated from the semiconductor substrate ([0020]-[0024]: 10) to include a first side surface on which the first modified regions are located ([0022]-[0025]: FS) and a second side surface (Fig. 2; [0022]-[0025]: there are at least four side surface; adjacent FS considered the second side surface) on which the second modified regions are located ([0020]-[0025]).
Regarding independent claim 20: Fuji teaches (e.g., Figs. 2-4; [0005]-[0008]) a semiconductor chip comprising:
a semiconductor substrate ([0019]-[0020]: 10 with surfaces F1 and F2), the semiconductor substrate including:
a first surface and a second surface ([0019]-[0020]: 10 with bottom surface F1 and upper surface F2 respectively) that are opposite to each other;
a first side surface and a second side surface ([0019]-[0020]: front side surface and lateral side surface) that extend from the first surface to the second surface (from the bottom surface to the upper surface of the substrate, respectively);
first modified regions ([0038]-[0039]: LM2) located on the first side surface (bottom side surface substrate of the front side surface) at a first distance from the first surface (F1); and
second modified regions ([0037]-[0039]: LM1) located on the second side surface (lateral side surface on the upper side of the substrate) at a second distance from the first surface (bottom side surface of the bottom side of the substrate) different from the first distance from the first surface (Fig. 2 and F4; show that the second distance from the first surface is different from the first distance from the first surface).
Fuji does not expressly teach that no modified region is located between the first surface and the second modified regions.
Hiraiwa teaches (e.g., Fig. 1) a method of manufacturing a semiconductor chip comprising a second modified regions ([0049]-[0050]: 52) and a first surface ([0042] and [0047]: bottom surface 11b);
Hiraiwa further teaches that no modified region is located between the first surface ([0042] and [0047]: bottom surface 11b) and the second modified regions ([0049]-[0050]: 52).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the method of Fuji, the method
wherein there is no modified region located between the first surface and the second modified regions,
as taught by Hiraiwa, for the benefits of reducing the amount of energy applied during the dicing process and better controlling the etched regions.
Regarding claim 21: Fujita teaches the claim limitation of the semiconductor chip of claim 20, on which this claim depends,
wherein the semiconductor substrate further includes:
a semiconductor base ([0040]-[0043]: substrate 10 provides a semiconductor base including LM2/LC1/LM1/LC2) providing the second surface (upper surface); and
an active layer ([0016] and [0034]-[0035]: 15) formed on the semiconductor base, the active layer providing the first surface (bottom surface).
Regarding claim 22: Fujita teaches the claim limitation of the semiconductor chip of claim 20, on which this claim depends,
wherein the first modified regions (LM2) and the second modified regions (LM1) have crystal structures different from a crystal structure of the semiconductor substrate (Fig. 4; [0020]-[0024], [0037] and [0039]-[0040]: modified portions 122 and 121 include crystal structures different semiconductor substrate 10; [0023]-[0024] and [0038]).
Regarding claim 24: Fujita teaches the claim limitation of the semiconductor chip of claim 20, on which this claim depends,
wherein the first side surface and the second side surface (Fig. 2; front side surface and the lateral side surface respectively) are side surfaces crossing each other (Fig. 2; front side and lateral side surfaces cross each other).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Abe et al. (US 2009/0121337 A1) in view of Hiraiwa et al. (US 2012/0261678 A1).
Regarding independent claim 19: Abe teaches (e.g., Figs. 1-9 and 12-25) a method of manufacturing a semiconductor package, comprising:
disposing a semiconductor chip ([0155]: 1C) over a package substrate ([0155]: 15); and
forming a molding layer ([0157]: 18) covering the semiconductor chip, wherein the semiconductor chip includes:
a first surface (bottom surface) and a second surface (upper surface) that are opposite to each other;
a first side surface and a second side surface (left-side and right side of semiconductor chip 1C) that extend from the first surface to the second surface (from bottom side to upper side);
first modified regions ([0143]-[0144] and [0148]: left side portion of semiconductor chip 1C) located on the first side surface at a first distance from the first surface (Figs. 14-18; [0143]-[0144] and [0148]); and
second modified regions ([0143]-[0144] and [0148]: right side portion of semiconductor chip 1C) located on the second side surface at a second distance from the first surface different from the first distance from the first surface ([0143]-[0144] and [0148]), Applicant is reminded that a "product" claim is directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Wertheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); In re Fitzgerald, 205 USPQ 594, 596 (CCPA); In re Marosi et al., 218 USPQ 289 (CAFC); and most recently, In re Thorpe et al., 227 USPQ 964 (CAFC, 1985) all of which make it clear that it is the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that, as here, an old or obvious product produced by a new method is not patentable as a product, whether claimed in "product by process" claims or not. MPEP § 2113; and
wherein the molding layer (18) is formed by providing a molding material ([0157]: molding material of epoxy resin is provided) on the package substrate to flow toward the second side surface of the semiconductor chip (Fig. 25; [0157]: the molding material 18 is provided to inherently flow on both sides of the semiconductor chip 1C due to the flowable nature of the epoxy resin),
wherein the first modified regions ([0038]-[0039]: LM2) are located closer to the first surface (bottom surface, F1) than the second modified regions ([0037]-[0039]: LM1).
Abe does not expressly teach that no modified region is located between the first surface and the second modified regions.
Hiraiwa teaches (e.g., Fig. 1) a method of manufacturing a semiconductor chip comprising a second modified regions ([0049]-[0050]: 52), a first surface ([0042] and [0047]: bottom surface 11b);
Hiraiwa further teaches that no modified region is located between the first surface ([0042] and [0047]: bottom surface 11b) and the second modified regions ([0049]-[0050]: 52).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the method of Fuji, the method
wherein there is no modified region located between the first surface and the second modified regions,
as taught by Hiraiwa, for the benefits of reducing the amount of energy applied during the dicing process and better controlling the etched regions.
Claims 8 and 10-15 are rejected under 35 U.S.C. 103 as being unpatentable over Fujita et al. (US 2019/0084080 A1) in view of Kim et al. (US 2015/0382443 A1) and Hiraiwa et al. (US 2012/0261678 A1).
Regarding independent claim 8: Fuji teaches (e.g., Figs. 2-4; [0005]-[0008]) a method of manufacturing a semiconductor chip ([0011]-[0044]), a method of manufacturing a semiconductor package, comprising:
forming first modified regions ([0019]-[0022]: LM2) in a semiconductor substrate ([0019]-[0020]: 10 with surfaces F1 and F2) along a first direction (horizontal direction) at a first depth ([0022]: depth of modified crystal LM2 closer to surface F1);
forming second modified regions ([0019]-[0022]: LM1) in the semiconductor substrate along a second direction (longitudinal direction) different from the first direction at a second depth ([0019]-[0022]: LM1 is located at a different depth closer to surface F2) different from the first depth;
dicing the semiconductor substrate (10) into semiconductor chips ([0035]: 1) using the first and second modified regions ([0030] and [0040]-[0041] and [0043]), each of the semiconductor chips including a first side surface diced along the first direction (Fig. 2; [0019]-[0022]: LM2 in horizontal direction of FS) and a second side surface diced along the second direction (Fig. 2; [0019]-[0022]: lateral direction of FS);
the semiconductor substrate has a first surface (bottom surface, F1) and a second surface (top surface, F2) that are opposite to each other,
wherein the first modified regions ([0038]-[0039]: LM2) are located closer to the first surface (bottom surface, F1) than the second modified regions ([0037]-[0039]: LM1).
Fujita does not expressly teach
mounting a semiconductor chip of the semiconductor chips over a package substrate; and
forming a molding layer covering the semiconductor chip by providing a molding material over the package substrate to flow toward the second side surface of the semiconductor chip;
wherein there is no modified region located between the first surface and the second modified regions.
Kim teaches (e.g., Figs. 2A-3B) a method comprising
mounting a semiconductor chip ([0079]: 200) of a semiconductor chips over a package substrate ([0079]: 100); and
forming a molding layer ([0080]: 300) covering the semiconductor chip (200) by providing a molding material ([0080]: epoxy base molding compound material 300) over the package substrate (100) to flow toward the second side surface of the semiconductor chip (Fig. 3B; [0080]: towards the right side of the semiconductor chip, as indicated by the arrows).
Therefore, it would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to include in the method of Fujita, the method comprising mounting a semiconductor chip of the semiconductor chips over a package substrate; and forming a molding layer covering the semiconductor chip by providing a molding material over the package substrate to flow toward the second side surface of the semiconductor chip, as taught by Kim, for the benefits of improving the molding material fills and avoid void, thus improving device protection from the external environments.
Fuji does not expressly teach that no modified region is located between the first surface and the second modified regions.
Hiraiwa teaches (e.g., Fig. 1) a method of manufacturing a semiconductor chip comprising a second modified regions ([0049]-[0050]: 52) and a first surface ([0042] and [0047]: bottom surface 11b);
Hiraiwa further teaches that no modified region is located between the first surface ([0042] and [0047]: bottom surface 11b) and the second modified regions ([0049]-[0050]: 52).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the method of Fuji, the method
wherein there is no modified region located between the first surface and the second modified regions, as taught by Hiraiwa, for the benefits of reducing the amount of energy applied during the dicing process and better controlling the etch regions.
Regarding claim 10: Fujita and Kim teach the claim limitation of the method of claim 9, on which this claim depends,
Fujita as modified by Kim teaches wherein the semiconductor chip (Kim: 1C) is disposed over the package substrate (Kim: 15) such that the first surface faces the package substrate (Kim: bottom surface faces the package substrate 15).
Regarding claim 11: Fujita and Kim teach the claim limitation of the method of claim 9, on which this claim depends,
wherein the semiconductor substrate includes:
a semiconductor base (Fujita: [0040]-[0043]: bottom portion of substrate 10 having width W3) providing the second surface (Fujita: upper surface); and
an active layer (Fujita: [0016] and [0034]-[0035]: layer including device 15) formed on the semiconductor base, the active layer provides the first surface (Fujita: [0016] and [0034]-[0035]: the active 15 provides the bottom surface).
Regarding claim 12: Fujita and Kim teach the claim limitation of the method of claim 8, on which this claim depends,
wherein the first modified regions (Fujita: [0020]-[0022]: LM2) and the second modified regions (Fujita: [0020]-[0022]: LM1) include crystal structures different from a crystal structure of the semiconductor substrate (Fujita: [0020]-[0023] and [0037]).
Regarding claim 13: Fujita and Kim teach the claim limitation of the method of claim 8, on which this claim depends,
Although Fujita as modified by Kim does not expressly teach that dicing the semiconductor substrate includes:
growing cracks accompanying the first modified regions and the second modified regions to reach opposite surfaces of the semiconductor substrate; and
expanding the semiconductor substrate so that the semiconductor chips are separated from the semiconductor substrate by the cracks.
Although Fujita as modified by Kim does not expressly teach that dicing the semiconductor substrate includes:
growing cracks accompanying the first modified regions and the second modified regions to reach opposite surfaces of the semiconductor substrate; and
expanding the semiconductor substrate so that the semiconductor chips are separated from the semiconductor substrate by the cracks.
Fujita teaches using the first modified regions ([0039]:122) and the second modified regions ([0039]: 121) to reach opposite surfaces of the semiconductor substrate (10); and
expanding the semiconductor substrate so that the semiconductor chips are separated from the semiconductor substrate by both modified regions ([0030], [0040]-[0041] and [0043]: the cleavage faces LC1 and LC2 are used as the crack expanding the semiconductor substrate so that the semiconductor chips are separated from the semiconductor substrate by the cleavage faces).
Therefore, it would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to enable the teachings of Fujita and arrive at : “dicing the semiconductor substrate includes: growing cracks accompanying the first modified regions and the second modified regions to reach opposite surfaces of the semiconductor substrate; and
expanding the semiconductor substrate so that the semiconductor chips are separated from the semiconductor substrate by the cracks” because using the cleavage faces necessarily creates cracks, even if the term cracks, has not been used expressly, the cleavage surfaces created by the modified regions, are used to guide the dicing process, so as to control the dicing process, while using the modified regions as gettering sites, thus reduce undesired impurities in the device layer.
Regarding claim 14: Fujita and Kim teach the claim limitation of the method of claim 8, on which this claim depends,
wherein the first modified regions (Fujita: [0020]-[0025] [0029] and [0037]: LM2) are formed by irradiating laser light (Fujita: [0020]-[0025] [0029] and [0037]: LM2) in the semiconductor substrate (Fujita: 10) from a surface of the semiconductor substrate, and
modifying portions of the semiconductor substrate where the laser light is focused, by the laser light (Fujita: [0022]-[0025], [0029] and [0037]).
Regarding claim 15: Fujita and Kim teach the claim limitation of the method of claim 8, on which this claim depends,
wherein the molding layer (Kim: 18) further extends between the package substrate (Kim: 15) and the semiconductor chip (Kim: top semiconductor chip 1C).
Regarding claim 17: Fujita and Kim teach the claim limitation of the method of claim 8, on which this claim depends,
wherein the semiconductor chip (Kim: [0156]-[0157]: 1C) is connected to the package substrate (Kim: 15) by conductive connectors (Kim: [0156]-[0157]: 17).
Alternatively, should the limitation imply that the molding layer is further located below the semiconductor chip and above the package substrate, then, Ki teaches this limitation as shown below.
Claims 15-16 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Fujita et al. (US 2019/0084080 A1), Kim et al. (US 2015/0382443 A1) and Hiraiwa et al. (US 2012/0261678 A1) as applied above and further in view of Ki et al. (US 2018/0076105 A1)
Regarding claim 15: Fujita and Kim teach the claim limitation of the method of claim 8, on which this claim depends;
Fujita as modified by Kim does not expressly teach that the molding layer further extends between the package substrate and the semiconductor chip.
Ki teaches (e.g., Figs. 1-3 and 5) a method comprising forming a molding layer ([0020] and [0026]: 400), a semiconductor chip ([0020] and [0023]: 200) and a package substrate ([0020]: 110c);
Ki further teaches that the molding layer ([0020] and [0026]: 400) further extends between the package substrate ([0020]: 110c) and the semiconductor chip ([0020] and [0023]: 200).
Therefore, it would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to include in the method of Fujita as modified by Kim, the method of forming the molding layer, such that the molding layer further extends between the package substrate and the semiconductor chip, as taught by Ki, for the benefits of protecting the semiconductor chip from all sides, and thus, better shielding the semiconductor chip from all sides, which in turn improves device reliability by shielding it from external elements.
Regarding claim 16: Fujita and Kim teach the claim limitation of the method of claim 8, on which this claim depends,
Fujita as modified by Kim does not expressly teach that the package substrate further includes a through hole at a position overlapping the semiconductor chip, and
wherein the molding layer extends to fill the through hole.
Ki teaches (e.g., Figs. 1-3B and 5) a method comprising forming a molding layer ([0020] and [0026]: 400), a semiconductor chip ([0020] and [0023]: 200) and a package substrate ([0020]: 110c);
Ki further teaches that the package substrate ([0020]: 110c) further includes a through hole ([0026]: 140) at a position overlapping the semiconductor chip ([0020] and [0023]: 200), and wherein the molding layer ([0020] and [0026]: 400) extends to fill the through hole (140).
Therefore, it would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to include in the method of Fujita as modified by Kim, the method wherein the package substrate further includes a through hole at a position overlapping the semiconductor chip, and wherein the molding layer extends to fill the through hole, as taught by Ki, for the benefits of protecting the semiconductor chip from all sides and thus better shielding the semiconductor chip more completely and improving device reliability by shielding it from all external elements.
Regarding claim 18: Fujita and Kim teach the claim limitation of the method of claim 17, on which this claim depends,
Fujita as modified by Kim does not expressly teach that forming the molding layer includes:
mounting the package substrate in a mold; and injecting the molding material into the mold, and
wherein a separation distance between the mold and the semiconductor chip is greater than a separation distance between the semiconductor chip and the package substrate.
Ki teaches (e.g., Figs. 1-3B and 5) a method comprising forming a molding layer ([0020] and [0026]: 400), a semiconductor chip ([0020] and [0023]: 200) and a package substrate ([0020]: 110c);
Ki further teaches teach that forming the molding layer includes:
mounting the package substrate ([0020]: 110c) in a mold ([0080]: 500); and injecting the molding material into the mold ([0080]: the molding material 300 is injected into the mold 500), and
wherein a separation distance between the mold (500) and the semiconductor chip (200) is greater than a separation distance between the semiconductor chip (200) and the package substrate (110a).
Therefore, it would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to include in the method of Fujita as modified by Kim, the method wherein forming the molding layer includes mounting the package substrate in a mold; and injecting the molding material into the mold, and wherein a separation distance between the mold and the semiconductor chip is greater than a separation distance between the semiconductor chip and the package substrate, as taught by Ki, for the benefits of controlling the molding process and packaging the device without voids in the molding material.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-24 have been considered but are moot because the new ground of rejection does not rely on any reference or portion of references applied in the prior rejection of record for any teaching or matter specifically challenged in the argument or newly added limitations.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HERVE-LOUIS Y ASSOUMAN whose telephone number is (571)272-2606. The examiner can normally be reached M-F: 08:30 AM-5:30 PM.
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/HERVE-LOUIS Y ASSOUMAN/ Examiner, Art Unit 2812
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