DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 10/16/25 have been fully considered but they are not persuasive.
Regarding claim 1, Applicant argues “Applicant submits that there is really no credible argument that Wang describes that the gate driver 504 operates to provide a voltage to the data comparator 565 that is proportional to the voltage applied to the input node of the transistor 308”.
Examiner respectfully disagrees. Wang teaches that a first drain source voltage VDS of the first transistor corresponding to a VDESAT1 or VDESAT2 (¶[0072], [0078]) which can be used by the controller 502 as a baseline or reference voltage (¶[0082]). VDSAT is dependent on the voltage VDS of the transistor 508. The term “proportional” is broadly defined as “corresponding in size, degree or intensity” (Merriam-Webster). Since the VDESAT value is inherently dependent on the VDS value, they are corresponding in size/degree. Therefore, Examiner maintains the rejection.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 5-7 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang et al., US 20210203309
Regarding claim 1, Wang discloses a power transistor age detection circuit comprising: a power transistor configured to pass current from a power transistor input node to a power transistor output node when the power transistor is on, an input voltage is present on the power transistor input node, and an output voltage that is lower than the input voltage is present on the power transistor output node (Fig. 5; MOSFET 508); a comparator (Fig. 5; data comparator 565) having a first comparator input node that is configured to receive a reference voltage (¶[0082]; VDESAT2 can be used by the controller 502 as a baseline or reference voltage), and a second comparator input node that is coupled to the power transistor input node so as to be configured to receive an age test voltage that is proportional on the input voltage that is applied to the power transistor input node (¶[0072]-[0078];[0089]; VDESAT2 from driver 504), the comparator being also configured to output a signal indicative of a status of the reference voltage with respect to the age test voltage (¶0090]; comparator determines package degradation which can correspond to a remaining operation lifetime); and an age detection circuit configured to receive the signal output from the comparator, and detect aging of the power transistor when the comparator, while the power transistor is on, outputs a signal indicative of particular status of the reference voltage with respect to the age test voltage (controller 502).
Regarding claim 2, Wang discloses wherein the particular status is that the age test voltage is greater than the reference voltage (¶[0018]).
Regarding claim 5, Wang discloses wherein the power transistor is a field-effect transistor (¶[0051]).
Regarding claim 6, Wang discloses wherein the power transistor is a gallium-nitride transistor (¶[0051]).
Regarding claim 7, Wang discloses wherein the power transistor is a high-electron-mobility transistor (¶[0051]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al., US 20210203309 in view of Bahl et al., US 20170254842
Regarding claim 4, Wang is silent in wherein the transistor age detection circuit further comprising a voltage divider having an output connected to the second comparator input node, such that the age test voltage is less than the input voltage of the power transistor. Bahl teaches voltage divider having an output connected to the second comparator input node, such that the age test voltage is less than the input voltage of a power transistor (Fig. 1; voltage divider circuit 116). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Bahl into Wang for the benefit of detecting the voltage level.
Claim(s) 8, 9, 12-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al., US 20210203309 in view of Lee, US 12,334,165
Regarding claim 8, Wang is silent in further comprising: a reference current source configured to provide a reference current through a voltage divider, the reference voltage generated on an output of the voltage divider. Lee teaches a reference current source configured to provide a reference current through a voltage divider, the reference voltage generated on an output of the voltage divider (Fig. 7-8; reference threshold voltage). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Lee into Wang for the benefit of generating a reference voltage so that comparison to the voltage level can be made.
Regarding claim 9, Wang is silent in a resistor of the voltage divider comprising a reference transistor in an on state. Lee teaches a resistor of the voltage divider comprising a reference transistor in an on state (Fig. 7-8; reference monitoring transistor TR_RM). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Lee into Wang for the benefit of generating a reference voltage so that comparison to the voltage level can be made.
Regarding claim 12, Wang teaches wherein the power transistor and the reference transistor are field-effect transistors (¶[0051]).
Regarding claim 13, Wang teaches wherein the power transistor and the reference transistors are gallium-nitride transistors (¶[0051]).
Regarding clam 14, Wang teaches wherein the power transistor and the reference transistor are high-electron-mobility transistors (¶[0051]).
Claim(s) 10, 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al., US 20210203309 in view of Lee, US 12,334,165 in view of Swope et al., US 2006/0238204
Regarding claim 10, Wang is silent in the second comparator input node coupled to the power transistor input node such that the age test voltage is less than 90 percent of the input voltage at the power transistor input node. Swope teaches a comparator input node coupled to an input node such that an age test voltage is less than 90 percent of an input voltage at the input node (¶[0013]; voltage monitor 22 having comparators in which a reference voltage is a percentage of a voltage being monitored). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Swope into Wang for the benefit of providing an output when an input voltage is out of regulation.
Regarding claim 11, Wang is silent in the second comparator input node coupled to the power transistor input node such that the age test voltage is less than 75 percent of the input voltage at the power transistor input node. Swope teaches a comparator input node coupled to an input node such that an age test voltage is less than 75 percent of an input voltage at the input node (¶[0013]; voltage monitor 22 having comparators in which a reference voltage is a percentage of a voltage being monitored). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Swope into Wang for the benefit of providing an output when an input voltage is out of regulation.
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al., US 20210203309 in view of Lee, US 12,334,165 in view of Xing et al., US 20240405768
Regarding claim 15, The power transistor age detection circuit according to claim 12, the power transistor and the reference transistor each having active regions formed from a same epitaxial stack. Xing teaches a power transistor and a reference transistor each having active regions formed from a same epitaxial stack (¶[0026]; transistors 110, 120). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Xing into Wang for the benefit of providing an efficient transistor testing structure.
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al., US 20210203309 in view of Lee, US 12,334,165 in view of Xing et al., US 20240405768 Aerts, US 20140167797
Regarding claim 16, Wang is silent in wherein a size ratio of a current flow area of the power transistor over a current flow area of the reference transistor is 500 or more. Aerts teaches wherein a size ratio of a current flow area of the power transistor over a current flow area of the reference transistor is 500 or more (¶[0011]). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Aerts into Wang as modified for the benefit of providing accuracy and noise reduction in testing the transistor.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/FEBA POTHEN/Examiner, Art Unit 2858