Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 5 recites the limitation "the certain delay" in line one. There is insufficient antecedent basis for this limitation in the claim. For the purpose of the current Office action, claim 5 is understood to depend from claim 4.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1,6-8,10,11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sugiyama et al (PG Pub 2018/0097096 A1) and Suzuki et al (PG Pub 2007/0187718 A1).
Regarding claim 1, Sugiyama teaches a circuit comprising a high-electron-mobility transistor, the high-electron-mobility transistor comprising: an epitaxial layer epitaxially grown (paragraphs [0090][0091]) on a substrate (10, fig. 8) in an epitaxial growth direction, the epitaxial layer comprising a channel semiconductor layer (14, paragraph [0036]) and a barrier semiconductor layer (16, paragraph [0036]) epitaxially grown on the channel semiconductor layer, an interface of the barrier semiconductor layer and the channel semiconductor layer defining a heterojunction that induces a two-dimensional electron gas (2DEG) (fig. 8) within the channel semiconductor layer, the 2DEG extending perpendicular to the epitaxial growth direction; a source contact (22, paragraph [0036]) that is in conductive contact with a first portion of the 2DEG (paragraph [0130][0131]); a drain contact (24, paragraph [0036]) that is in conductive contact with a second portion of the 2DEG (paragraph [0130][0131]); a gate contact (20, paragraph [0036]) disposed over the barrier semiconductor layer in the epitaxial growth direction, and being disposed between the drain contact and the source contact in a direction perpendicular to the epitaxial growth direction, the gate contact comprising an enhancement gate portion (on layer 18) and a depletion gate portion (on layer 20), the depletion gate portion being disposed between the enhancement gate portion and the drain contact in the direction perpendicular to the epitaxial growth direction; and a p-doped semiconductor portion (18, paragraph [0036]) between the enhancement gate portion and the barrier semiconductor layer in the epitaxial growth direction, such that the 2DEG is discontinuous (fig. 8) under the enhancement gate portion when zero volts is applied to the enhancement gate portion, the depletion gate portion being configured such that the 2DEG is continuous (fig. 8) under the depletion gate portion when zero volts is applied to the depletion gate portion.
Sugiyama does not teach a controller.
In the same field of endeavor, Suzuki teaches a controller (20/30, figs. 1 and 2), for the benefit of switching on/off biases applied to the gate and drain/source (paragraph [0042]).
Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention to include a controller for the benefit of switching on/off biases applied to the gate and drain/source.
Regarding claim 6, Sugiyama teaches the circuit according to Claim 1, the enhancement gate portion and the depletion gate portion being electrically connected together (fig. 8).
Regarding claim 7, Sugiyama (fig. 8) in view of Suzuki (fig. 1, paragraph [0042]) teaches the circuit according to Claim 6, the controller configured to apply at least a turn-on voltage to the enhancement gate portion to thereby turn on the high-electron-mobility transistor, the controller further configured to apply the turn-on voltage to the connected depletion gate portion.
Regarding claim 8, Sugiyama teaches the circuit according to Claim 1, a thickness of the enhancement gate portion being greater than a thickness of the depletion gate portion in the epitaxial growth direction (fig. 8).
Regarding claim 10, Sugiyama teaches the circuit according to Claim 1, the channel layer being a Gallium-Nitride (GaN) channel layer (paragraph [0040]).
Regarding claim 11, Sugiyama teaches the circuit according to Claim 1, the barrier layer being an Aluminum-Gallium-Nitride (AlGaN) layer (paragraph [0043]).
Claim(s) 2-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sugiyama et al (PG Pub 2018/0097096 A1) and Suzuki et al (PG Pub 2007/0187718 A1) as applied to claim 1 above, and further in view of Chang et al (PG Pub 2021/0020768 A1).
Regarding claim 2, Sugiyama remains as applied in claim 1.
Sugiyama does not teach the enhancement gate portion and the depletion gate portion being disconnected.
In the same field of endeavor, Chang teaches the enhancement gate portion (20, fig. 1) and the depletion gate portion (24) being disconnected, for the benefit of removing trapped electrons (paragraph [0028]).
Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention to disconnect the enhancement gate portion and the depletion gate portion, for the benefit of removing trapped electrons.
Regarding claim 3, note than applying different voltages to the two gate portions is an intended use of the device and does not carry patentable weight because Chang’s device can be used as claimed since the two gate portions are separate portions (fig. 1). Nonetheless, Chang teaches the circuit according to Claim 2, the controller configured to at least sometimes apply a different voltage to the enhancement gate portion than is applied to the depletion gate portion (paragraph [0028]).
Regarding claim 4, note than applying voltages to the two gate portions with a delay in between the two applications is an intended use of the device and does not carry patentable weight because Chang’s device can be used as claimed since the two gate portions are separate portions (fig. 1). Nonetheless, Suzuki in view of Chang teaches the controller circuit according to Claim 3, the controller configured to apply at least a turn-on voltage (paragraph [0028] of Chang) to the enhancement gate portion to thereby turn on the high-electron-mobility transistor, and further configured to apply a voltage to the depletion gate portion (Va, fig. 1 of Chang).
The cited art does not teach the controller is configured to apply the voltage to the depletion gate portion within a certain delay after applying the turn-on voltage to the enhancement gate portion. Applying the voltage to the depletion gate portion with a certain delay is an intended use of the device and does not carry patentable weight because Chang’s device can be used as claimed since the two gate portions are separate portions: A person can switch on/off the controller or different portions thereof to apply the voltages to the enhancement gate and depletion gate portions, for example. It was decided that “when the claim recites using an old composition or structure and the ‘use’ is directed to a result or property of that composition or structure, then the claim is anticipated.” In re May, 574 F.2d 1082, 1090, 197 USPQ 601, 607 (CCPA 1978). Also see MPEP 2112.02. It was also ruled that “apparatus claims cover what a device is, not what a device does." Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990) (emphasis in original). A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987).
Regarding claim 5, see claims 4 for features “the certain delay being 20 nanoseconds or less.”
Claim(s) 1 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang (PG Pub 2022/0223724 A1) and Suzuki et al (PG Pub 2007/0187718 A1).
Regarding claim 1, Yang teaches a circuit comprising a high-electron-mobility transistor, the high-electron-mobility transistor comprising: an epitaxial layer epitaxially grown (paragraph [0030]) on a substrate (102, fig. 1) in an epitaxial growth direction, the epitaxial layer comprising a channel semiconductor layer (106, paragraph [0032]) and a barrier semiconductor layer (108, paragraph [0034]) epitaxially grown on the channel semiconductor layer, an interface of the barrier semiconductor layer and the channel semiconductor layer defining a heterojunction that induces a two-dimensional electron gas (2DEG) (107-1 and 107-2, paragraph [0029]) within the channel semiconductor layer, the 2DEG extending perpendicular to the epitaxial growth direction; a source contact (134, paragraph [0029]) that is in conductive contact with a first portion of the 2DEG (paragraph [0040]); a drain contact (132, paragraph [0029]) that is in conductive contact with a second portion of the 2DEG (paragraph [0040]); a gate contact (120, paragraph [0029]) disposed over the barrier semiconductor layer in the epitaxial growth direction, and being disposed between the drain contact and the source contact in a direction perpendicular to the epitaxial growth direction, the gate contact comprising an enhancement gate portion (122) and a depletion gate portion (124/126), the depletion gate portion being disposed between the enhancement gate portion and the drain contact in the direction perpendicular to the epitaxial growth direction; and a p-doped semiconductor portion (110, paragraph [0034]) between the enhancement gate portion and the barrier semiconductor layer in the epitaxial growth direction, such that the 2DEG is discontinuous (fig. 1) under the enhancement gate portion when zero volts is applied to the enhancement gate portion, the depletion gate portion being configured such that the 2DEG is continuous (fig. 1) under the depletion gate portion when zero volts is applied to the depletion gate portion.
Yang does not teach a controller.
In the same field of endeavor, Suzuki teaches a controller (20/30, figs. 1 and 2), for the benefit of switching on/off biases applied to the gate and drain/source (paragraph [0042]).
Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention to include a controller for the benefit of switching on/off biases applied to the gate and drain/source.
Regarding claim 9, Yang teaches the circuit according to Claim 1, a length of the enhancement gate portion (Lb, fig. 1) being shorter than (paragraph [0036]) a length of the depletion gate portion (Lh) in the direction perpendicular to the epitaxial growth direction.
Conclusion
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/FEIFEI YEUNG LOPEZ/Primary Examiner, Art Unit 2899
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