DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Claims 1-20 are pending in the application. Claims 8-15 and 20 have been withdrawn per the 6/15/2026 restriction election (see below). Claims 1-7 and 16-19 are being examined.
Election/Restrictions
Claim 8-15 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention II, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 6/15/2026. Applicant has elected Species A and states that claims 1-7 and 16-20 read on the elected species.
Examiner notes that claims 16-20 do NOT read on elected Species A as claim 16 recites “a bus located on the first side of the top wafer”. This limitation is directed towards Species B. For this reason, claims 16-20 are withdrawn from further consideration. This action is FINAL.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/24/2023 is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Abraham et al. (US 2022/0189922 A1, hereafter Abraham1) in view of Yao et al. (US 11,600,588 B1, hereafter Yao).
Regarding claim 1, Abraham1 teaches in Fig. 5 a semiconductor device, comprising:
a device wafer (504, [0045]) having a first side (see annotated Fig. 5) and a second side (see annotated Fig. 5), wherein a plurality of qubits (see annotated Fig. 5) are located on the first side of the device wafer (504);
a bus (see annotated Fig. 5) located on the second side of the device wafer (504); and
a top wafer (502, [0045]) having a first side (see annotated Fig. 5) and a second side (see annotated Fig. 5).
Abraham1 fails to teach a first plurality of bump bonds located on the first side of the top wafer bond the top wafer with the second side of the device wafer, as Abraham1 teaches hermetic bonding between the top wafer and the device wafer. However, Yao discuses different bonding techniques in quantum devices and both bump bonds and hermetic are common in the art as superconducting contact bonds (column 5 lines 41-42). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the hermetic seal of Abraham1 to comprise bump bonds, as it is known in the art to utilize bump bonds.
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Regarding claim 2 Abraham1 in view of Yao teach the semiconductor device of claim 1, further comprising an interposer (508, [0045]) having a first side (see annotated Fig. 5) and a second side (see annotated Fig. 5), wherein a second plurality of bump bonds (506, [0045]) located on the second side of the interposer bond the interposer (506) with the first side of the device wafer (504, [0045]).
Regarding claim 3 Abraham1 in view of Yao teach the semiconductor device of claim 1, wherein the bus (see annotated Fig. 5) connects the plurality of qubits (see annotated Fig. 5) via a first set of through-silicon vias (TSVs) (see annotated Fig. 5). Abraham1 teaches in [0036] that the qubits are connected through TSVs to a coplanar waveguide, which is the bus, see annotated Fig. 5.
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Regarding claim 4, Abraham1 in view of Yao teach the semiconductor device of claim 1. Abraham1 further teaches the top wafer (502, [0045]) further comprises a first metal layer between the first plurality of bump bonds. While not explicitly shown in Fig. 5, Abraham1 teaches the cap wafer (502) is metal bonded to the qubit chip layer using a meta coating where the bond is taking place [0035]. As the modified device is utilizing bump bonds, the metal coating would also exist between the plurality of bumps.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Abraham1 in view of Yao as applied to claim 2 above, and further in view of Hertzberg et al. (US 2022/0058509 A1, hereafter Hertzberg) and Abraham et al. (US 2022/0199507 A1, hereafter Abraham2).
Regarding claim 5, Abraham1 in view of Yao teach the semiconductor device of claim 2. Abraham1 in view of Yao fail to teach wherein the interposer further comprises a second metal layer between the second plurality of bump bonds.
However, Hertzberg teaches a similar device in Fig. 5 in which there is a metal layer (ground plane, 540, [0041]) between an interposer chip (520, [0041]) and bump bonds (530, [0041]). This metal layer is used to vary the resonant frequency of the qubits [0041]. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Abraham1 in view of Yao to include the gate plane of Hertzberg to better tune the device to design specifications.
Abraham1 in view of Yao in view of Hertzberg fail to teach a second set of TSVs in the interposer. However, Abraham2 teaches in Fig. 5 a similar device in which the interposer (508, [0051]) is depicted with TSVs (509; [0051]). These TSVs provide electrical connection from the multi-level wiring layer (MLM in Fig. 5 as in FIG. 2, [0042] and [0051]). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the interposer of Abraham1 in view of Yao in view of Hertzberg to include TSVs as taught by Abraham2 in order to have electrical communication with lower levels of the device.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Abraham1 in view of Yao in view of Hertzberg in view of Abraham2 as applied to claim 5 above, and further in view of Zhao et al. (US 2025/0029912 A1, hereafter Zhang).
Regarding claim 6, Abraham1 in view of Yao in view of Hertzberg in view of Abraham2 teach the semiconductor device of claim 5. The modified device is silent on the first plurality of bump bonds and the second plurality of bump bonds are made of different materials. However, Zhao teaches a bonding method in which different materials are used for the solder balls [0013]. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Abraham1 in view of Yao in view of Hertzberg in view of Abraham2 to have the first plurality of bump bonds and second plurality of bump bonds to comprise different materials in order to have the ump bonds vary in mechanical strength and have different thermal expansions from one another (as Zhao states in [0013]) as necessary in the fabrication of the device.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Abraham1 in view of Yao as applied to claim 2 above, and further in view of Yu et al. (US 2013/0140713 A1, hereafter Yu).
Regarding claim 7, Abraham1 in view of Yao teach the semiconductor device of claim 2, further comprising a carrier wafer on the first side of the interposer. However, Yu shows in Fig. 4b a carrier wafer (400, [0037]) bonded to a carrier wafer (100, [0022]). The carrier wafer is added in order to provide structural support for the die above it [0022]. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Abraham1 in view of Yao to include a carrier wafer as taught by Yu on the first side of the interposer in order to increase structural support.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMMANTHA K SALAZ whose telephone number is (571)272-2484. The examiner can normally be reached Monday - Friday 8:00am-5:00pm.
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/SAMMANTHA K SALAZ/Examiner, Art Unit 2892
/ERIC W JONES/Primary Examiner, Art Unit 2892
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