The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA
DETAILED ACTION
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The claimed limitation of “performing a first ion implantation process to form a first local doped region in the semiconductor substrate adjacent to implant first ions of a first conductive type”, as recited in claim 1, is unclear as to which structure is claimed.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8 are rejected under 35 U.S.C. 103 as being unpatentable over Burr et al. (5,650,340) in view of Wang et al. (6,566,204) and Hsing (6,252,278) and supported by Burr et al. (5,773,863).Regarding claims 1 and 2, Burr et al. (‘340) teach in figures 4A-4J and related text a method for manufacturing a semiconductor device, comprising:
forming a gate structure 125 over a semiconductor substrate 111, wherein the gate structure has opposite first and second sides (see figure 4F);
forming a first mask, wherein the first mask covers a second side of the gate structure and does not cover a first side of the gate structure 125 (see figure 4G);
using the first mask, performing a first ion implantation process to form a first local doped region 116 in the semiconductor substrate adjacent to implant first ions of a first conductive type to the first side of the gate structure 125, wherein the first local doped region has the first conductive type P;
forming a second mask, wherein the second mask exposes the first and second sides of the gate structure; and
forming a source/drain region 131A/131B (see figure 4H) respectively on the first and second sides of the gate structure in the semiconductor substrate after forming the local doped region, wherein the source/drain region comprises a second conductive type N different from the first conductive type, and the first conductive type is p-type, and the second conductive type is n-type.
Burr et al. (‘340) do not teach in the embodiment of figures 4A-4J using the second mask, performing a second ion implantation process to implant second ions of the first conductive type to form a second local doped region in the semiconductor substrate adjacent to the second side of the gate structure and increase a doping concentration of the first local doped region, wherein the second local doped region has the first conductive type.
In other words, Burr et al. (‘340) do not teach using symmetric halo structure.
Burr et al. (‘340) encourage the use of symmetric halo structure. Burr et al. (‘340) teach in related that “While the performance of some symmetric halo devices has been encouraging, it is believed that further improvements in device performance should be attainable”.
Wang et al. teach in figures 1-4 and related text that conventional semiconductor devices are formed as symmetrical (see figure 2) or asymmetrical (see figure 4) channel enhancement-mode halo structures.
Hsing teaches in figures 7-8 and related text forming a gate structure over a semiconductor substrate, wherein the gate structure has opposite first and second sides, forming a first mask 101, wherein the first mask covers a second side of the gate structure and does not cover a first side of the gate structure, using the first mask, performing a first ion implantation process to form a first local doped region 52 in the semiconductor substrate adjacent to the first side of the gate structure, wherein the first local doped region has a first conductive type, forming a second mask 103, wherein the second mask exposes the first and second sides of the gate structure; and using the second mask 103, performing a second ion implantation process to form a second local doped region in the semiconductor substrate adjacent to the second side of the gate structure wherein the second local doped region has the first conductive type.
Burr et al. (‘863), Burr et al. (‘340), Hsing, Wang et al. are analogous art because they are directed to semiconductor devices comprising halo structures and one of ordinary skill in the art would have had a reasonable expectation of success to modify Burr et al. (‘340) because they are from the same field of endeavor.It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form a symmetrical halo structure, as taught by Wang et al., by using the second mask, performing a second ion implantation process to form a second local doped region in the semiconductor substrate adjacent to the second side of the gate structure, as taught by Hsing, and to increase a doping concentration of the first local doped region (inherently therein because the first local doped region undoes two implantation processes), wherein the second local doped region has the first conductive type, in Burr et al. (‘340)’s device, in order to expand the application prospects of the device by using the structure in devices having low threshold voltages, in order to further improve the device characteristics and in order to simplify the processing steps of making the device by using conventional implantation processes.
The combination is motivated by the teaching of Burr et al. (‘863) who point out the advantages of using symmetrical halo implant structure (see e.g. figure 5 of Burr et al. (‘863))
Regarding claim 3, Burr et al. (‘340) teach in figures 4A-4J and related text using the second mask, performing a third ion implantation process to form a lightly doped region 131A, 131B respectively on the first and second sides of the gate structure in the semiconductor substrate, wherein the lightly doped region comprises the second conductive type, and a doping concentration of the lightly doped region N- is lower than a doping concentration of the source/drain region N+.
Regarding claims 4-5, it would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form a doping dose of the first ion implantation process greater or less than a doping dose of the second ion implantation process in prior art’s device, in order to adjust the conductivity of the transistor according to the requirements of the application in hand.
Regarding claim 6, Burr et al. (‘340) teach in figures 4A-4J and related text forming a well 121 in the semiconductor substrate, wherein the well comprises the first conductive type, and forming the gate structure is performed such that the gate structure is over the well.
Regarding claim 7, Burr et al. (‘340) teach in figures 4A-4J and related text forming the source/drain region comprises: forming a third mask (not depicted), wherein the second mask exposes the first and second sides of the gate structure; and using the third mask, performing a third ion implantation process (see figure 4I).
Regarding claim 8, Burr et al. (‘340) teach in figures 4A-4J and related text forming the gate structure is performed such that the gate structure is over the active region, and the first ion implantation process and the second ion implantation process are performed such that the first and second local doped regions are in the active region.
Burr et al. (‘340) do not teach forming an isolation structure in the semiconductor substrate to define an active region.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form an isolation structure in the semiconductor substrate to define an active region in prior art’s device, in order to provide better protection to the device, as is well-known in the art.
Response to Arguments
Applicants argue that Hsing does not teach that the first conductive type is p-type, and the second conductive type is n-type.
However, the primary reference to Burr et al. (‘340) teaches that the first conductive type is p-type, and the second conductive type is n-type.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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O.N. /ORI NADAV/
7/24/2026 PRIMARY EXAMINER
TECHNOLOGY CENTER 2800
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