DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant’s election without traverse of Group-I (Claims 1-3, 11-13 and 20) in the reply filed on 06/11/2026 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 11-13 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over MCKNIGHT-MACNEIL et al. (US PGpub: 2022/0020669 A1 A1), herein after MCKNIGHT-MACNEIL, in view of known arts like MCKNIGHT-MACNEIL or, Elsherbini et al. (US 2020/0091128 A1).
Regarding claim 1, MCKNIGHT-MACNEIL teaches a power module (GaN power transistors, such as GaN HEMTs, provide for high current, FIG. 6A-29 and description) , comprising:
a substrate (Backside of die in FIG. 6B);
at least four conductive traces (Conductive micro via 140 as in FIG. 7) disposed on the substrate, each conductive trace including:
an insulation board (After forming the conductive vias 140 and 150, and thermal vias 170, the source and drain interconnect areas, 132-2 and 134-2, and thermal pad 180-2, a fourth (back-side) dielectric build-up layer 120-4 is provided on the back-side of the layer stack…… dielectric layers 120-1, 120-2, 120-3 and 120-4, with drilling of micro-vias and vias, and copper plating steps to form electrically conductive vias, thermal vias and the first, second and third copper layers 130-1, 130-2 and 130-3, for the conductive interconnect layers. The conductive interconnect layers are patterned to define internal conductive interconnect traces, and to define external electrical contact pads and the thermal pads.);
a gate bus disposed on the insulation board (Micro-vias are laser drilled through the fourth dielectric build-up layer 120-4 to contact respective areas of the source, drain, gate portions of the second conductive layer 130-2 and the thermal pad 180-2 defined by the second conductive layer 130-2. A copper plating process is then performed to fill the drilled vias and form the electrically conductive vias and thermal vias, and to build up the thickness of the third copper layer 130-3 to a required thickness. The third copper layer 130-3 is patterned to define an external source pad 132-3, drain pad 134-3 and thermal pad 180-3, and a gate pad (not shown in this view). A patterned coating of solder resist 190 is provided on the back-side, as is conventional, with openings to the source pad 132-3, drain pad 134-3, gate pad, and the thermal pad 180-4.);
a kelvin bus disposed on the insulation board (FIG. 6A, for example, for a GaN power transistor device, there is one large area drain pad and one large area source pad and dual gate pads. The external pads of the embedded die package may be arranged as a single external pad for each of the source, drain and gate. Alternatively, there may be single/multiple/distributed external pads, such as dual gate pads, and a source pad and a source sense (Kelvin source) pad. It is also known to have multiple/distributed external pads for an embedded source bus and/or embedded drain bus. For example, various arrangements of external source, drain and gate pads are illustrated in datasheets for currently available products of GaN Systems Inc.); and
a semiconductor die operating as a transistor, the semiconductor die including a drain, a gate, and a source (The back (bottom) side of the package comprises a thermal pad, and source, drain and gate contact pads….. The die 10 comprises source, drain and gate contact areas defined by a low inductance, thick copper redistribution layer (Cu-RDL) on the front-side, and a back-side layer of conductive metallization (back-side metal). In GaNPx type embedded packages, the front-side Cu-RDL provides electrical contacts. For example, as illustrated schematically in FIGS. 6A and 6B, the Cu-RDL defines large area source and drain contact areas (source and drain pads) with interdigitated extensions (e.g. tapered portions or fingers), and dual gate contact areas (gate pads). The back-side metallization, which is thermally and electrically conductive, provides for thermal contact through thermal vias to the thermal pad, and also allows for a back-side source connection, if required. In the following description, references to “front-side” and “back-side” are with respect to the GaN die, as indicated in FIGS. 6A and 6B, i.e. wherein the substrate side of the die is the back-side and the active area of the lateral GaN transistor and its source, drain and gate contacts are provided on the front-side of the die; and references to “top” and “bottom” are with respect to the package, as it would be mounted on a substrate, such as a support surface of a power module or PCB. For example, in the embedded die package of this example the external source, drain and gate pads are on the same surface (bottom) of the package that is to be mounted on the substrate surface. Customarily, this configuration may be referred to as having a bottom side thermal pad, and the terms “top” and “bottom” are not intended to limit the orientation of the package as it would be surface mounted for operation ),
MCKNIGHT-MACNEIL does not explicitly teach wherein the drain is coupled to the conductive trace, the source is coupled to the kelvin bus and to an electrical connection off of the conductive trace, and the gate is coupled to the gate bus.
However, it is obvious to the skilled person from MCKNIGHT-MACNEIL’s teaching that the drain is coupled to the conductive trace, the source is coupled to the kelvin bus and to an electrical connection off of the conductive trace, and the gate is coupled to the gate bus. Or, see US 20200091128 A1 Elsherbini et al. (The IC device (FIG. 7A-9) 1600 may include one or more device layers 1604 disposed on the die substrate 1602. The device layer 1604 may include features of one or more transistors 1640 (e.g., metal oxide semiconductor field-effect transistors (MOSFETs)) formed on the die substrate 1602. The device layer 1604 may include, for example, one or more source and/or drain (S/D) regions 1620, a gate 1622 to control current flow in the transistors 1640 between the S/D regions 1620, and one or more S/D contacts 1624 to route electrical signals to/from the S/D regions 1620. The transistors 1640 may include additional features not depicted for the sake of clarity, such as device isolation regions, gate contacts, and the like. The transistors 1640 are not limited to the type and configuration depicted in FIG. 9 and may include a wide variety of other types and configurations such as, for example, planar transistors, non-planar transistors, or a combination of both. Non-planar transistors may include FinFET transistors, such as double-gate transistors or tri-gate transistors, and wrap-around or all-around gate transistors, such as nanoribbon and nanowire transistors.)
Hence, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use MCKNIGHT-MACNEIL’s power module with other teaching from MCKNIGHT-MACNEIL or Elsherbini so that The power device exhibit better power delivery and signal speed
Regarding claim 2, MCKNIGHT-MACNEIL teaches the power module of claim 1, wherein the at least four conductive traces include a first conductive trace, a second conductive trace, a third conductive trace and a fourth conductive trace arranged in a single column (all traces can be thought in a column from side of reference, FIG. 24).
Regarding claim 3, MCKNIGHT-MACNEIL teaches the power module of claim 2, further comprising a neutral point terminal, a first diode between the second conductive trace and the neutral point terminal, and a second diode between the fourth conductive trace and the neutral point terminal (In other embodiments, the power semiconductor device may comprise a GaN power diode. While embodiments of embedded die packaging for a power semiconductor device are described in detail with refer to a power semiconductor device comprising a GaN power transistor, a power semiconductor device may comprise a GaN diode. The power semiconductor device may comprise a plurality of GaN power transistors, a plurality GaN power diodes, a combination of at least one GaN power transistor and at least one power diode. For example, the die may comprise a power semiconductor device which comprises a plurality of GaN transistors configured as one of: a half-bridge, a full-bridge, and other switching topologies. The die may comprise other components, integrated with the power semiconductor device, e.g., one or more of driver circuitry, control circuitry, sensors, passive components, et al., The power semiconductor device may be co-packaged and interconnected with other components, such as a driver chip, embedded in the package.).
Regarding claim 11, MCKNIGHT-MACNEIL teaches a multi-level inverter package (embedded die package, .GaN power transistors, such as GaN HEMTs, provide for high current, FIG. 6A-29 and description), comprising:
at least four conductive traces (Conductive micro via 140 as in FIG. 7) disposed on the substrate, each conductive trace including:
an insulation board (After forming the conductive vias 140 and 150, and thermal vias 170, the source and drain interconnect areas, 132-2 and 134-2, and thermal pad 180-2, a fourth (back-side) dielectric build-up layer 120-4 is provided on the back-side of the layer stack…… dielectric layers 120-1, 120-2, 120-3 and 120-4, with drilling of micro-vias and vias, and copper plating steps to form electrically conductive vias, thermal vias and the first, second and third copper layers 130-1, 130-2 and 130-3, for the conductive interconnect layers. The conductive interconnect layers are patterned to define internal conductive interconnect traces, and to define external electrical contact pads and the thermal pads.);
a gate bus disposed on the insulation board (Micro-vias are laser drilled through the fourth dielectric build-up layer 120-4 to contact respective areas of the source, drain, gate portions of the second conductive layer 130-2 and the thermal pad 180-2 defined by the second conductive layer 130-2. A copper plating process is then performed to fill the drilled vias and form the electrically conductive vias and thermal vias, and to build up the thickness of the third copper layer 130-3 to a required thickness. The third copper layer 130-3 is patterned to define an external source pad 132-3, drain pad 134-3 and thermal pad 180-3, and a gate pad (not shown in this view). A patterned coating of solder resist 190 is provided on the back-side, as is conventional, with openings to the source pad 132-3, drain pad 134-3, gate pad, and the thermal pad 180-4.);; and
a kelvin bus disposed on the insulation board (FIG. 6A, for example, for a GaN power transistor device, there is one large area drain pad and one large area source pad and dual gate pads. The external pads of the embedded die package may be arranged as a single external pad for each of the source, drain and gate. Alternatively, there may be single/multiple/distributed external pads, such as dual gate pads, and a source pad and a source sense (Kelvin source) pad. It is also known to have multiple/distributed external pads for an embedded source bus and/or embedded drain bus. For example, various arrangements of external source, drain and gate pads are illustrated in datasheets for currently available products of GaN Systems Inc.); and
a semiconductor die operating as a transistor, the semiconductor die including a drain, a gate, and a source (The back (bottom) side of the package comprises a thermal pad, and source, drain and gate contact pads….. The die 10 comprises source, drain and gate contact areas defined by a low inductance, thick copper redistribution layer (Cu-RDL) on the front-side, and a back-side layer of conductive metallization (back-side metal). In GaNPx type embedded packages, the front-side Cu-RDL provides electrical contacts. For example, as illustrated schematically in FIGS. 6A and 6B, the Cu-RDL defines large area source and drain contact areas (source and drain pads) with interdigitated extensions (e.g. tapered portions or fingers), and dual gate contact areas (gate pads). The back-side metallization, which is thermally and electrically conductive, provides for thermal contact through thermal vias to the thermal pad, and also allows for a back-side source connection, if required. In the following description, references to “front-side” and “back-side” are with respect to the GaN die, as indicated in FIGS. 6A and 6B, i.e. wherein the substrate side of the die is the back-side and the active area of the lateral GaN transistor and its source, drain and gate contacts are provided on the front-side of the die; and references to “top” and “bottom” are with respect to the package, as it would be mounted on a substrate, such as a support surface of a power module or PCB. For example, in the embedded die package of this example the external source, drain and gate pads are on the same surface (bottom) of the package that is to be mounted on the substrate surface. Customarily, this configuration may be referred to as having a bottom side thermal pad, and the terms “top” and “bottom” are not intended to limit the orientation of the package as it would be surface mounted for operation ),
MCKNIGHT-MACNEIL does not explicitly teach wherein the drain is coupled to the conductive trace, the source is coupled to the kelvin bus and to an electrical connection off of the conductive trace, and the gate is coupled to the gate bus.
However, it is obvious to the skilled person from MCKNIGHT-MACNEIL’s teaching that the drain is coupled to the conductive trace, the source is coupled to the kelvin bus and to an electrical connection off of the conductive trace, and the gate is coupled to the gate bus. Or, see US 20200091128 A1 Elsherbini et al. (The IC device (FIG. 7A-9) 1600 may include one or more device layers 1604 disposed on the die substrate 1602. The device layer 1604 may include features of one or more transistors 1640 (e.g., metal oxide semiconductor field-effect transistors (MOSFETs)) formed on the die substrate 1602. The device layer 1604 may include, for example, one or more source and/or drain (S/D) regions 1620, a gate 1622 to control current flow in the transistors 1640 between the S/D regions 1620, and one or more S/D contacts 1624 to route electrical signals to/from the S/D regions 1620. The transistors 1640 may include additional features not depicted for the sake of clarity, such as device isolation regions, gate contacts, and the like. The transistors 1640 are not limited to the type and configuration depicted in FIG. 9 and may include a wide variety of other types and configurations such as, for example, planar transistors, non-planar transistors, or a combination of both. Non-planar transistors may include FinFET transistors, such as double-gate transistors or tri-gate transistors, and wrap-around or all-around gate transistors, such as nanoribbon and nanowire transistors.)
Hence, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use MCKNIGHT-MACNEIL’s power module with other teaching from MCKNIGHT-MACNEIL or Elsherbini so that The power device exhibit better power delivery and signal speed.
Regarding claim 12, MCKNIGHT-MACNEIL teaches the multi-level inverter package of claim 11, wherein the at least four conductive traces include a first conductive trace, a second conductive trace, a third conductive trace and a fourth conductive trace arranged in a single column (all traces can be thought in a column from side of reference, FIG. 24)...
Regarding claim 13, MCKNIGHT-MACNEIL teaches the multi-level inverter package of claim 12, further comprising a neutral point terminal, a first diode between the second conductive trace and the neutral point terminal, and a second diode between the fourth conductive trace and the neutral point terminal (In other embodiments, the power semiconductor device may comprise a GaN power diode. While embodiments of embedded die packaging for a power semiconductor device are described in detail with refer to a power semiconductor device comprising a GaN power transistor, a power semiconductor device may comprise a GaN diode. The power semiconductor device may comprise a plurality of GaN power transistors, a plurality GaN power diodes, a combination of at least one GaN power transistor and at least one power diode. For example, the die may comprise a power semiconductor device which comprises a plurality of GaN transistors configured as one of: a half-bridge, a full-bridge, and other switching topologies. The die may comprise other components, integrated with the power semiconductor device, e.g., one or more of driver circuitry, control circuitry, sensors, passive components, et al., The power semiconductor device may be co-packaged and interconnected with other components, such as a driver chip, embedded in the package.).
Regarding claim 20, MCKNIGHT-MACNEIL teaches A vehicle comprising: a multi-level inverter package (embedded die package, .GaN power transistors, such as GaN HEMTs, provide for high current, FIG. 6A-29 and description), comprising:
a substrate (Backside of die in FIG. 6B);
at least four conductive traces (Conductive micro via 140 as in FIG. 7) disposed on the substrate, each conductive trace including:
an insulation board (After forming the conductive vias 140 and 150, and thermal vias 170, the source and drain interconnect areas, 132-2 and 134-2, and thermal pad 180-2, a fourth (back-side) dielectric build-up layer 120-4 is provided on the back-side of the layer stack…… dielectric layers 120-1, 120-2, 120-3 and 120-4, with drilling of micro-vias and vias, and copper plating steps to form electrically conductive vias, thermal vias and the first, second and third copper layers 130-1, 130-2 and 130-3, for the conductive interconnect layers. The conductive interconnect layers are patterned to define internal conductive interconnect traces, and to define external electrical contact pads and the thermal pads.);
a gate bus disposed on the insulation board (Micro-vias are laser drilled through the fourth dielectric build-up layer 120-4 to contact respective areas of the source, drain, gate portions of the second conductive layer 130-2 and the thermal pad 180-2 defined by the second conductive layer 130-2. A copper plating process is then performed to fill the drilled vias and form the electrically conductive vias and thermal vias, and to build up the thickness of the third copper layer 130-3 to a required thickness. The third copper layer 130-3 is patterned to define an external source pad 132-3, drain pad 134-3 and thermal pad 180-3, and a gate pad (not shown in this view). A patterned coating of solder resist 190 is provided on the back-side, as is conventional, with openings to the source pad 132-3, drain pad 134-3, gate pad, and the thermal pad 180-4.);
a kelvin bus disposed on the insulation board (FIG. 6A, for example, for a GaN power transistor device, there is one large area drain pad and one large area source pad and dual gate pads. The external pads of the embedded die package may be arranged as a single external pad for each of the source, drain and gate. Alternatively, there may be single/multiple/distributed external pads, such as dual gate pads, and a source pad and a source sense (Kelvin source) pad. It is also known to have multiple/distributed external pads for an embedded source bus and/or embedded drain bus. For example, various arrangements of external source, drain and gate pads are illustrated in datasheets for currently available products of GaN Systems Inc.); and
a semiconductor die operating as a transistor, the semiconductor die including a drain, a gate, and a source (The back (bottom) side of the package comprises a thermal pad, and source, drain and gate contact pads….. The die 10 comprises source, drain and gate contact areas defined by a low inductance, thick copper redistribution layer (Cu-RDL) on the front-side, and a back-side layer of conductive metallization (back-side metal). In GaNPx type embedded packages, the front-side Cu-RDL provides electrical contacts. For example, as illustrated schematically in FIGS. 6A and 6B, the Cu-RDL defines large area source and drain contact areas (source and drain pads) with interdigitated extensions (e.g. tapered portions or fingers), and dual gate contact areas (gate pads). The back-side metallization, which is thermally and electrically conductive, provides for thermal contact through thermal vias to the thermal pad, and also allows for a back-side source connection, if required. In the following description, references to “front-side” and “back-side” are with respect to the GaN die, as indicated in FIGS. 6A and 6B, i.e. wherein the substrate side of the die is the back-side and the active area of the lateral GaN transistor and its source, drain and gate contacts are provided on the front-side of the die; and references to “top” and “bottom” are with respect to the package, as it would be mounted on a substrate, such as a support surface of a power module or PCB. For example, in the embedded die package of this example the external source, drain and gate pads are on the same surface (bottom) of the package that is to be mounted on the substrate surface. Customarily, this configuration may be referred to as having a bottom side thermal pad, and the terms “top” and “bottom” are not intended to limit the orientation of the package as it would be surface mounted for operation ).
MCKNIGHT-MACNEIL does not explicitly teach wherein the drain is coupled to the conductive trace, the source is coupled to the kelvin bus and to an electrical connection off of the conductive trace, and the gate is coupled to the gate bus..
However, it is obvious to the skilled person from MCKNIGHT-MACNEIL’s teaching that the drain is coupled to the conductive trace, the source is coupled to the kelvin bus and to an electrical connection off of the conductive trace, and the gate is coupled to the gate bus. Or, see US 20200091128 A1 Elsherbini et al. (The IC device (FIG. 7A-9) 1600 may include one or more device layers 1604 disposed on the die substrate 1602. The device layer 1604 may include features of one or more transistors 1640 (e.g., metal oxide semiconductor field-effect transistors (MOSFETs)) formed on the die substrate 1602. The device layer 1604 may include, for example, one or more source and/or drain (S/D) regions 1620, a gate 1622 to control current flow in the transistors 1640 between the S/D regions 1620, and one or more S/D contacts 1624 to route electrical signals to/from the S/D regions 1620. The transistors 1640 may include additional features not depicted for the sake of clarity, such as device isolation regions, gate contacts, and the like. The transistors 1640 are not limited to the type and configuration depicted in FIG. 9 and may include a wide variety of other types and configurations such as, for example, planar transistors, non-planar transistors, or a combination of both. Non-planar transistors may include FinFET transistors, such as double-gate transistors or tri-gate transistors, and wrap-around or all-around gate transistors, such as nanoribbon and nanowire transistors.)
Hence, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use MCKNIGHT-MACNEIL’s power module with other teaching from MCKNIGHT-MACNEIL or Elsherbini so that The power device exhibit better power delivery and signal speed
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See form PTO-892.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHEIKH MARUF whose telephone number is (571)270-1903. The examiner can normally be reached on M-F, 8am-6pm EDT.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached on 571-270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SHEIKH MARUF/Primary Examiner, Art Unit 2897
Prosecution Insights