DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-15, 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shimanuki (US 2002/0079563 A1).
With respect to claim 1, Shimanuki discloses, in Figs.1-17, an electronic device, comprising: opposite first/(bottom surface) (12a) and second/(up surface) sides; opposite third/(horizontal and vertical sides surface) and fourth/(horizontal and vertical side surface) sides spaced apart from one another along a first direction/(cross sectional direction cutting between opposing leads 2 of horizontal/vertical sides and orthogonal to side of 4b-c); opposite fifth/(inclined surface between vertical and horizontal surface)/(side of4b) and sixth/(inclined surface between vertical and horizontal surface)/(side of 4c) sides spaced apart from one another along a second direction/(B-B, E-E or G-G cross sectional direction) that is orthogonal to the first direction, the first and second sides spaced apart from one another along a third direction/(up-down direction) that is orthogonal to the first and second directions (see Fig.2, Par.[0083]-[0086] wherein a section of each of leads 2, which are used as terminals for external connection, is exposed in the peripheral region of back surface 12a (surface on which the semiconductor device is mounted) of the molded section (resin) of said semiconductor device; see Par.[0091] wherein Supporting portions 4a of suspension leads 4 are bent away from exposed surfaces 4c of exposed portions 4b (i.e., in the direction of the surface that is opposite back surface 12a of molded section 12 of QFN1)); a molded package structure (12) (see Par.[0085] wherein molded section 12 that is formed by resin-molding around semiconductor chip 8; suspension leads 4, including the supporting portions 4a that support tub 5 and exposed portions 4b that are connected to the supporting portions and are exposed on back surface 12a of molded section 12, and is processed so that its supporting portions 4a are elevated (by a process of bending to elevate the tub); multiple leads 2 that are located around tub 5 and are exposed on back surface 12a of molded section 12; and thin metal wires (bonding wires) 10 that connect each of the electrode pads (bonding pads) of semiconductor chip 8 with a corresponding lead 2); conductive metal first leads (2) exposed outside the molded package structure (12) along the first side (12a), and individual ones of the first leads (2) extending outward from the molded package structure (12) along a respective one of the third and fourth sides; and conductive metal second leads (4) exposed outside the molded package structure (12) along the first side (12a), individual ones of the second leads (4) having a lateral side exposed outside the molded package structure (12) along a respective one of the fifth and sixth sides, and the lateral side of the individual second leads being flush with a respective side of the molded package structure (12) along the respective one of the fifth and sixth sides (4b-c) (see Fig.2 wherein leads 2 and 4 disposition of leads 2 and 4 are shown).
With respect to claim 2, Shimanuki discloses, in Figs.1-17, the electronic device, comprising: a die attach pad (5a) (see Par.[0095]-[0096] wherein tub 5 has chip-supporting surface 5a that is smaller than semiconductor chip 8. Tub 5 of embodiment 1 is of the cross type, where chip-supporting surface 5a forms a cross, and is also referred to as a small tub); and a first tie bar (15) connected to the die attach pad (5a) and exposed outside the molded package structure along the fifth side (see Par.[0105]-[0106], [0111], [0122] wherein in suspension leads 4 of individual leadframe 15 as shown in FIGS. 5 and 6, supporting portions 4a are bent away from exposed surfaces 4c of exposed portions 4b; leads 2 and suspension leads 4 of individual leadframes 15 of matrix leadframe 14 are cut at positions that are slightly outside the areas of each of molded sections 12; see Par.[0094], [0114]-[0116] wherein stepped portions 6 (the elevating portions) of supporting portions 4a of suspension leads 4 are placed outside the area of bonding stage 3 shown in FIG. 8. Specifically, processing to elevate the tub (elevation processing) is applied to the respective supporting portions 4a of the four suspension leads 4 outside the area of semiconductor chip 8; stepped portions 6 of supporting portions 4a of suspension leads 4 are formed outside the area of semiconductor chip 8, and not directly below semiconductor chip 8).
With respect to claim 3, Shimanuki discloses, in Figs.1-17, the electronic device, comprising a second tie bar (6) spaced apart from the tie bar (15) and exposed outside the molded package structure along the fifth side/(side of 4b) (see Par.[0105]-[0106], [0111], [0122] wherein in suspension leads 4 of individual leadframe 15 as shown in FIGS. 5 and 6, supporting portions 4a are bent away from exposed surfaces 4c of exposed portions 4b; leads 2 and suspension leads 4 of individual leadframes 15 of matrix leadframe 14 are cut at positions that are slightly outside the areas of each of molded sections 12; see Par.[0094], [0114]-[0116] wherein stepped portions 6 (the elevating portions) of supporting portions 4a of suspension leads 4 are placed outside the area of bonding stage 3 shown in FIG. 8. Specifically, processing to elevate the tub (elevation processing) is applied to the respective supporting portions 4a of the four suspension leads 4 outside the area of semiconductor chip 8; stepped portions 6 of supporting portions 4a of suspension leads 4 are formed outside the area of semiconductor chip 8, and not directly below semiconductor chip 8).
With respect to claim 4, Shimanuki discloses, in Figs.1-17, the electronic device, comprising: a third tie bar (6) exposed outside the molded package structure (12) along the sixth side (4c); and a fourth tie bar (6) spaced apart from the third tie bar (6) and exposed outside the molded package structure along the sixth side/(side of 4c) (see Par.[0105]-[0106], [0111], [0122] wherein in suspension leads 4 of individual leadframe 15 as shown in FIGS. 5 and 6, supporting portions 4a are bent away from exposed surfaces 4c of exposed portions 4b; leads 2 and suspension leads 4 of individual leadframes 15 of matrix leadframe 14 are cut at positions that are slightly outside the areas of each of molded sections 12; see Par.[0094], [0114]-[0116] wherein stepped portions 6 (the elevating portions) of supporting portions 4a of suspension leads 4 are placed outside the area of bonding stage 3 shown in FIG. 8. Specifically, processing to elevate the tub (elevation processing) is applied to the respective supporting portions 4a of the four suspension leads 4 outside the area of semiconductor chip 8; stepped portions 6 of supporting portions 4a of suspension leads 4 are formed outside the area of semiconductor chip 8, and not directly below semiconductor chip 8).
With respect to claim 5, Shimanuki discloses, in Figs.1-17, the electronic device, wherein: a first set of the second leads (4b, 4c) are spaced apart from one another along the first direction and have respective lateral sides exposed outside the molded package structure (12) along the fifth side; the first tie bar (15) is exposed outside the molded package structure (12) along the fifth side between a first corner of the molded package structure (12) and the first set of the second leads (4); the second tie bar (6) is exposed outside the molded package structure (12) along the fifth side between a second corner of the molded package structure (12) and the first set of the second leads (4b, 4c); a second set of the second leads (4b, 4c) are spaced apart from one another along the first direction and have respective lateral sides exposed outside the molded package structure along the sixth side; the third tie bar (6) is exposed outside the molded package structure along the sixth side between a third corner of the molded package structure (12) and the second set of the second leads (4b, 4c); and the fourth tie bar (6) is exposed outside the molded package structure (12) along the sixth side between a fourth corner of the molded package structure (12) and the second set of the second leads (4b, 4c) (see Fig.2, Par.[0083]-[0086] wherein a section of each of leads 2, which are used as terminals for external connection, is exposed in the peripheral region of back surface 12a (surface on which the semiconductor device is mounted) of the molded section (resin) of said semiconductor device; see Par.[0091] wherein Supporting portions 4a of suspension leads 4 are bent away from exposed surfaces 4c of exposed portions 4b (i.e., in the direction of the surface that is opposite back surface 12a of molded section 12 of QFN1); see Par.[0105]-[0106], [0111], [0122] wherein in suspension leads 4 of individual leadframe 15 as shown in FIGS. 5 and 6, supporting portions 4a are bent away from exposed surfaces 4c of exposed portions 4b; leads 2 and suspension leads 4 of individual leadframes 15 of matrix leadframe 14 are cut at positions that are slightly outside the areas of each of molded sections 12; see Par.[0094], [0114]-[0116] wherein stepped portions 6 (the elevating portions) of supporting portions 4a of suspension leads 4 are placed outside the area of bonding stage 3 shown in FIG. 8. Specifically, processing to elevate the tub (elevation processing) is applied to the respective supporting portions 4a of the four suspension leads 4 outside the area of semiconductor chip 8; stepped portions 6 of supporting portions 4a of suspension leads 4 are formed outside the area of semiconductor chip 8, and not directly below semiconductor chip 8).
With respect to claim 6, Shimanuki discloses, in Figs.1-17, the electronic device, wherein: a first set of the second leads (4b, 4c) are spaced apart from one another along the first direction and have respective lateral sides exposed outside the molded package structure along the fifth side; and a second set of the second leads (4b, 4c) are spaced apart from one another along the first direction and have respective lateral sides exposed outside the molded package structure along the sixth side (see Par.[0105]-[0106], [0111], [0122] wherein in suspension leads 4 of individual leadframe 15 as shown in FIGS. 5 and 6, supporting portions 4a are bent away from exposed surfaces 4c of exposed portions 4b; leads 2 and suspension leads 4 of individual leadframes 15 of matrix leadframe 14 are cut at positions that are slightly outside the areas of each of molded sections 12; see Par.[0094], [0114]-[0116] wherein stepped portions 6 (the elevating portions) of supporting portions 4a of suspension leads 4 are placed outside the area of bonding stage 3 shown in FIG. 8. Specifically, processing to elevate the tub (elevation processing) is applied to the respective supporting portions 4a of the four suspension leads 4 outside the area of semiconductor chip 8; stepped portions 6 of supporting portions 4a of suspension leads 4 are formed outside the area of semiconductor chip 8, and not directly below semiconductor chip 8).
With respect to claim 7, Shimanuki discloses, in Figs.1-17, the electronic device, wherein: a first set of the first leads (2) are spaced apart from one another along the second direction and have respective lateral sides exposed outside the molded package structure (12) along the third side; and a second set the first leads (2) are spaced apart from one another along the second direction and have respective lateral sides exposed outside the molded package structure along the fourth side (see Par.[0105]-[0106], [0111], [0122] wherein in suspension leads 4 of individual leadframe 15 as shown in FIGS. 5 and 6, supporting portions 4a are bent away from exposed surfaces 4c of exposed portions 4b; leads 2 and suspension leads 4 of individual leadframes 15 of matrix leadframe 14 are cut at positions that are slightly outside the areas of each of molded sections 12; see Par.[0094], [0114]-[0116] wherein stepped portions 6 (the elevating portions) of supporting portions 4a of suspension leads 4 are placed outside the area of bonding stage 3 shown in FIG. 8. Specifically, processing to elevate the tub (elevation processing) is applied to the respective supporting portions 4a of the four suspension leads 4 outside the area of semiconductor chip 8; stepped portions 6 of supporting portions 4a of suspension leads 4 are formed outside the area of semiconductor chip 8, and not directly below semiconductor chip 8).
With respect to claim 8, Shimanuki discloses, in Figs.1-17, the electronic device, comprising a semiconductor die (8) electrically coupled to one of the first leads (2) and to one of the second leads (4b, 4c) (see Figs.4(a)-4(b)).
With respect to claim 9, Shimanuki discloses, in Figs.1-17, the electronic device, wherein: a first set of the second leads (4b, 4c) are spaced apart from one another along the first direction and have respective lateral sides exposed outside the molded package structure along the fifth side; and a second set of the second leads (4b, 4c) are spaced apart from one another along the first direction and have respective lateral sides exposed outside the molded package structure (12) along the sixth side (see Par.[0105]-[0106], [0111], [0122] wherein in suspension leads 4 of individual leadframe 15 as shown in FIGS. 5 and 6, supporting portions 4a are bent away from exposed surfaces 4c of exposed portions 4b; leads 2 and suspension leads 4 of individual leadframes 15 of matrix leadframe 14 are cut at positions that are slightly outside the areas of each of molded sections 12; see Par.[0094], [0114]-[0116] wherein stepped portions 6 (the elevating portions) of supporting portions 4a of suspension leads 4 are placed outside the area of bonding stage 3 shown in FIG. 8. Specifically, processing to elevate the tub (elevation processing) is applied to the respective supporting portions 4a of the four suspension leads 4 outside the area of semiconductor chip 8; stepped portions 6 of supporting portions 4a of suspension leads 4 are formed outside the area of semiconductor chip 8, and not directly below semiconductor chip 8).
With respect to claim 10, Shimanuki discloses, in Figs.1-17, the electronic device, wherein: a first set of the first leads (2) are spaced apart from one another along the second direction and have respective lateral sides exposed outside the molded package structure (12) along the third side; and a second set the first leads (2) are spaced apart from one another along the second direction and have respective lateral sides exposed outside the molded package structure (12) along the fourth side (see Par.[0105]-[0106], [0111], [0122] wherein in suspension leads 4 of individual leadframe 15 as shown in FIGS. 5 and 6, supporting portions 4a are bent away from exposed surfaces 4c of exposed portions 4b; leads 2 and suspension leads 4 of individual leadframes 15 of matrix leadframe 14 are cut at positions that are slightly outside the areas of each of molded sections 12; see Par.[0094], [0114]-[0116] wherein stepped portions 6 (the elevating portions) of supporting portions 4a of suspension leads 4 are placed outside the area of bonding stage 3 shown in FIG. 8. Specifically, processing to elevate the tub (elevation processing) is applied to the respective supporting portions 4a of the four suspension leads 4 outside the area of semiconductor chip 8; stepped portions 6 of supporting portions 4a of suspension leads 4 are formed outside the area of semiconductor chip 8, and not directly below semiconductor chip 8).
With respect to claim 11, Shimanuki discloses, in Figs.1-17, the electronic device, wherein: a first set of the first leads (2) are spaced apart from one another along the second direction and have respective lateral sides exposed outside the molded package structure (12) along the third side; and a second set the first leads (2) are spaced apart from one another along the second direction and have respective lateral sides exposed outside the molded package structure (12) along the fourth side (see Par.[0105]-[0106], [0111], [0122] wherein in suspension leads 4 of individual leadframe 15 as shown in FIGS. 5 and 6, supporting portions 4a are bent away from exposed surfaces 4c of exposed portions 4b; leads 2 and suspension leads 4 of individual leadframes 15 of matrix leadframe 14 are cut at positions that are slightly outside the areas of each of molded sections 12; see Par.[0094], [0114]-[0116] wherein stepped portions 6 (the elevating portions) of supporting portions 4a of suspension leads 4 are placed outside the area of bonding stage 3 shown in FIG. 8. Specifically, processing to elevate the tub (elevation processing) is applied to the respective supporting portions 4a of the four suspension leads 4 outside the area of semiconductor chip 8; stepped portions 6 of supporting portions 4a of suspension leads 4 are formed outside the area of semiconductor chip 8, and not directly below semiconductor chip 8).
With respect to claim 12, Shimanuki discloses, in Figs.1-17, the electronic device, comprising a semiconductor die (8) electrically coupled to one of the first leads (2) and to one of the second leads (2) (see Figs.4(a)-4(b)).
With respect to claim 13, Shimanuki discloses, in Figs.1-17, the electronic device, wherein the second leads (2) have a bottom side exposed outside the molded package structure (12) along the first side, and the second leads (4b, 4c) have a uniform thickness along the third direction (see Figs.2, 4(a)-4(b)).
With respect to claim 14, Shimanuki discloses, in Figs.1-17, the electronic device, wherein the second leads (2) have a nonuniform thickness along the third direction and includes a bottom side half etch pullback feature.
Moreover, regarding the limitation “etch pullback feature”, it is submitted that such limitation does not further define the structure as instantly claimed, nor serve to distinguish over Shimanuki because “etch back” is a controlled process that removes a thin top layer of material to planarize a surface, expose underlying features, or improve bonding. Therefore, it is considerate as “product by process” limitation. Applicant attention is thereby directed to the fact that a "product by process" claim is directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wertheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); In re Marosi et al, 218 USPQ 289; and particularly In re Thorpe, 227 USPQ 964, all of which make it clear that it is the patentability of the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in "product by process" claims or not. Note that Applicant has the burden of proof in such cases, as the above case law make clear.
With respect to claim 15, Shimanuki discloses, in Figs.1-17, the electronic device, wherein the second leads (4b, 4c) have a nonuniform thickness along the third direction and include a top side half etch feature with no pullback (see Figs.2, 4(a)-4(b)).
With respect to claim 20, Shimanuki discloses, in Figs.1-17, a lead frame, comprising: unit areas arranged in an array with rows along a first direction/(cross sectional direction cutting between opposing leads 2 of horizontal/vertical sides and orthogonal to side of 4b-c) and columns along an orthogonal second direction/(B-B, E-E or G-G cross sectional direction), the respective unit areas having a die attach pad (5a), prospective first leads (2) along two opposite lateral sides of the unit area that are spaced apart from one another along the first direction/(cross sectional direction cutting between opposing leads 2 of horizontal/vertical sides and orthogonal to side of 4b-c), and prospective second leads (4b, 4c) along two opposite lateral ends of the unit area that are spaced apart from one another along the second direction/(B-B, E-E or G-G cross sectional direction) (see Fig.2, Par.[0083]-[0086] wherein a section of each of leads 2, which are used as terminals for external connection, is exposed in the peripheral region of back surface 12a (surface on which the semiconductor device is mounted) of the molded section (resin) of said semiconductor device; see Par.[0091] wherein Supporting portions 4a of suspension leads 4 are bent away from exposed surfaces 4c of exposed portions 4b (i.e., in the direction of the surface that is opposite back surface 12a of molded section 12 of QFN1)); first tie bars (15) connected to the prospective first leads (2) of the unit areas along a column of the array; second tie bars (6) connected to the prospective second leads (4) along adjacent rows of the array; and third tie bars (6) connected between the die attach pad (5a) and an adjacent one of the second tie bars (6) of the unit areas along the column of the array (see Par.[0105]-[0106], [0111], [0122] wherein in suspension leads 4 of individual leadframe 15 as shown in FIGS. 5 and 6, supporting portions 4a are bent away from exposed surfaces 4c of exposed portions 4b; leads 2 and suspension leads 4 of individual leadframes 15 of matrix leadframe 14 are cut at positions that are slightly outside the areas of each of molded sections 12; see Par.[0094], [0114]-[0116] wherein stepped portions 6 (the elevating portions) of supporting portions 4a of suspension leads 4 are placed outside the area of bonding stage 3 shown in FIG. 8. Specifically, processing to elevate the tub (elevation processing) is applied to the respective supporting portions 4a of the four suspension leads 4 outside the area of semiconductor chip 8; stepped portions 6 of supporting portions 4a of suspension leads 4 are formed outside the area of semiconductor chip 8, and not directly below semiconductor chip 8; see Par.[0095]-[0096] wherein tub 5 has chip-supporting surface 5a that is smaller than semiconductor chip 8. Tub 5 of embodiment 1 is of the cross type, where chip-supporting surface 5a forms a cross, and is also referred to as a small tub).
Claims 16-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Suzuhara (US 2022/0254704 A1).
With respect to claim 16, Suzuhara discloses, in Figs.1A-15B, a method of fabricating an electronic device, the method comprising: mounting a semiconductor die (116) in a unit area of a lead frame (102) (see Par.[0082]-[0083] wherein regarding a method for manufacturing the semiconductor package 100, the plurality of external connection terminals 114 are cut out from a lead frame 102 on which the die pad 104 is provided, and therefore, are formed of the same material as that of the die pad 104; the semiconductor chip 116 is located on a top surface of the die pad 104 and is electrically connected with the plurality of external connection terminals 114); electrically connecting the semiconductor die (116) to prospective first leads (114) along two opposite lateral sides of the unit area that are spaced apart from one another along a first direction/(vertical direction); electrically connecting the semiconductor die (116) to prospective second leads (114) along two opposite lateral ends of the unit area that are spaced apart from one another along a second direction/(horizontal direction) that is orthogonal to the first direction; forming a molded package structure (120) that extends through multiple unit areas along a column of the lead frame (102), exposes portions of the prospective first leads (114) in the unit area, and encloses the prospective second leads (114) in the unit area (see Par.[0075]-[0077], [0086] wherein FIG. 3A shows the semiconductor package 100 with a part of a sealing member 120 being cut off in order to show a semiconductor chip 116 and the like sealed therein); separating the column from an adjacent second column of the lead frame (102) along the second direction to form first leads (114) along the two opposite lateral sides of the unit area (see Par.[0120] wherein the grooves 100a are formed that separate the plurality of external connection terminals 114 and the second coupling portion 108 from the bottom surface 102b of the lead frame 102 (FIG. 5O, FIG. 5P, FIG. 5Q and FIG. 5R)); and separating an electronic device of the unit area from the lead frame (102) along the first direction to cut through the molded package structure (120) and the prospective second leads to form second leads along the two opposite lateral ends of the unit area (see Par.[0122]-[0123], [0148] wherein he plurality of semiconductor packages 200 are separated from each other by a die process. Concurrently, the plurality of external connection terminals 114 are separated from each other such that each of the plurality of external connection terminals 114 includes, in a side surface thereof, a part of the side wall of the first opening 106a).
With respect to claim 17, Suzuhara discloses, in Figs.1A-15B, the method, wherein the lead frame (102) has a thickness of 0.1 mm or more and 3.0 mm or less (see Par.[0093] wherein the thickness of the lead frame 102 corresponds to the thickness of the metal plate, and is 100 μm or greater and 600 μm or less; the lead frame 102 has a thickness of 200 μm), and separating the column from an adjacent second column of the lead frame (102) includes performing a punching process that forms the first leads along the two opposite lateral sides of the unit area (see Par.[0095] wherein the metal plate may be subjected to a process including etching or punching performed by use of a die, to be formed into the lead frame 102 described below; see Par.[0136] wherein the metal plate may be subjected to a process including etching or punching performed by use of a die, to be formed into the lead frame 202 described below).
With respect to claim 18, Suzuhara discloses, in Figs.1A-15B, the method, wherein separating an electronic device of the unit area from the lead frame includes performing a saw or laser cutting process that cuts through the molded package structure and the prospective second leads to form the second leads along the two opposite lateral ends of the unit area (see Par.[0149] wherein the cutting (e.g.; saw cutting or laser cutting) is performed along a pattern 200a shown in FIG. 9I).
With respect to claim 20, Suzuhara discloses, in Figs.1A-15B, a lead frame, comprising: unit areas arranged in an array with rows along a first direction/(vertical direction) and columns along an orthogonal second direction/(horizontal direction), the respective unit areas having a die attach pad (104), prospective first leads (114) along two opposite lateral sides of the unit area that are spaced apart from one another along the first direction, and prospective second leads (114) along two opposite lateral ends of the unit area that are spaced apart from one another along the second direction (see Fig.12A wherein a portion of matrix arrangement of package unit areas are shown; see Par.[0082]-[0083] wherein regarding a method for manufacturing the semiconductor package 100, the plurality of external connection terminals 114 are cut out from a lead frame 102 on which the die pad 104 is provided, and therefore, are formed of the same material as that of the die pad 104; the semiconductor chip 116 is located on a top surface of the die pad 104 and is electrically connected with the plurality of external connection terminals 114); first tie bars (106) connected to the prospective first leads (114) of the unit areas along a column of the array; second tie bars (106) connected to the prospective second leads (114) along adjacent rows of the array; and third tie bars (108) connected between the die attach pad and an adjacent one of the second tie bars of the unit areas along the column of the array (see Fig.9C, Par.[0117]-[0118] wherein a part of the top surface 114a of each of the plurality of external connection terminals 114, the top surface of the first coupling portion 106, the bottom surface of the die pad 104, the side surface 114c of the outer terminal 114e of each of the plurality of external connection terminals 114, the bottom surface 114b of each of the plurality of external connection terminals 114, the bottom surface of the first coupling portion 106, and the bottom surface of the second coupling portion 108 are exposed).
Claims 16, 18, 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Hanasaka et al. (US 2024/0371658 A1 hereinafter referred to as “Hanasaka”).
With respect to claim 16, Hanasaka discloses, in Figs.1-16, a method of fabricating an electronic device, the method comprising: mounting a semiconductor die (6) in a unit area of a lead frame (1) (see Par.[0026]-[0029] wherein the lead frame 1 has a front surface 1a on which a semiconductor chip 6 (FIGS. 5 and 6) is mounted, and a back surface 1b opposite the front surface 1a); electrically connecting the semiconductor die (6) to prospective first leads (3) along two opposite lateral sides of the unit area that are spaced apart from one another along a first direction (A1); electrically connecting the semiconductor die (6) to prospective second leads (3) along two opposite lateral ends of the unit area that are spaced apart from one another along a second direction that is orthogonal to the first direction (see Par.[0030]-[0032] wherein tie bar portions 4a and 4b are arranged in a grid shape surrounding each of the die pads 2; the tie bar portion 4a extends substantially in parallel with the first direction A1; the tie bar portion 4b extends substantially in parallel with the second direction A2; the respective thicker portions 3a of the lead portions 3 arranged along the first direction A1 are coupled to the tie bar portions 4a via the thinner portions 3b); forming a molded package structure (9) that extends through multiple unit areas along a column of the lead frame (1), exposes portions/(at least exposed side area of lead 3) of the prospective first leads (3) in the unit area, and encloses the prospective second leads (3) in the unit area; separating the column from an adjacent second column of the lead frame along the second direction (A2) to form first leads along the two opposite lateral sides of the unit area (see Fig.5 wherein matrix arrangements od unit areas are shown); and separating an electronic device of the unit area from the lead frame along the first direction to cut through the molded package structure and the prospective second leads to form second leads along the two opposite lateral ends of the unit area (see Par.[0042]-[0044] wherein As described below in detail, the semiconductor device manufacturing method according to the embodiment further includes a cutting step (see FIG. 12)).
With respect to claim 18, Hanasaka discloses, in Figs.1-16, the method of claim 17, wherein separating an electronic device of the unit area from the lead frame includes performing a saw or laser cutting process that cuts through the molded package structure and the prospective second leads to form the second leads along the two opposite lateral ends of the unit area (see Par.[0044], [0057] wherein the cutting step, for example, a portion of the lead frame 1 having the total thickness and a portion of the resin material 9 having the total thickness are cut with the blade (e.g.; saw blade) 13 having a width W2 (FIG. 12)).
With respect to claim 20, Hanasaka discloses, in Figs.1-16, a lead frame, comprising: unit areas arranged in an array with rows along a first direction and columns along an orthogonal second direction, the respective unit areas having a die attach pad (2(1)), prospective first leads (3) along two opposite lateral sides of the unit area that are spaced apart from one another along the first direction, and prospective second leads (3) along two opposite lateral ends of the unit area that are spaced apart from one another along the second direction (see Par.[0047] wherein FIG. 6 is a cross-sectional arrow view of the lead frame 1 along VI-VI line of FIG. 5 in which the semiconductor chips 6 are bonded on the die pads 2 of the lead frame 1; (see Par.[0030]-[0032] wherein tie bar portions 4a and 4b are arranged in a grid shape surrounding each of the die pads 2; the tie bar portion 4a extends substantially in parallel with the first direction A1; the tie bar portion 4b extends substantially in parallel with the second direction A2; the respective thicker portions 3a of the lead portions 3 arranged along the first direction A1 are coupled to the tie bar portions 4a via the thinner portions 3b); see Fig.5 wherein matrix arrangements od unit areas are shown); first tie bars (4a) connected to the prospective first leads (3) of the unit areas along a column of the array; second tie bars (4b) connected to the prospective second leads along adjacent rows of the array; and third tie bars (1a) connected between the die attach pad and an adjacent one of the second tie bars of the unit areas along the column of the array (see Par.[0030]-[0032] wherein the die pad 2 is an area where a semiconductor chip 6 is mounted on the front surface 1a of the die pad 2 (see FIG. 6); tie bar portions 4a and 4b are arranged in a grid shape surrounding each of the die pads 2; the tie bar portion 4a extends substantially in parallel with the first direction A1; the tie bar portion 4b extends substantially in parallel with the second direction A2; the respective thicker portions 3a of the lead portions 3 arranged along the first direction A1 are coupled to the tie bar portions 4a via the thinner portions 3b).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Suzuhara.
With respect to claim 19, Suzuhara discloses, in Figs.1A-15B, the method, wherein: the electronic device has a package size; the electronic device has a package thickness of 0.25 mm or more and 5.0 mm or less; and separating an electronic device of the unit area from the lead frame includes performing a saw or laser cutting process that cuts through the molded package structure and the prospective second leads to form the second leads along the two opposite lateral ends of the unit area (see Par.[0149] wherein the cutting (e.g.; saw cutting or laser cutting) is performed along a pattern 200a shown in FIG. 9I; see Par.[0093] wherein the thickness of the lead frame 102 corresponds to the thickness of the metal plate, and is 100 μm or greater and 600 μm or less; the lead frame 102 has a thickness of 200 μm). However, Suzuhara does not explicitly disclose the electronic device has a package size of 1.2 mm x 1.2 mm or more and 20 mm x 20 mm or less; the electronic device has a package thickness of 0.25 mm or more and 5.0 mm or less.
Even though Suzuhara does not disclose the electronic device has a package size of 1.2 mm x 1.2 mm or more and 20 mm x 20 mm or less; the electronic device has a package thickness of 0.25 mm or more and 5.0 mm or less, the said range is predictable by simple engineering optimization motivated by a design choice, such as, level of package miniaturization. In cases like the present, where patentability is said to be based upon particular chosen dimensions or upon another variable recited within the claims, applicant must show that the chosen dimensions are critical. As such, the claimed dimensions appear to be an obvious matter of engineering design choice and thus, while being a difference, does not serve in any way to patentably distinguish the claimed invention from the applied prior art. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990); In re Kuhle, 526 F2d. 553,555,188 USPQ 7, 9 (CCPA 1975).
Response to Arguments
Applicant’s arguments with respect to claims 1, 16, 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Citation of Pertinent Prior Art
The prior art made of record (see PTO-892) and not relied upon is considered pertinent to applicant's disclosure.
Examiner’s Telephone/Fax Contacts
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOULOUCOULAYE INOUSSA whose telephone number is (571)272-0596. The examiner can normally be reached Monday-Friday (10-18).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JEFF W NATALINI can be reached at 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Mouloucoulaye Inoussa/ Primary Examiner, Art Unit 2818
Prosecution Insights