Prosecution Insights
Last updated: April 19, 2026
Application No. 18/494,075

LIGHT-EMITTING DIODE, LIGHT-EMITTING DEVICE INCLUDING THE SAME, AND METHOD FOR MANUFACTURING LIGHT-EMITTING DIODE

Non-Final OA §102§103
Filed
Oct 25, 2023
Examiner
INOUSSA, MOULOUCOULAY
Art Unit
2818
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Tianjin Sanan Optoelectronics Co., Ltd.
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
2y 6m
To Grant
93%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allow Rate
645 granted / 752 resolved
+17.8% vs TC avg
Moderate +7% lift
Without
With
+7.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
36 currently pending
Career history
788
Total Applications
across all art units

Statute-Specific Performance

§101
2.1%
-37.9% vs TC avg
§103
38.3%
-1.7% vs TC avg
§102
41.4%
+1.4% vs TC avg
§112
18.0%
-22.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 752 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-4, 7-8, 11-12, 15-16, 19-21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ito (US 2020/0119230 A1). With respect to claim 1, Ito discloses, in Figs.1-28, a light-emitting diode, comprising: an epitaxial structure (7) having a first surface/(upper surface of 7) and a second surface/(lower surface of 7) opposite to said first surface, said epitaxial structure (7) including, along a direction from said first surface/(upper surface of 7) to said second surface/(lower surface of 7), a first-type/(n-type) semiconductor layer (18-20), a light-emitting layer (12) and a second-type/(p-type) semiconductor layer (17) in such order, said first-type semiconductor layer (18-20) including an ohmic contact layer (interface between 19-20) which at least partially defines said first surface/(upper surface 7) of said epitaxial structure (7); and a first metal electrode (11) formed on said first surface of said epitaxial structure (7), and including a main electrode (24) and a plurality of auxiliary electrodes (25), said auxiliary electrodes (25) being formed on said ohmic contact layer (19) opposite to said light-emitting layer (12) and being electrically connected to said ohmic contact layer (19), wherein said ohmic contact layer (19) is made of an indium phosphide-based material of AlxGayInP, where 0≤x≤1 or 0≤y≤1, and wherein in a top view of said light-emitting diode, a projection of each of said auxiliary electrodes (25) on said first surface is smaller than or equal to a projection of said ohmic contact layer (19) on said first surface (see Par.[0078] wherein the compound semiconductor layer 7 is an epitaxial layer formed by an epitaxial growth method; see Par.[0079]-[0081] wherein a p-type cladding layer 17 (having a thickness of, e.g., 0.1 μm to 2.5 μm) sequentially from the side of the substrate 2; on the other hand, the n-type semiconductor layer 14 is formed by stacking an n-type cladding layer 18 (having a thickness of, e.g., 0.1 μm to 2.5 μm), an n-type window layer 19 (having a thickness of, e.g., 2.0 μm to 5.0 μm) as an example of the second layer of the present disclosure and an n-type contact layer 20 (having a thickness of, e.g., 0.1 μm to 2.5 μm) as an example of the first layer of the present disclosure sequentially on the light-emitting layer 12; the n-type window layer 19 may be formed as an n-type semiconductor layer by doping AlInGaP with, for example, Si as an n-type dopant; the p-type contact layer 15 and the n-type contact layer 20 are low resistance layers for making ohmic contact with the light-transmitting conductive layer 6 and the cathode electrode layer 11, respectively; as such the interface contact between 19 and 20 is of ohmic contact; see Figs.2 wherein projections of electrode portions on first surface is smaller than or equal to that of ohmic contact layer). With respect to claim 2, Ito discloses, in Figs.1-28, the light-emitting diode, wherein said ohmic contact layer (19) has a surrounding surface that is not covered by said auxiliary electrodes (25) (see Figs.1-2, wherein there are areas of layer 19 around ohmic electrode 11). With respect to claim 3, Ito discloses, in Figs.1-28, the light-emitting diode, wherein said first surface of said epitaxial structure (7) has a first portion defined by said ohmic contact layer (19) and a second portion not covered by said ohmic contact layer, said main electrode being formed on said first portion of said first surface or on said second portion of said first surface (see Figs.1-2, wherein there are areas of layer 19 around ohmic electrode 11). With respect to claim 4, Ito discloses, in Figs.1-28, the light-emitting diode, wherein said first metal electrode includes at least three metals selected from the group consisting of gold, germanium, nickel, and alloys thereof, said first metal electrode having a nickel content that first increases and then decreases along a direction from a bottom surface of said first metal electrode adjacent to said first surface of said epitaxial structure to a top surface of said first metal electrode opposite to said bottom surface (see Par.[0138] wherein it was verified how the increase rate of the forward voltage (VF) of the semiconductor light emitting device 1 is changed depending on the thickness of the Ni layer 55, the thickness of the AuGe layer 54 and the Ni content ratio with respect to the entire cathode electrode layer 11 (AuGe/Ni). FIG. 18 is a view showing the relationship between the thickness of the Ni layer 55 and the VF increase rate. FIG. 19 is a view showing the relationship between the thickness of the AuGe layer 54 and the VF increase rate. FIG. 20 is a view showing the relationship between the Ni content ratio with respect to AuGe/Ni and the VF increase rate; see Fig.20 wherein the Ni content decreased (from 20wt% to 42wt%) then increased (from 42wt% to 80wt%) with respect to AuGe within thickness of the electrode). With respect to claim 7, Ito discloses, in Figs.1-28, the light-emitting diode, wherein said ohmic contact layer includes nickel/(ohmic contact interface includes Ni) (see Par.[0138] wherein it was verified how the increase rate of the forward voltage (VF) of the semiconductor light emitting device 1 is changed depending on the thickness of the Ni layer 55, the thickness of the AuGe layer 54 and the Ni content ratio with respect to the entire cathode electrode layer 11 (AuGe/Ni). FIG. 18 is a view showing the relationship between the thickness of the Ni layer 55 and the VF increase rate. FIG. 19 is a view showing the relationship between the thickness of the AuGe layer 54 and the VF increase rate. FIG. 20 is a view showing the relationship between the Ni content ratio with respect to AuGe/Ni and the VF increase rate; see Fig.20 wherein the Ni content decreased (from 20wt% to 42wt%) then increased (from 42wt% to 80wt%) with respect to AuGe within thickness of the electrode). With respect to claim 8, Ito discloses, in Figs.1-28, the light-emitting diode, wherein said first-type semiconductor layer further includes at least one window layer (19) which is disposed on said ohmic contact layer opposite to said first metal electrode, and which is made of an indium phosphide-based material of AlmGanInP, where 0≤m≤1 or 0≤n≤1, said ohmic contact layer having an Al content that is less than an Al content of said window layer (see Par.[0078] wherein the compound semiconductor layer 7 is an epitaxial layer formed by an epitaxial growth method; see Par.[0079]-[0081] wherein a p-type cladding layer 17 (having a thickness of, e.g., 0.1 μm to 2.5 μm) sequentially from the side of the substrate 2; on the other hand, the n-type semiconductor layer 14 is formed by stacking an n-type cladding layer 18 (having a thickness of, e.g., 0.1 μm to 2.5 μm), an n-type window layer 19 (having a thickness of, e.g., 2.0 μm to 5.0 μm) as an example of the second layer of the present disclosure and an n-type contact layer 20 (having a thickness of, e.g., 0.1 μm to 2.5 μm) as an example of the first layer of the present disclosure sequentially on the light-emitting layer 12; the n-type window layer 19 may be formed as an n-type semiconductor layer by doping AlInGaP with, for example, Si as an n-type dopant; the p-type contact layer 15 and the n-type contact layer 20 are low resistance layers for making ohmic contact with the light-transmitting conductive layer 6 and the cathode electrode layer 11, respectively; as such the interface contact between 19 and 20 is of ohmic contact; see Figs.2 wherein projections of electrode portions on first surface is smaller than or equal to that of ohmic contact layer). With respect to claim 11, Ito discloses, in Figs.1-28, the light-emitting diode, wherein a light emitted by said light-emitting diode has a wavelength ranging from 550 nm to 750 nm (see Par.[0082] wherein the band gap decreases and the light emission wavelength increases. In the present embodiment, the light emission wavelength is set to 610 nm to 680 nm (e.g., 625 nm) by adjusting the IN composition in the quantum well layer (InGaP layer)). With respect to claim 12, Ito discloses, in Figs.1-28, a light-emitting diode, comprising: an epitaxial structure (7) having a first surface/(upper surface of 7) and a second surface/(lower surface of 7) opposite to said first surface, said epitaxial structure (7) including, along a direction from said first surface to said second surface, a first-type semiconductor layer (18), a light-emitting layer (12) and a second-type semiconductor layer (17) in such order, said first-type semiconductor layer including an ohmic contact layer/(interface 20-19) which at least partially defines said first surface of said epitaxial structure (7); and a first metal electrode (11) formed on said first surface of said epitaxial structure (7), and including a main electrode (24) and a plurality of auxiliary electrodes (250, said auxiliary electrodes being disposed on said ohmic contact layer (19/20) opposite to said light-emitting layer and being electrically connected to said ohmic contact layer, wherein said ohmic contact layer is made of an indium phosphide-based of AlxGayInP, where 0≤x≤1 or 0≤y≤1 (see Par.[0078] wherein the compound semiconductor layer 7 is an epitaxial layer formed by an epitaxial growth method; see Par.[0079]-[0081] wherein a p-type cladding layer 17 (having a thickness of, e.g., 0.1 μm to 2.5 μm) sequentially from the side of the substrate 2; on the other hand, the n-type semiconductor layer 14 is formed by stacking an n-type cladding layer 18 (having a thickness of, e.g., 0.1 μm to 2.5 μm), an n-type window layer 19 (having a thickness of, e.g., 2.0 μm to 5.0 μm) as an example of the second layer of the present disclosure and an n-type contact layer 20 (having a thickness of, e.g., 0.1 μm to 2.5 μm) as an example of the first layer of the present disclosure sequentially on the light-emitting layer 12; the n-type window layer 19 may be formed as an n-type semiconductor layer by doping AlInGaP with, for example, Si as an n-type dopant; the p-type contact layer 15 and the n-type contact layer 20 are low resistance layers for making ohmic contact with the light-transmitting conductive layer 6 and the cathode electrode layer 11, respectively; as such the interface contact between 19 and 20 is of ohmic contact; see Figs.2 wherein projections of electrode portions on first surface is smaller than or equal to that of ohmic contact layer), and wherein said first metal electrode (11) includes at least three metals selected from the group consisting of gold, germanium, nickel, and alloys thereof, said first metal electrode having a nickel content that first increases and then decreases along a direction from a bottom surface of said first metal electrode adjacent to said first surface of said epitaxial structure to a top surface of said first metal electrode opposite to said bottom surface (see Par.[0138] wherein it was verified how the increase rate of the forward voltage (VF) of the semiconductor light emitting device 1 is changed depending on the thickness of the Ni layer 55, the thickness of the AuGe layer 54 and the Ni content ratio with respect to the entire cathode electrode layer 11 (AuGe/Ni). FIG. 18 is a view showing the relationship between the thickness of the Ni layer 55 and the VF increase rate. FIG. 19 is a view showing the relationship between the thickness of the AuGe layer 54 and the VF increase rate. FIG. 20 is a view showing the relationship between the Ni content ratio with respect to AuGe/Ni and the VF increase rate; see Fig.20 wherein the Ni content decreased (from 20wt% to 42wt%) then increased (from 42wt% to 80wt%) with respect to AuGe within thickness of the electrode). With respect to claim 15, Ito discloses, in Figs.1-28, the light-emitting diode, wherein said ohmic contact layer includes nickel/(ohmic contact interface includes Ni) (see Par.[0138] wherein it was verified how the increase rate of the forward voltage (VF) of the semiconductor light emitting device 1 is changed depending on the thickness of the Ni layer 55, the thickness of the AuGe layer 54 and the Ni content ratio with respect to the entire cathode electrode layer 11 (AuGe/Ni). FIG. 18 is a view showing the relationship between the thickness of the Ni layer 55 and the VF increase rate. FIG. 19 is a view showing the relationship between the thickness of the AuGe layer 54 and the VF increase rate. FIG. 20 is a view showing the relationship between the Ni content ratio with respect to AuGe/Ni and the VF increase rate; see Fig.20 wherein the Ni content decreased (from 20wt% to 42wt%) then increased (from 42wt% to 80wt%) with respect to AuGe within thickness of the electrode). With respect to claim 16, Ito discloses, in Figs.1-28, the light-emitting diode, wherein said first-type semiconductor layer further includes at least one window layer which is disposed on said ohmic contact layer opposite to said first metal electrode, and which is made of an indium phosphide-based material of AlmGanInP, where 0≤m≤1 or 0≤n≤1, said ohmic contact layer having an Al content that is less than an Al content of said window layer (see Par.[0078] wherein the compound semiconductor layer 7 is an epitaxial layer formed by an epitaxial growth method; see Par.[0079]-[0081] wherein a p-type cladding layer 17 (having a thickness of, e.g., 0.1 μm to 2.5 μm) sequentially from the side of the substrate 2; on the other hand, the n-type semiconductor layer 14 is formed by stacking an n-type cladding layer 18 (having a thickness of, e.g., 0.1 μm to 2.5 μm), an n-type window layer 19 (having a thickness of, e.g., 2.0 μm to 5.0 μm) as an example of the second layer of the present disclosure and an n-type contact layer 20 (having a thickness of, e.g., 0.1 μm to 2.5 μm) as an example of the first layer of the present disclosure sequentially on the light-emitting layer 12; the n-type window layer 19 may be formed as an n-type semiconductor layer by doping AlInGaP with, for example, Si as an n-type dopant; the p-type contact layer 15 and the n-type contact layer 20 are low resistance layers for making ohmic contact with the light-transmitting conductive layer 6 and the cathode electrode layer 11, respectively; as such the interface contact between 19 and 20 is of ohmic contact; see Figs.2 wherein projections of electrode portions on first surface is smaller than or equal to that of ohmic contact layer). With respect to claim 19, Ito discloses, in Figs.1-28, a light-emitting device, comprising a light-emitting diode (see Par.[0073] wherein LED 1 is shown). With respect to claim 20, Ito discloses, in Figs.1-28, a method for manufacturing a light-emitting diode, comprising: sequentially forming a light-emitting layer (18) and a second-type semiconductor layer (17) on a first-type semiconductor layer, so as to obtain an epitaxial structure (7) having a first surface and a second surface opposite to the first surface, the first-type semiconductor layer including an ohmic contact layer/(interface 19-20) which at least partially defines the first surface of the epitaxial structure; forming a main electrode (24) on the first surface of the epitaxial structure; and forming a plurality of auxiliary electrodes (25) on the ohmic contact layer, wherein the ohmic contact layer is made of an indium phosphide-based material of AlxGayInP, where 0≤x≤1 or 0≤y≤1, and wherein in a top view of the light-emitting diode, a projection of each of the auxiliary electrodes on the first surface is smaller than or equal to a projection of the ohmic contact layer on the first surface (see Par.[0078] wherein the compound semiconductor layer 7 is an epitaxial layer formed by an epitaxial growth method; see Par.[0079]-[0081] wherein a p-type cladding layer 17 (having a thickness of, e.g., 0.1 μm to 2.5 μm) sequentially from the side of the substrate 2; on the other hand, the n-type semiconductor layer 14 is formed by stacking an n-type cladding layer 18 (having a thickness of, e.g., 0.1 μm to 2.5 μm), an n-type window layer 19 (having a thickness of, e.g., 2.0 μm to 5.0 μm) as an example of the second layer of the present disclosure and an n-type contact layer 20 (having a thickness of, e.g., 0.1 μm to 2.5 μm) as an example of the first layer of the present disclosure sequentially on the light-emitting layer 12; the n-type window layer 19 may be formed as an n-type semiconductor layer by doping AlInGaP with, for example, Si as an n-type dopant; the p-type contact layer 15 and the n-type contact layer 20 are low resistance layers for making ohmic contact with the light-transmitting conductive layer 6 and the cathode electrode layer 11, respectively; as such the interface contact between 19 and 20 is of ohmic contact; see Figs.2 wherein projections of electrode portions on first surface is smaller than or equal to that of ohmic contact layer). With respect to claim 21, Ito discloses, in Figs.1-28, the method, wherein the main electrode is formed on one of a first portion of the first surface which is defined by the ohmic contact layer and a second portion of the first surface of the epitaxial structure which is not covered by the ohmic contact layer (see Figs.1-2). Claims 1-3, 7, 20-21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yamamoto et al. (US 2020/0381589 A1 hereinafter referred to as “Yamamoto”). With respect to claim 1, Yamamoto discloses, in Figs.1-10B, a light-emitting diode, comprising: an epitaxial structure (30) having a first surface/(upper surface of 30) and a second surface/(lower surface of 30) opposite to said first surface, said epitaxial structure (30) including, along a direction from said first surface to said second surface, a first-type semiconductor layer (31), a light-emitting layer (35) and a second-type semiconductor layer (37) in such order, said first-type semiconductor layer including an ohmic contact layer (10, 20) which at least partially defines said first surface of said epitaxial structure (30), and a first metal electrode (93) formed on said first surface of said epitaxial structure (30), and including a main electrode (93b) and a plurality of auxiliary electrodes/(branches electrodes) (93a), said auxiliary electrodes being formed on said ohmic contact layer (20A) opposite to said light-emitting layer (35) and being electrically connected to said ohmic contact layer (20A), wherein said ohmic contact layer (20A) is made of an indium phosphide-based material of AlxGayInP, where 0≤x≤1 or 0≤y≤1, and wherein in a top view of said light-emitting diode, a projection of each of said auxiliary electrodes on said first surface is smaller than or equal to a projection of said ohmic contact layer on said first surface (see Par.[0055]-[0058] wherein an n-type InGaAs contact layer 20 is formed on an n-type InP growth substrate 10 resulting of InGaAsP or InP-As based material (i.e.; AlxGayInP when x=0; y=1) compound 20A; see Par.[0061]-[0066] wherein the n-type InGaAs and IP contact layers 20, 10 formed in the first step and the layers in the semiconductor laminate 30 formed in the second step can be formed by epitaxial growth, for example by a well-known thin film deposition technique such as metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or sputtering; the semiconductor laminate 30 may include an n-type cladding layer 31, active layers 35, and a p-type cladding layer 37 in this order, and each of these layers is formed as a layer made of InGaAsP-based III-V group compound semiconductor containing at least In and P; see Par.[0077] wherein the n-side electrode 93, particularly the wiring portion 93a preferably contains Au and Ge, or preferably contains Ti, Pt, and Au; the n-side electrode 93 containing these metallic elements ensures an ohmic contact with the n-type InGaAs contact layer 20A); and a first metal electrode (93) formed on said first surface of said epitaxial structure (30), and including a main electrode and a plurality of auxiliary electrodes/(branches electrodes), said auxiliary electrodes being formed on said ohmic contact layer (20A) opposite to said light-emitting layer (35) and being electrically connected to said ohmic contact layer (20A; see Par.[0112] wherein electrode (Au (thickness: 10 nm)/Ge (thickness: 33 nm)/Au (thickness: 57 nm)/Ni (thickness: 34 nm)/Au (thickness: 800 nm); a pad portion 93b (Ti (thickness: 150 nm)/Pt (thickness: 100 nm)/Au (thickness: 2500 nm)) was formed at the center portion of the n-side electrode to obtain the n-side electrode having a pattern as illustrated in FIG. 10B) was formed as a wiring portion 93a; see Figs.4, 10B, wherein projections of electrode portions on first surface is smaller than or equal to that of ohmic contact layer). With respect to claim 2, Yamamoto discloses, in Figs.1-10B, the light-emitting diode, wherein said ohmic contact layer (20A) has a surrounding surface that is not covered by said auxiliary electrodes (see Figs.4, 10B wherein layer 20A auxiliaries’ branches surround main electrode below which layer 20A is disposed). With respect to claim 3, Yamamoto discloses, in Figs.1-10B, the light-emitting diode, wherein said first surface of said epitaxial structure (30) has a first portion defined by said ohmic contact layer (20A) and a second portion not covered by said ohmic contact layer (20A), said main electrode (93b) being formed on said first portion of said first surface or on said second portion of said first surface (see Figs.4, 10B). With respect to claim 7, Yamamoto discloses, in Figs.1-10B, the light-emitting diode, wherein said ohmic contact layer includes nickel/(interface ohmic contact includes Ni material) (see Par.[0077] wherein the n-side electrode 93, particularly the wiring portion 93a preferably contains Au and Ge, or preferably contains Ti, Pt, and Au; the n-side electrode 93 containing these metallic elements ensures an ohmic contact with the n-type InGaAs contact layer 20A); and a first metal electrode (93) formed on said first surface of said epitaxial structure (30), and including a main electrode and a plurality of auxiliary electrodes/(branches electrodes), said auxiliary electrodes being formed on said ohmic contact layer (20A) opposite to said light-emitting layer (35) and being electrically connected to said ohmic contact layer (20A; see Par.[0112] wherein electrode (Au (thickness: 10 nm)/Ge (thickness: 33 nm)/Au (thickness: 57 nm)/Ni (thickness: 34 nm)/Au (thickness: 800 nm); a pad portion 93b (Ti (thickness: 150 nm)/Pt (thickness: 100 nm)/Au (thickness: 2500 nm)) was formed at the center portion of the n-side electrode to obtain the n-side electrode having a pattern as illustrated in FIG. 10B) was formed as a wiring portion 93a). With respect to claim 20, Yamamoto discloses, in Figs.1-10B, a method for manufacturing a light-emitting diode, comprising: sequentially forming a light-emitting layer (31) and a second-type semiconductor layer (37) on a first-type semiconductor layer, so as to obtain an epitaxial structure (30) having a first surface and a second surface opposite to the first surface, the first-type semiconductor layer including an ohmic contact layer (20A) which at least partially defines the first surface of the epitaxial structure; forming a main electrode (93b) on the first surface of the epitaxial structure; and forming a plurality of auxiliary electrodes (93a) on the ohmic contact layer, wherein the ohmic contact layer is made of an indium phosphide-based material of AlxGayInP, where 0≤x≤1 or 0≤y≤1, and wherein in a top view of the light-emitting diode, a projection of each of the auxiliary electrodes on the first surface is smaller than or equal to a projection of the ohmic contact layer on the first surface (see Par.[0055]-[0058] wherein an n-type InGaAs contact layer 20 is formed on an n-type InP growth substrate 10 resulting of InGaAsP or InP-As based material (i.e.; AlxGayInP when x=0; y=1) compound 20A; see Par.[0061]-[0066] wherein the n-type InGaAs and IP contact layers 20, 10 formed in the first step and the layers in the semiconductor laminate 30 formed in the second step can be formed by epitaxial growth, for example by a well-known thin film deposition technique such as metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or sputtering; the semiconductor laminate 30 may include an n-type cladding layer 31, active layers 35, and a p-type cladding layer 37 in this order, and each of these layers is formed as a layer made of InGaAsP-based III-V group compound semiconductor containing at least In and P; see Par.[0077] wherein the n-side electrode 93, particularly the wiring portion 93a preferably contains Au and Ge, or preferably contains Ti, Pt, and Au; the n-side electrode 93 containing these metallic elements ensures an ohmic contact with the n-type InGaAs contact layer 20A); and a first metal electrode (93) formed on said first surface of said epitaxial structure (30), and including a main electrode and a plurality of auxiliary electrodes/(branches electrodes), said auxiliary electrodes being formed on said ohmic contact layer (20A) opposite to said light-emitting layer (35) and being electrically connected to said ohmic contact layer (20A; see Par.[0112] wherein electrode (Au (thickness: 10 nm)/Ge (thickness: 33 nm)/Au (thickness: 57 nm)/Ni (thickness: 34 nm)/Au (thickness: 800 nm); a pad portion 93b (Ti (thickness: 150 nm)/Pt (thickness: 100 nm)/Au (thickness: 2500 nm)) was formed at the center portion of the n-side electrode to obtain the n-side electrode having a pattern as illustrated in FIG. 10B) was formed as a wiring portion 93a; see Figs.4, 10B, wherein projections of electrode portions on first surface is smaller than or equal to that of ohmic contact layer). With respect to claim 21, Ito discloses, in Figs.1-28, the method, wherein the main electrode is formed on one of a first portion of the first surface which is defined by the ohmic contact layer and a second portion of the first surface of the epitaxial structure which is not covered by the ohmic contact layer (see Figs.4, 10B). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 5-6, 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Ito in view of Yamamoto. With respect to claim 5, Ito discloses all the claimed limitations of claim 4. However, Ito does not explicitly disclose the limitations of claim 5. Yamamoto discloses, in Figs.1-10B, the light-emitting diode, wherein said first metal electrode further includes titanium and platinum, the titanium being distributed closer to said ohmic contact layer than the platinum, the platinum being distributed immediately adjacent to the titanium (see Par.[0077] wherein the n-side electrode 93, particularly the wiring portion 93a preferably contains Au and Ge, or preferably contains Ti, Pt, and Au; the n-side electrode 93 containing these metallic elements ensures an ohmic contact with the n-type InGaAs contact layer 20A); and a first metal electrode (93) formed on said first surface of said epitaxial structure (30), and including a main electrode and a plurality of auxiliary electrodes/(branches electrodes), said auxiliary electrodes being formed on said ohmic contact layer (20A) opposite to said light-emitting layer (35) and being electrically connected to said ohmic contact layer (20A; see Par.[0112] wherein electrode (Au (thickness: 10 nm)/Ge (thickness: 33 nm)/Au (thickness: 57 nm)/Ni (thickness: 34 nm)/Au (thickness: 800 nm); a pad portion 93b (Ti (thickness: 150 nm)/Pt (thickness: 100 nm)/Au (thickness: 2500 nm)) was formed at the center portion of the n-side electrode to obtain the n-side electrode having a pattern as illustrated in FIG. 10B) was formed as a wiring portion 93a). Ito and Yamamoto are analogous art because they are all directed to a LED, and one of ordinary skill in the art would have had a reasonable expectation of success by modifying Ito to include Yamamoto because they are from the same field of endeavor. Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the electrode material in Ito by including Ti/Pt/Au/Ge/Ni as taught by Yamamoto in order to utilize the additional Ti/Pt properties such as excellent chemical stability, high current efficiency, low hydrogen evolution potential, and a long operational lifespan thereby providing electrode with corrosion resistance, high catalytic activities, excellent electrical conductivity, structure integrity for enhance overall device performance. With respect to claim 6, Yamamoto discloses, in Figs.1-10B, the light-emitting diode, wherein the titanium in said first metal electrode forms a titanium-containing layer having a thickness of greater than 800 angstroms (Å) (see Par.[0077] wherein the n-side electrode 93, particularly the wiring portion 93a preferably contains Au and Ge, or preferably contains Ti, Pt, and Au; the n-side electrode 93 containing these metallic elements ensures an ohmic contact with the n-type InGaAs contact layer 20A); and a first metal electrode (93) formed on said first surface of said epitaxial structure (30), and including a main electrode and a plurality of auxiliary electrodes/(branches electrodes), said auxiliary electrodes being formed on said ohmic contact layer (20A) opposite to said light-emitting layer (35) and being electrically connected to said ohmic contact layer (20A; see Par.[0112] wherein electrode (Au (thickness: 10 nm)/Ge (thickness: 33 nm)/Au (thickness: 57 nm)/Ni (thickness: 34 nm)/Au (thickness: 800 nm); a pad portion 93b (Ti (thickness: 150 nm=1500Å)/Pt (thickness: 100 nm)/Au (thickness: 2500 nm)) was formed at the center portion of the n-side electrode to obtain the n-side electrode having a pattern as illustrated in FIG. 10B) was formed as a wiring portion 93a). With respect to claim 13, Ito discloses all the claimed limitations of claim 12. However, Ito does not explicitly disclose the limitations of claim 13. Yamamoto discloses, in Figs.1-10B, the light-emitting diode, wherein said first metal electrode further includes titanium and platinum, the titanium being distributed closer to said ohmic contact layer than the platinum, the platinum being distributed immediately adjacent to the titanium (see Par.[0077] wherein the n-side electrode 93, particularly the wiring portion 93a preferably contains Au and Ge, or preferably contains Ti, Pt, and Au; the n-side electrode 93 containing these metallic elements ensures an ohmic contact with the n-type InGaAs contact layer 20A); and a first metal electrode (93) formed on said first surface of said epitaxial structure (30), and including a main electrode and a plurality of auxiliary electrodes/(branches electrodes), said auxiliary electrodes being formed on said ohmic contact layer (20A) opposite to said light-emitting layer (35) and being electrically connected to said ohmic contact layer (20A; see Par.[0112] wherein electrode (Au (thickness: 10 nm)/Ge (thickness: 33 nm)/Au (thickness: 57 nm)/Ni (thickness: 34 nm)/Au (thickness: 800 nm); a pad portion 93b (Ti (thickness: 150 nm)/Pt (thickness: 100 nm)/Au (thickness: 2500 nm)) was formed at the center portion of the n-side electrode to obtain the n-side electrode having a pattern as illustrated in FIG. 10B) was formed as a wiring portion 93a). Ito and Yamamoto are analogous art because they are all directed to a LED, and one of ordinary skill in the art would have had a reasonable expectation of success by modifying Ito to include Yamamoto because they are from the same field of endeavor. Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the electrode material in Ito by including Ti/Pt/Au/Ge/Ni as taught by Yamamoto in order to utilize the additional Ti/Pt properties such as excellent chemical stability, high current efficiency, low hydrogen evolution potential, and a long operational lifespan thereby providing electrode with corrosion resistance, high catalytic activities, excellent electrical conductivity, structure integrity for enhance overall device performance. With respect to claim 14, Yamamoto discloses, in Figs.1-10B, the light-emitting diode, wherein the titanium in said first metal electrode forms a titanium-containing layer having a thickness of greater than 800 angstroms (Å) (see Par.[0077] wherein the n-side electrode 93, particularly the wiring portion 93a preferably contains Au and Ge, or preferably contains Ti, Pt, and Au; the n-side electrode 93 containing these metallic elements ensures an ohmic contact with the n-type InGaAs contact layer 20A); and a first metal electrode (93) formed on said first surface of said epitaxial structure (30), and including a main electrode and a plurality of auxiliary electrodes/(branches electrodes), said auxiliary electrodes being formed on said ohmic contact layer (20A) opposite to said light-emitting layer (35) and being electrically connected to said ohmic contact layer (20A; see Par.[0112] wherein electrode (Au (thickness: 10 nm)/Ge (thickness: 33 nm)/Au (thickness: 57 nm)/Ni (thickness: 34 nm)/Au (thickness: 800 nm); a pad portion 93b (Ti (thickness: 150 nm=1500Å)/Pt (thickness: 100 nm)/Au (thickness: 2500 nm)) was formed at the center portion of the n-side electrode to obtain the n-side electrode having a pattern as illustrated in FIG. 10B) was formed as a wiring portion 93a). Claims 9-10, 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Ito. With respect to claim 9, Ito discloses, in Figs.1-28, the light-emitting diode, wherein said ohmic contact layer is n-type doped and has a doping concentration, said window layer being n-type doped and having a doping concentration (see Par.[0078] wherein the compound semiconductor layer 7 is an epitaxial layer formed by an epitaxial growth method; see Par.[0079]-[0081] wherein a p-type cladding layer 17 (having a thickness of, e.g., 0.1 μm to 2.5 μm) sequentially from the side of the substrate 2; on the other hand, the n-type semiconductor layer 14 is formed by stacking an n-type cladding layer 18 (having a thickness of, e.g., 0.1 μm to 2.5 μm), an n-type window layer 19 (having a thickness of, e.g., 2.0 μm to 5.0 μm) as an example of the second layer of the present disclosure and an n-type contact layer 20 (having a thickness of, e.g., 0.1 μm to 2.5 μm) as an example of the first layer of the present disclosure sequentially on the light-emitting layer 12; the n-type window layer 19 may be formed as an n-type semiconductor layer by doping AlInGaP with, for example, Si as an n-type dopant; the p-type contact layer 15 and the n-type contact layer 20 are low resistance layers for making ohmic contact with the light-transmitting conductive layer 6 and the cathode electrode layer 11, respectively; as such the interface contact between 19 and 20 is of ohmic contact; see Figs.2 wherein projections of electrode portions on first surface is smaller than or equal to that of ohmic contact layer). Even though Ito does not disclose n-type doped and has a doping concentration of greater than 4E+18/cm3, said window layer being n-type doped and having a doping concentration of ranging from 4E+17/cm3 to 4E+18/cm3, the said range is predictable by simple engineering optimization motivated by a design choice, such as, band gap optimization for efficient light extraction. In cases like the present, where patentability is said to be based upon particular chosen dimensions or upon another variable recited within the claims, applicant must show that the chosen dimensions are critical. As such, the claimed dimensions appear to be an obvious matter of engineering design choice and thus, while being a difference, does not serve in any way to patentably distinguish the claimed invention from the applied prior art. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990); In re Kuhle, 526 F2d. 553,555,188 USPQ 7, 9 (CCPA 1975). With respect to claim 10, Ito discloses, in Figs.1-28, the light-emitting diode, wherein a relation between AlxGayInP and AlmGanInP is m–x≥0.2, where m ranges from 0.2 to 1.0, x ranging from 0 to 0.8 (see Par.[0078] wherein the compound semiconductor layer 7 is an epitaxial layer formed by an epitaxial growth method; see Par.[0079]-[0081] wherein a p-type cladding layer 17 (having a thickness of, e.g., 0.1 μm to 2.5 μm) sequentially from the side of the substrate 2; on the other hand, the n-type semiconductor layer 14 is formed by stacking an n-type cladding layer 18 (having a thickness of, e.g., 0.1 μm to 2.5 μm), an n-type window layer 19 (having a thickness of, e.g., 2.0 μm to 5.0 μm) as an example of the second layer of the present disclosure and an n-type contact layer 20 (having a thickness of, e.g., 0.1 μm to 2.5 μm) as an example of the first layer of the present disclosure sequentially on the light-emitting layer 12; the n-type window layer 19 may be formed as an n-type semiconductor layer by doping AlInGaP with, for example, Si as an n-type dopant; the p-type contact layer 15 and the n-type contact layer 20 are low resistance layers for making ohmic contact with the light-transmitting conductive layer 6 and the cathode electrode layer 11, respectively; as such the interface contact between 19 and 20 is of ohmic contact; see Figs.2 wherein projections of electrode portions on first surface is smaller than or equal to that of ohmic contact layer). With respect to claim 17, Ito discloses, in Figs.1-28, the light-emitting diode, wherein said ohmic contact layer is n-type doped and has a doping concentration, said window layer being n-type doped and having a doping concentration (see Par.[0078] wherein the compound semiconductor layer 7 is an epitaxial layer formed by an epitaxial growth method; see Par.[0079]-[0081] wherein a p-type cladding layer 17 (having a thickness of, e.g., 0.1 μm to 2.5 μm) sequentially from the side of the substrate 2; on the other hand, the n-type semiconductor layer 14 is formed by stacking an n-type cladding layer 18 (having a thickness of, e.g., 0.1 μm to 2.5 μm), an n-type window layer 19 (having a thickness of, e.g., 2.0 μm to 5.0 μm) as an example of the second layer of the present disclosure and an n-type contact layer 20 (having a thickness of, e.g., 0.1 μm to 2.5 μm) as an example of the first layer of the present disclosure sequentially on the light-emitting layer 12; the n-type window layer 19 may be formed as an n-type semiconductor layer by doping AlInGaP with, for example, Si as an n-type dopant; the p-type contact layer 15 and the n-type contact layer 20 are low resistance layers for making ohmic contact with the light-transmitting conductive layer 6 and the cathode electrode layer 11, respectively; as such the interface contact between 19 and 20 is of ohmic contact; see Figs.2 wherein projections of electrode portions on first surface is smaller than or equal to that of ohmic contact layer). Even though Ito does not disclose n-type doped and has a doping concentration of greater than 4E+18/cm3, said window layer being n-type doped and having a doping concentration of ranging from 4E+17/cm3 to 4E+18/cm3, the said range is predictable by simple engineering optimization motivated by a design choice, such as, band gap optimization for efficient light extraction. In cases like the present, where patentability is said to be based upon particular chosen dimensions or upon another variable recited within the claims, applicant must show that the chosen dimensions are critical. As such, the claimed dimensions appear to be an obvious matter of engineering design choice and thus, while being a difference, does not serve in any way to patentably distinguish the claimed invention from the applied prior art. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990); In re Kuhle, 526 F2d. 553,555,188 USPQ 7, 9 (CCPA 1975). With respect to claim 18, Ito discloses, in Figs.1-28, the light-emitting diode, wherein a relation between AlxGayInP and AlmGanInP is m–x≥0.2, where m ranges from 0.2 to 1.0, x ranging from 0 to 0.8 (see Par.[0078] wherein the compound semiconductor layer 7 is an epitaxial layer formed by an epitaxial growth method; see Par.[0079]-[0081] wherein a p-type cladding layer 17 (having a thickness of, e.g., 0.1 μm to 2.5 μm) sequentially from the side of the substrate 2; on the other hand, the n-type semiconductor layer 14 is formed by stacking an n-type cladding layer 18 (having a thickness of, e.g., 0.1 μm to 2.5 μm), an n-type window layer 19 (having a thickness of, e.g., 2.0 μm to 5.0 μm) as an example of the second layer of the present disclosure and an n-type contact layer 20 (having a thickness of, e.g., 0.1 μm to 2.5 μm) as an example of the first layer of the present disclosure sequentially on the light-emitting layer 12; the n-type window layer 19 may be formed as an n-type semiconductor layer by doping AlInGaP with, for example, Si as an n-type dopant; the p-type contact layer 15 and the n-type contact layer 20 are low resistance layers for making ohmic contact with the light-transmitting conductive layer 6 and the cathode electrode layer 11, respectively; as such the interface contact between 19 and 20 is of ohmic contact; see Figs.2 wherein projections of electrode portions on first surface is smaller than or equal to that of ohmic contact layer). Citation of Pertinent Prior Art The prior art made of record (e.g.; see PTO-892) and not relied upon is considered pertinent to applicant's disclosure. Examiner’s Telephone/Fax Contacts Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOULOUCOULAYE INOUSSA whose telephone number is (571)272-0596. The examiner can normally be reached Monday-Friday (10-18). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JEFF W NATALINI can be reached at 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Mouloucoulaye Inoussa/ Primary Examiner, Art Unit 2818
Read full office action

Prosecution Timeline

Oct 25, 2023
Application Filed
Feb 20, 2026
Non-Final Rejection — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12604746
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
2y 5m to grant Granted Apr 14, 2026
Patent 12589451
PASTE COMPOSITION AND SEMICONDUCTOR DEVICE
2y 5m to grant Granted Mar 31, 2026
Patent 12588421
MEMORY ELEMENT WITH A HARDMASK STACK HAVING DIFFERENT STRESS LEVELS
2y 5m to grant Granted Mar 24, 2026
Patent 12588241
ASYMMETRIC SOURCE AND DRAIN CONTACTS FOR A THIN FILM TRANSISTOR (TFT) STRUCTURE
2y 5m to grant Granted Mar 24, 2026
Patent 12588521
Metal Nitride Core-Shell Particle Die-Attach Material
2y 5m to grant Granted Mar 24, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
93%
With Interview (+7.1%)
2y 6m
Median Time to Grant
Low
PTA Risk
Based on 752 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month