Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Allowable Subject Matter
Claims 10-19 and 21 are allowed.
The following is an examiner’s statement of reasons for allowance:
The primary reason for the allowance of the claim is the inclusion of the limitation “a first connection line connecting the source region of the source follower transistor to the first pickup dopant region” as recited in independent claim 10, in all of the claims which is not found in the prior art references.
Claims 11-19 are allowed for the same reasons as claim 10, from which they depend.
The primary reason for the allowance of the claim is the inclusion of the limitation “a first connection line electrically connecting a source terminal of the source follower transistor to the first pickup dopant region” as recited in independent claim 21, in all of the claims which is not found in the prior art references.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claim 3 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The primary reason for the allowance of the claims is the inclusion of the limitation, along with the other claimed features, “a first pickup dopant region in the first well region; and
a first connection line electrically connecting the source terminal of the source follower transistor to the first pickup dopant region”, as recited in claim 3.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2 and 4- 9 are rejected under 35 U.S.C. 103 as being unpatentable over Wan et al. (U.S. 2014/0042299 A1, hereinafter refer to Wan) in view of Gocho et al. (U.S. 2021/0400224 A1, hereinafter refer to Gocho).
Regarding Claim 1: Wan discloses an image sensor (see Wan, Figs.10-11 as shown below and ¶ [0011]) comprising:
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a photoelectric conversion element (24) in a first semiconductor substrate (26) (see Wan, Fig.10 as shown above);
a second semiconductor substrate (120) on the first semiconductor substrate (26) (see Wan, Fig.10 as shown above);
a source follower transistor (128) on the second semiconductor substrate (120) (see Wan, Figs.10-11 as shown above); and
a through-plug (146) penetrating the second semiconductor substrate (120), the through-plug (146) electrically connecting the photoelectric conversion element (24) to the source follower transistor (128) (see Wan, Figs.10-11 as shown above and ¶ [0040]- ¶ [0041]),
wherein a source terminal of the source follower transistor (128) is electrically connected to the second semiconductor substrate (120) (see Wan, Figs.10-11 as shown above).
Wan is silent upon explicitly disclosing wherein the second semiconductor substrate including a first well region having a first conductivity type;
a source follower transistor on the first well region of the second semiconductor substrate;
an isolation structure in the second semiconductor substrate, the isolation structure surrounding the first well region when viewed in a plan view.
For support see Gocho, which teaches wherein the second semiconductor substrate (300) including a first well region (301) having a first conductivity type (see Gocho, Figs.45, 51, 52, and 53 as shown below and ¶ [0332]);
a source follower transistor (104) on the first well region (301) of the second semiconductor substrate (300) (see Gocho, Figs.45, 51, 52, and 53 as shown below, ¶ [0338] - ¶ [0339], ¶ [0349], ¶ [0353]);
an isolation structure (STI) in the second semiconductor substrate (300), the isolation structure (STI) surrounding the first well region when viewed in a plan view (see Gocho, Figs.52-53 as shown below, ¶ [0338] - ¶ [0339], ¶ [0349], ¶ [0353]).
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Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Wan and Gocho to enable the second semiconductor substrate to include a first well region having a first conductivity type; a source follower transistor to be formed on the first well region of the second semiconductor substrate and an isolation structure in the second semiconductor substrate, the isolation structure to surround the first well region when viewed in a plan view as taught by Gocho in order to individually control the respective threshold voltages of the selection transistor, the reset transistor, and the amplification transistor and to turn on amplification transistor at a desired voltage value and amplify the electrical signal from the photoelectric conversion element.
Regarding Claim 2: Wan as modified teaches an image sensor as set forth in claim 1 as above. The combination of Wan and Gocho further teaches wherein the second semiconductor substrate (300) further comprises a second well region (301) separated from the first well region (301) by the isolation structure (STI) (see Gocho, Figs.52-53 as shown above, ¶ [0338] - ¶ [0339], ¶ [0349], ¶ [0353]).
Regarding Claim 4: Wan as modified teaches an image sensor as set forth in claim 2 as above. The combination of Wan and Gocho further teaches wherein a second connection line (138) electrically connecting a gate terminal of the source follower transistor (128) to the through-plug (146) (see Wan, Fig.10 as shown above and Fig.9).
Regarding Claim 5: Wan as modified teaches an image sensor as set forth in claim 2 as above. The combination of Wan and Gocho further teaches wherein a reset transistor on the second well region (301) of the second semiconductor substrate (300) (see Gocho, Figs.52-53 as shown above, ¶ [0338] - ¶ [0339], ¶ [0349], ¶ [0353]); and
a second pickup dopant region (321) in the second well region (301) (see Gocho, Figs.52-53 as shown above, ¶ [0338] - ¶ [0339], ¶ [0349], ¶ [0353]).
Regarding Claim 6: Wan as modified teaches an image sensor as set forth in claim 2 as above. The combination of Wan and Gocho further teaches wherein the first well region (301) is electrically isolated from the second well region (301) (see Gocho, Figs.52-53 as shown above, ¶ [0338] - ¶ [0339], ¶ [0349], ¶ [0353]).
Regarding Claim 7: Wan as modified teaches an image sensor as set forth in claim 2 as above. The combination of Wan and Gocho further teaches wherein the through-plug (Cfd) penetrates the first well region (301) of the second semiconductor substrate (300) (see Gocho, Figs.45, 51, and 52-53 as shown above, ¶ [0338] - ¶ [0339], ¶ [0349], ¶ [0353]).
Regarding Claim 8: Wan as modified teaches an image sensor as set forth in claim 1 as above. The combination of Wan and Gocho further teaches wherein a through-insulating pattern (340) penetrating the second semiconductor substrate (300), the through-insulating pattern (340) surrounding a side surface of the through-plug (Cfd) (see Gocho, Figs.45, 51, and 52-53 as shown above, ¶ [0338] - ¶ [0339], ¶ [0349], ¶ [0353]).
Regarding Claim 9: Wan as modified teaches an image sensor as set forth in claim 1 as above. The combination of Wan and Gocho further teaches wherein a floating diffusion region (32) in the first semiconductor substrate (26) (see Wan, Figs.10-11 as shown above); and
a transfer gate electrode (30) between the photoelectric conversion element (24) and the floating diffusion region (32), wherein the through-plug (146) is electrically connected to the floating diffusion region (32) (see Wan, Figs.10-11 as shown above).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BITEW A DINKE whose telephone number is (571)272-0534. The examiner can normally be reached M-F 7 a.m. - 5 p.m..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571)272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BITEW A DINKE/Primary Examiner, Art Unit 2812
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