DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claims 10-19 and 21 are allowed.
The following is an examiner’s statement of reasons for allowance:
The primary reason for the allowance of the claim is the inclusion of the limitation “a first connection line connecting the source region of the source follower transistor to the first pickup dopant region” as recited in independent claim 10, in all of the claims which is not found in the prior art references.
Claims 11-19 are allowed for the same reasons as claim 10, from which they depend.
The primary reason for the allowance of the claim is the inclusion of the limitation “a first connection line electrically connecting a source terminal of the source follower transistor to the first pickup dopant region” as recited in independent claim 21, in all of the claims which is not found in the prior art references.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claim 3 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The primary reason for the allowance of the claims is the inclusion of the limitation, along with the other claimed features, “a first pickup dopant region in the first well region; and
a first connection line electrically connecting the source terminal of the source follower transistor to the first pickup dopant region”, as recited in claim 3.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wan et al. (U.S. 2014/0042299 A1, hereinafter refer to Wan).
Regarding Claim 1: Wan discloses an image sensor (see Wan, Figs.10-11 as shown below and ¶ [0011]) comprising:
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a photoelectric conversion element (24) in a first semiconductor substrate (26) (see Wan, Fig.10 as shown above);
a second semiconductor substrate (120) on the first semiconductor substrate (26) (see Wan, Fig.10 as shown above);
a source follower transistor (128) on the second semiconductor substrate (120) (see Wan, Figs.10-11 as shown above); and
a through-plug (146) penetrating the second semiconductor substrate (120), the through-plug (146) electrically connecting the photoelectric conversion element (24) to the source follower transistor (128) (see Wan, Figs.10-11 as shown above and ¶ [0040]- ¶ [0041]),
wherein a source terminal of the source follower transistor (128) is electrically connected to the second semiconductor substrate (120) (see Wan, Figs.10-11 as shown above).
Regarding Claim 9: Wan discloses an image sensor as set forth in claim 1 as above. Wan further teaches wherein a floating diffusion region (32) in the first semiconductor substrate (26) (see Wan, Figs.10-11 as shown above); and
a transfer gate electrode (30) between the photoelectric conversion element (24) and the floating diffusion region (32), wherein the through-plug (146) is electrically connected to the floating diffusion region (32) (see Wan, Figs.10-11 as shown above).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2 and 4-8 are rejected under 35 U.S.C. 103 as being unpatentable over Wan et al. (U.S. 2014/0042299 A1, hereinafter refer to Wan) as applied to claim 1 above, and further in view of Yamada et al. (WO 2021/256142 A1, hereinafter refer to Yamada).
U.S. 2023/0254608 A1 (hereinafter refer to Yamada) is relied upon solely for the English language translation of WO 2021/256142 A1.
Regarding Claim 2: Wan discloses an image sensor as applied to claim 1 above. Wan is silent upon explicitly disclosing wherein the second semiconductor substrate comprises: a first well region;
a second well region; and an isolation structure surrounding the first well region, wherein the source follower transistor is on the first well region.
Before effective filing date of the claimed invention the disclosed second semiconductor substrate were known to comprises a first well region; a second well region; and an isolation structure surrounding the first well region, wherein the source follower transistor is on the first well region in order to obtain an imaging device capable of suppressing deterioration in characteristics.
For support see Yamada, which teaches wherein the second semiconductor substrate (20) comprises: a first well region (PWL) (see Yamada, Figs.8 and 10 as shown below, ¶ [0006]);
a second well region (PWL); and an isolation structure (202) surrounding the first well region (PWL), wherein the source follower transistor (AMP) is on the first well region (PWL) (see Yamada, Figs.8 and 10 as shown below, ¶ [0006]).
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Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Wan and Yamada to enable the second semiconductor substrate of Wan to comprises the first well region; the second well region; and an isolation structure surrounding the first well region, wherein the source follower transistor to be formed on the first well region as taught by Yamada in order to obtain an imaging device capable of suppressing deterioration in characteristics.
Regarding Claim 4: Wan discloses an image sensor as set forth in claim 2 as above. The combination of Wan and Yamada further teaches wherein a second connection line (138) electrically connecting a gate terminal of the source follower transistor (128) to the through-plug (146) (see Wan, Fig.10 as shown above and Fig.9).
Regarding Claim 5: Wan discloses an image sensor as set forth in claim 2 as above. The combination of Wan and Yamada further teaches wherein a reset transistor on the second well region (PWL) of the second semiconductor substrate (10); and
a second pickup dopant region (FD) in the second well region (PWL) (see Yamada, Fig.10 as shown above).
Regarding Claim 6: Wan discloses an image sensor as set forth in claim 2 as above. The combination of Wan and Yamada further teaches wherein the first well region (PWL) is electrically isolated from the second well region (PWL) (see Yamada, Fig.10 as shown above).
Regarding Claim 7: Wan discloses an image sensor as set forth in claim 2 as above. The combination of Wan and Yamada further teaches wherein the through-plug (FL2) penetrates the first well region (PWL) of the second semiconductor substrate (20) (see Yamada, Fig.10 as shown above).
Regarding Claim 8: Wan discloses an image sensor as applied to claim 1 above. Wan is silent upon explicitly disclosing wherein a through-insulating pattern penetrating the second semiconductor substrate, the through-insulating pattern surrounding a side surface of the through-plug.
Before effective filing date of the claimed invention the disclosed through-insulating pattern were known to penetrate the second semiconductor substrate and the through-insulating pattern surrounding a side surface of the through-plug in order to obtain an imaging device capable of suppressing deterioration in characteristics.
For support see Yamada, which teaches wherein a through-insulating pattern (202) penetrating the second semiconductor substrate (20), the through-insulating pattern (202) surrounding a side surface of the through-plug (FL2 or DL or VL) (see Yamada, Figs.8 and 10 as shown above, ¶ [0006]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Wan and Yamada to enable the through-insulating pattern to be penetrating the second semiconductor substrate and the through-insulating pattern surrounds a side surface of the through-plug as taught by Yamada in order to obtain an imaging device capable of suppressing deterioration in characteristics.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BITEW A DINKE whose telephone number is (571)272-0534. The examiner can normally be reached M-F 7 a.m. - 5 p.m..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571)272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BITEW A DINKE/Primary Examiner, Art Unit 2812