Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested:
STRUCUTRE OF A GATE CONTACT OF A SEMICONDUCTOR DEVICE
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng [US PGPUB 20230065446] in view of Li et al. [US PGPUB 20240213141] and in view of Wu et al. [US PGPUB 20210134667] (hereinafter Li and Wu).
Regarding claim 1, Cheng teaches a semiconductor device, comprising:
a substrate (110/115/120, Para 40) including an active pattern (120, Fig. 15);
a channel pattern (22, Para 48) on the active pattern (Fig. 15), the channel pattern including a plurality of semiconductor patterns (Para 48) that are vertically stacked and spaced apart from each other (Fig. 15);
a source/drain pattern (82, Para 63, Fig. 15) connected to the plurality of semiconductor patterns (Fig. 15);
a gate electrode (200, Para 73) on the plurality of semiconductor patterns (Fig. 15), the gate electrode including a plurality of inner electrodes (3 gate 200 bordered by source/drain pattern, Fig. 15) between neighboring semiconductor patterns of the plurality of semiconductor patterns (Fig. 15) and an outer electrode (gate 200 formed in layer 130A, Fig. 15) on an uppermost semiconductor pattern of the plurality of semiconductor patterns (Fig. 15); and
a gate contact structure (75/77, Para 80) electrically connected to the outer electrode (Fig. 15), wherein
the gate contact structure includes a lower gate contact (75, Fig. 15) on a top surface of the outer electrode (Fig. 15) and an upper gate contact (77, Fig. 15) on the lower gate contact (Fig. 15).
Cheng does not specifically disclose that the lower gate contact includes a first liner pattern, a first filling pattern on the first liner pattern, and a nucleation pattern between the first liner pattern and the first filling pattern.
However, it is noted that Cheng further discloses that the material of the first metal contact plug 75 includes tungsten (W). However, other electrically conductive materials may be used (Para 78).
In view of such further teaching by Cheng, a person having ordinary skills in the art would have been obvious to explore or implement other materials as a gate contact in Cheng’s invention.
Referring to the invention of Li, Li teaches that forming a gate contact M1/VB to gate electrode 150, wherein the gate contact can include metallic fill material (first filling pattern) including, but not limited to, tungsten (W), cobalt (Co), ruthenium (Ru), copper (Cu), or combinations thereof, as well as thin liner layers (not shown) (e.g., TiN and/or TaN barrier layer) (first liner pattern) and/or seed layer (nucleation pattern)) which are formed prior to depositing the metallic fill material (Para 92).
In view of such teaching by Li, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the invention of Cheng comprise the teachings of Li at least based on the rationale of using known technique to improve similar devices (methods, or products) in the same way using (MPEP 2143.I.C); wherein it is known that such structure helps prevent metallic material from diffusing into surrounding dielectric layers.
Regarding the limitation “the nucleation pattern between the first liner pattern and the first filling pattern,” Wu teaches a gate contact structure 102, wherein nucleation pattern (seed layer 109, Para 61) is formed between the liner pattern (barrier layer 104, Para 55) and filling pattern (conductive material 110, Para 64).
In view of such teaching by Wu, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the invention modified invention of Cheng in view Li comprise the teachings of Wu at least based on the rationale of using known technique to improve similar devices (methods, or products) in the same way using (MPEP 2143.I.C) and/or relying on teachings, suggestions, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention (MPEP 2143.I.G).
Regarding claim 2, the modified invention of Cheng specifically in view of Wu teaches a semiconductor device wherein the nucleation pattern extends from a bottom surface of the first filling pattern to a lateral surface of the first filling pattern (Wu, Fig. 20A).
Regarding claim 3, the modified invention of Cheng specifically in view of Cheng/Wu teaches a semiconductor device wherein the nucleation pattern extends to a bottom surface of the upper gate contact (Cheng, Fig. 15; in view of the upper gate contact entirely covering the lower gate contact, and in view of Wu disclosing eliminating any recess at a surface of the nucleation pattern, Para 69/70, Fig. 20A/21).
In view of such teaching by Cheng and Wu, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the nucleation pattern extends to a bottom surface of the upper gate contact in order to prevent increasing contact resistance or structural defects (Wu, Para 69).
Regarding claim 4, the modified invention of Cheng specifically in view of Wu teaches a semiconductor device wherein the nucleation pattern includes boron and at least one of aluminum, copper, tungsten, molybdenum, and cobalt (Wu, Para 58/59; i.e, tungsten with reduced concentration of boron).
Regarding claim 6, the modified invention of Cheng specifically in view of Wu teaches a semiconductor device wherein the nucleation pattern is a tungsten (W) single layer (Para 57).
Regarding the limitation “deposited by performing a pulse nucleation layer (PNL) process”, it should be noted that the present claim is drawn to a device, thus, the PNL process limitation would not structurally distinguish the present invention from the modified invention of Cheng.
It should be noted that a "product by process claim" is directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wertheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); and In re Marosi et al., 218 USPQ 289, all of which make it clear that it is the patentability of the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in " product by process" claims or not. Note that applicant has the burden of proof in such cases, as the above caselaw makes clear. See also MPEP 2113 [R-1].
Regarding claim 12, the modified invention of Cheng specifically in view of Cheng/Wu teaches a semiconductor device wherein a bottom surface of the upper gate contact, a top surface of the first liner pattern, a top surface of the first filling pattern, and a top surface of the nucleation pattern are in direct contact with each other (Cheng, Fig. 15; in view of the upper gate directly contacting the lower gate contact, and in view of Wu disclosing eliminating any recess at a surface of the nucleation pattern, Para 69/70, Fig. 20A/21).
In view of such teaching by Cheng and Wu, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the nucleation pattern extends to a bottom surface of the upper gate contact in order to prevent increasing contact resistance or structural defects (Wu, Para 69).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng in view of Li and Wu and further in view of Sharangpani et al. [US PGPUB 20160149049] (hereinafter Sharangpani).
Regarding claim 5, the modified invention of Cheng teaches the limitation of claim 4 upon which it depends.
The modified invention of Cheng does not specifically disclose a semiconductor device wherein the nucleation pattern is non-crystalline or amorphous.
Referring to the invention of Sharangpani, Sharangpani discloses that it is known that boron containing tungsten nucleation pattern are formed in amorphous state (Para 133).
In view of such teaching by Sharangpani, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the modified invention of Chen comprise the teachings of Sharangpani, at least based on the rationale of using known technique to improve similar devices (methods, or products) in the same way using (MPEP 2143.I.C)
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng in view of Li and Wu and further in view of Wang et al. [US Patent 7405151] (hereinafter Wang).
Regarding claim 7, the modified invention of Cheng specifically in view of Li teaches a semiconductor device wherein the upper gate contact includes a second liner pattern and a second filling pattern on the second liner pattern (Para 92, in view of gate contact M1/VB to gate electrode 150, comprising metallic fill material (second filling pattern) including, but not limited to, tungsten (W), cobalt (Co), ruthenium (Ru), copper (Cu), or combinations thereof, as well as thin liner layers (not shown) (e.g., TiN and/or TaN barrier layer) (second liner pattern) ... (Para 98).
The modified invention does not specifically disclose that the second liner pattern extends from a bottom surface of the second filling pattern to a lateral surface of the second filling pattern.
Referring to the invention of Wang, Wang teaches forming contact structures at different levels of a device (Fig. 6, 200, 215/217/220, and 250/255/260), wherein the contact structures have the similar structures, wherein liner pattern (170, 215, and 250 of the respective contact structure) extends from a bottom surface of filling pattern (190a, 220, 260) to a lateral surface of the filling pattern (Fig. 6).
In view of such teaching by Wang, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the modified invention of Cheng have the bottom gate contact as disclosed by Wu duplicated at the upper gate contact of Cheng at least based on the rationale of using known technique to improve similar devices (methods, or products) in the same way using (MPEP 2143.I.C)
Claims 8 and 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng in view of Li, Wu and Wang and further in view of Yang et al. [US PGPUB 20230420295] (hereinafter Yang).
Regarding claim 8, the modified invention of Cheng teaches the limitation of claim 7 upon which it depends.
The modified invention despite disclosing the use of similar material as those of the claimed invention in layer of the device, fails to specifically disclose wherein the first liner pattern, the second liner pattern, the first filling pattern, and the second filling pattern independently includes at least one of aluminum, copper, tungsten, molybdenum, and cobalt.
Referring to the invention of Yang, Yang teaches forming a contact structure (Fig. 2E/F), wherein liner pattern (230), nucleation pattern (240), and the filling pattern (274) form a tungsten-containing layer (Para 72, meaning the layers all contain tungsten –see Para 41/42/71).
In view of such teaching by Yang, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the modified invention of Cheng comprise the teaching of Yang at least based on the rationale of simple substitution of one known element/structure with a suitable another to obtain predictable results (MPEP 2143.I.B).
Regarding claim 10, the modified invention of Cheng specifically in view of Yang teaches a semiconductor device wherein the first liner pattern and the second liner pattern each are a tungsten (W) layer (in view of layers 230/240/274 containing tungsten –see Para 41/42/71).
Regarding the limitation “deposited by performing a physical vapor deposition (PVD) process”, it should be noted that the present claim is drawn to a device, thus, the PVD process limitation would not structurally distinguish the present invention from the modified invention of Cheng.
It should be noted that a "product by process claim" is directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wertheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); and In re Marosi et al., 218 USPQ 289, all of which make it clear that it is the patentability of the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in " product by process" claims or not. Note that applicant has the burden of proof in such cases, as the above caselaw makes clear. See also MPEP 2113 [R-1].
Regarding claim 11, the modified invention of Cheng specifically in view of Yang teaches a semiconductor device wherein the first filling pattern and the second filling patterns each are a tungsten (W) layer (in view of layers 230/240/274 containing tungsten –see Para 41/42/71).
Regarding the limitation “deposited by performing a chemical vapor deposition (CVD) process”, it should be noted that the present claim is drawn to a device, thus, the CVD process limitation would not structurally distinguish the present invention from the modified invention of Cheng.
It should be noted that a "product by process claim" is directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wertheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); and In re Marosi et al., 218 USPQ 289, all of which make it clear that it is the patentability of the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in " product by process" claims or not. Note that applicant has the burden of proof in such cases, as the above caselaw makes clear. See also MPEP 2113 [R-1].
Claims 1-2, 4, 6 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Bae et al. [US PGPUB 20210391464] in view Wu (hereinafter Bae).
Regarding claim 1, Bae teaches a semiconductor device, comprising:
a substrate (110, Para 23) including an active pattern (FA1, Para 26);
a channel pattern (NS1, Para 74) on the active pattern (Fig. 11), the channel pattern including a plurality of semiconductor patterns that are vertically stacked and spaced apart from each other (Fig. 11);
a source/drain pattern (SD1, Para 80) connected to the plurality of semiconductor patterns (Fig. 11);
a gate electrode (224, Para 81) on the plurality of semiconductor patterns (Fig. 11), the gate electrode including a plurality of inner electrodes (224S, Para 78) between neighboring semiconductor patterns of the plurality of semiconductor patterns (Fig. 11) and an outer electrode (electrode 224, Para 78) on an uppermost semiconductor pattern of the plurality of semiconductor patterns (Fig. 11); and
a gate contact structure (CB/184, Para 62) electrically connected to the outer electrode (Fig. 11), wherein the gate contact structure includes a lower gate contact (CB) on a top surface of the outer electrode and an upper gate contact (184) on the lower gate contact (Fig. 11), and
the lower gate contact includes a first liner pattern (172, Para 57), a first filling pattern (174, Para 57) on the first liner pattern (Fig. 11).
Bae does not specifically disclose a nucleation pattern between the first liner pattern and the first filling pattern.
metallic material from diffusing into surrounding dielectric layers.
Regarding the limitation “the nucleation pattern between the first liner pattern and the first filling pattern,” Wu teaches a gate contact structure 102, wherein in forming a tungsten fill pattern 110 (Para 64) on linear pattern 104 (Para 55) a nucleation pattern (seed layer 109, Para 61) is formed between the liner pattern and filling pattern.
In view of such teaching by Wu, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the invention of Bae further comprising the teachings of Wu at least based on the rationale of using known technique to improve similar devices (methods, or products) in the same way using (MPEP 2143.I.C) and/or relying on teachings, suggestions, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention (MPEP 2143.I.G).
Regarding claim 2, the modified invention of Bae specifically in view of Wu, teaches a semiconductor device wherein the nucleation pattern extends from a bottom surface of the first filling pattern to a lateral surface of the first filling pattern (Wu, Fig. 20A).
Regarding claim 4, the modified invention of Bae specifically in view of Wu, teaches a semiconductor device wherein the nucleation pattern includes boron and at least one of aluminum, copper, tungsten, molybdenum, and cobalt (Para 59).
Regarding claim 6, the modified invention of Bae specifically in view of Wu, teaches a semiconductor device wherein the nucleation pattern is a tungsten (W) single layer (Para 58).
Regarding the limitation “deposited by performing a pulse nucleation layer (PNL) process”, it should be noted that the present claim is drawn to a device, thus, the PNL process limitation would not structurally distinguish the present invention from the modified invention of Bae.
It should be noted that a "product by process claim" is directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wertheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); and In re Marosi et al., 218 USPQ 289, all of which make it clear that it is the patentability of the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in " product by process" claims or not. Note that applicant has the burden of proof in such cases, as the above caselaw makes clear. See also MPEP 2113 [R-1].
Regarding claim 13, Bae teaches a semiconductor device wherein a width in a first direction of the outer electrode is less than a width in the first direction of the gate contact structure.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Bae in view of Shama et al. [US PGPUB 20230200093] (hereinafter Shama).
Regarding claim 17, Bae teaches a semiconductor device, comprising:
a substrate 100 (Para 23, Fig.11) including an active pattern (FA1, Para 26, Fig. 11);
a device isolation layer (DTA) on the substrate and defining the active pattern (Fig. 9);
a channel pattern (NS1, Para 75) on the active pattern (Fig. 11), the channel pattern including a plurality of semiconductor patterns that are vertically stacked and spaced apart from each other (Fig. 11);
a source/drain pattern (SD1, Para 80) connected to the plurality of semiconductor patterns (Fig. 11);
a gate electrode (224, Para 81) on the plurality of semiconductor patterns (Fig. 11);
a gate dielectric layer (222, Para 79) between the gate electrode and neighboring semiconductor patterns among the plurality of semiconductor patterns (Fig. 11);
a gate spacer (232, Para 81) on a sidewall of the gate electrode (Fig. 11);
a gate contact structure (CB/184, Para 62) electrically connected to the gate electrode (Para 61), the gate contact structure including a lower gate contact (CB) in direct contact with the gate electrode and an upper gate contact (184) on the lower gate contact (Fig. 11);
an active contact structure (CA1/184, Para 62) electrically connected to the source/drain pattern (Para 22, Fig. 11), the active contact structure including a lower active contact (CA1) adjacent to the source/drain pattern and an upper active contact (184) on the lower active contact (Fig. 11);
a metal-semiconductor compound layer (156, Para 103) between the active contact structure and the source/drain pattern (Fig. 11);
a first layer (186, Para 62) on the gate contact structure (Fig. 11), the first layer including a power line (M11, Para 62) and a first wiring line (M13, Para 62) electrically connected to the active contact structure (Fig. 11); and,
wherein
a top surface of the upper gate contact and a top surface of the upper active contact are coplanar with each other (Fig. 11), and
a level of a bottom surface of the upper gate contact is higher than a level of a bottom surface of the upper active contact (Fig. 11).
Bae does not specifically disclose that the first layer is a metal layer; and
a second metal layer on the first metal layer, the second metal layer including a second wiring line electrically connected to first metal layer.
Referring to the invention of Shama discloses the using of FETs to drive memory cells (Fig. 5), wherein device has a first metal layer (M1, Para 49); and
plurality of metal layers (M2-M11) to include second metal layer (M2) on the first metal layer (Fig. 5), the second metal layer including a second wiring line electrically connected to first metal layer (Fig. 5).
In view of such teaching by Shama, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the invention of Bae comprise the teachings of Shama at least based on the rationale of to have relying on teachings, suggestions, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention (MPEP 2143.I.G), wherein such implementation would result in a more elaborate device with valuable features (forming a memory device).
Allowable Subject Matter
Claims 14-16 are allowed.
Claims 9 and 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance
Claims 14-16 are allowed because all prior arts of record and related prior arts not of record either singularly or in combination fail to anticipate or render obvious a semiconductor device, comprising:
a lower gate contact which includes a first liner pattern, a first filling pattern on the first liner pattern, and a nucleation pattern between the first liner pattern and the first filling pattern,
the nucleation pattern includes metal and boron,
the nucleation pattern has a first boron concentration,
the first liner pattern and the first filling pattern each have a second boron concentration, and
the first boron concentration is greater than the second boron concentration (as claimed in claim 14), in combination with the rest of claim limitations as claimed and defined by the Applicant.
Conclusion
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/ISMAIL A MUSE/ Primary Examiner, Art Unit 2812
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