DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 4-12, 15-19 and 21-23 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US 2007/0268764 A1).
Regarding claim 1, Kim teaches an electronic device, comprising:
a plurality of memory cells configured to store data (Fig. 3, Cell arrays 2A and 2B);
a plurality of digit lines each configured to carry data to and from a respective memory cell of the plurality of memory cells (Fig. 3, digit lines D and D_); and
a plurality of sense amplifiers each selectively coupled to respective digit lines of the plurality of digit lines and comprising a first transistor of cross-coupled transistors, a second transistor of the cross-coupled transistors, a first gut node, and second gut node wherein each sense amplifier is configured to operate based on coupling, during a presense operation, the first and second gut nodes to a negative voltage source characterized by a negative voltage less than a ground voltage and based on coupling, during at least a latching operation, the first and second gut nodes to the ground voltage (Fig. 3, shows one of the plurality of sense amplifier. Transistors 20 and 22 or transistors 24 and 26 are crossed coupled transistors which are selectively coupled to the digit lines D and D_ through the first and second gut nodes 28 and 30. The first and second gut nodes are less than ground voltage, e.g. -0.3 V, at time t1 to t2. The term presense operation in the specification is described to which the sense amplifier may operate in a differential voltage configuration. During the t1 to t2, the sense amplifier operate in a differential voltage configuration. During time after t2, the latch operation is active to latch the data and the first and second gut nodes are coupled to ground voltage, see Fig. 5 and ¶0024).
Regarding claim 21, Kim further teaches the electronic device of claim 1, wherein each sense amplifier is configured to: charge an n-channel strobe with the negative voltage source, wherein a shared coupling between the plurality of sense amplifiers is configured to transmit the n-channel strobe to each respective sense amplifier of the plurality of sense amplifiers; amplify a differential voltage between the first and second gut nodes at least in part by charging the first gut node and discharging the second gut node based on respective charges from the plurality of digit lines, wherein the respective charges from the plurality of digit lines are based on the charged n-channel strobe; and send the amplified differential voltage to respective digit lines of the plurality of digit lines as a differential signal (Fig. 3, Fig. 4B and Fig. 5, the n-channel strobe for transistor 72 will be transmitted to the sense amplifier. The sense amplifier will amplify a differential voltage between nodes 28 and 30, where one node will be charged to high level and the second node will be discharged to a low level based on the charges on the digit lines).
Regarding claim 4, Kim further teaches the electronic device of claim 21, comprising a memory controller configured to: receive an instruction to perform a sensing operation via a sense amplifier of the plurality of sense amplifiers (inherent to receive a read command to perform sensing operation by the sense amplifier); perform a precharging operation at least in part by sending a first control signal to a third transistor coupled between the sense amplifier and the negative voltage source to turn on the third transistor, wherein turning on the third transistor is configured to charge a n-channel strobe node; send a second control signal to turn off the third transistor based on the n-channel strobe node being charged to a negative voltage; and perform a voltage threshold compensation before amplifying the differential voltage at least in part by transmitting a third control signal to tum on the second transistor coupled between the sense amplifier and a second reference voltage source characterized by the ground voltage (Fig. 5 and Fig. 4B, signal NLATP will send a first signal to third transistor 72 coupled between the sense amplifier and the negative voltage source -0.3V to turn on the third transistor. When the n-channel strobe node is charged to a negative voltage, it will turn off the third transistor. Second transistor 84 is coupled between the ground and the sense amplifier).
Regarding claim 5, Kim further teaches the electronic device of claim 4, wherein the memory controller is configured to: perform the pre sense operation after performing the voltage threshold compensation at least in part by pulsing a fourth control signal to turn on the first transistor (Fig. 5, T1 to T2); and perform the latching operation and an active idle operation after performing the presense operation and after turning off the first transistor (latching operation after T2)
Regarding claim 6, Kim further teaches the electronic device of claim 5, wherein the sense amplifier comprises a first digit line of the plurality of digit lines that corresponds to the first gut node and a second digit line of the plurality of digit lines corresponds to the second gut node, wherein the sense amplifier comprises an equalization transistor configured to equalize the first and second gut node before amplifying the differential voltage, and wherein the equalization transistor is off during the presense operation (Fig. 5, first digital line D and second digital line D_ are equalized using an equalization circuit before T0).
Regarding claim 7, Kim further teaches the electronic device of claim 1, wherein the plurality of digit lines comprise a plurality of complementary pairs of the digit lines of the plurality of digit lines (memory device comprises a plurality of complementary digit lines D_).
Regarding claim 8, Kim further teaches the electronic device of claim 7, wherein each digit line of each of the plurality of complementary pairs of the digit lines is coupled to respective memory cells storing complementary data (Fig. 5, memory cell stores data in one of the nodes 28 or 30 and stores complementary data in the other node 28 or 30).
Regarding claim 9, Kim further teaches the electronic device of claim 1, wherein the negative voltage source is configured to increase a gain of each of the plurality of sense amplifiers (Fig. 5 and ¶0022).
Regarding claim 10, Kim teaches a memory device, comprising:
one or more memory cells configured to store data (Fig. 3, Cell array 1 and cell array B);
a pair of digit lines coupled to the one or more memory cells (Digit lines D and D_); and
a sense amplifier coupled to the pair of digit lines and comprising: cross-coupled transistors coupled to a supply voltage (Fig. 3, transistors 20 and 22);
a first gut node coupled to a first transistor of the cross-coupled transistors, wherein the first gut node corresponds to a first digit line of the pair of digit lines (Node 28 is coupled to a first digit line D);
a second gut node coupled to a second transistor of the cross-coupled transistors, wherein the second gut node corresponds to a second digit line of the pair of digit lines (Node 30 is coupled to a second digit line D_);
a third transistor coupled to the first gut node, wherein a gate of the third transistor is coupled to the second digit line (Transistor 24);
a fourth transistor coupled to the second gut node, wherein a gate of the fourth transistor is coupled to the first digit line (Transistor 26);
a fifth transistor (Fig. 4B, Transistor 72) coupled to a negative voltage, wherein a drain of the fifth transistor is coupled to a source of the third and fourth transistors, wherein the fifth transistor is closed during a presense operation and is open during a latching operation (transistor 72 is closed during presense operation between time T1 and T2, and the fifth transistor is open during the latching operation after T2); and
a sixth transistor (Fig. 4, Transistor 84) coupled to a ground voltage, wherein the sixth transistor is open during the presense operation and closed during the latching operation (during the presense operation, transistor 84 is open. During the latching operation, transistor 84 is closed at T2), and wherein the drain of the sixth transistor is coupled to the source of the third and fourth transistors, wherein the negative voltage is less than the ground voltage.
Regarding claim 11, Kim teaches the memory device of claim 10, comprising:
a first isolating transistor coupled between the first digit line and the first gut node to selectively decouple the first digit line from the first gut node when amplifying a difference in voltages between the first and second gut nodes; and a second isolating transistor coupled between the second digit line and the second gut node to selectively decouple the second digit line from the second gut node when amplifying the difference in voltages between the first and second gut nodes (Fig. 3, transistors 6A and 6B isolate the digit line from the gut nodes).
Regarding claim 12, Kim further teaches the memory device of claim 10, wherein the first and second transistors comprise PMOS transistors (Fig. 3, transistors 20 and 22 are PMOS transistors).
Regarding claim 15, Kim further teaches the memory device of claim 10, wherein the fourth transistor is configured to use a charge of the first digit line to discharge a voltage stored in of the second gut node, wherein the first transistor is configured to use the discharged voltage of the second gut node to amplify the voltage of the first gut node to amplify a differential voltage between the first and second gut nodes, and wherein a gain used to amplify the differential voltage is based on a voltage difference between the negative voltage and the supply voltage (Fig. 5).
Regarding claims 16-17 and 19, the method have similar limitations as the claims above except they were written in a method format. Therefore, the claims are rejected under the same grounds of rejection.
Regarding claim 22, Kim teaches the memory device of claim 10, wherein the presense operation is configured to prepare the sense amplifier for subsequent operations comprising the latching operation and active idle operations (presense operation between T1 to T2 is part of sequence of operation of the sense amplifier which prepares for subsequent operation comprising the latching operation and the active idle operation after T2).
Regarding claim 23, Kim teaches the memory device of claim 22, wherein the presense operation is performed after a precharging operation and before the subsequent operations (Fig. 4, period before T0 can be considered a precharging operation, where the bit lines are precharged to VCC/2).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 13, 14 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim as applied to claims 10 or 16 above.
Regarding claims 13, 14 and 20, Kim teaches wherein the negative voltage is -0.3 V and the negative voltage is 1.95 below the supply voltage. Kim is silent in teaching wherein the negative voltage is characterized as a voltage between -0.25 volts (V) and -0.17V, and the negative voltage is characterized as a voltage between 1.1 volts (V) and 1.3V lower than the supply voltage. However, these numbers are very close to the numbers used by Kim and applying - 0.25V instead of -0.3 V would still have the memory operate in the same way. In addition, reference Kim was invented almost 20 years ago, which the SRAM used higher supply voltage comparing to SRAM memory device used in the present time. Low-power SRAM can operate with a supply voltage up to 1.2 V, which is within the claimed range. Any person with the ordinary skills in the art would be able to operate the memory device in the same way by applying these ranges. It would have been obvious to a person with the ordinary skill in the art before the effective filling date of the claimed invention to apply the voltage ranges based on design choice.
Response to Arguments
Applicant's arguments filed 01/20/206 have been fully considered but they are not persuasive.
Applicant’s representative argues on page 9 “In rejecting claim 1, the Office Action equated some of these recitations to, in Kim, the "first and second gut nodes are less than ground voltage, e.g. -0.3 V, at a first time and are coupled to a ground voltage at a second time, see Fig. 5 and ¶0024)." Office Action, p. 3. However, the Office Action does not provide evidence that, nor does Kim appear to disclose, for example, "wherein each sense amplifier is configured to operate based on coupling, during a presense phase, the first and second gut nodes to a negative voltage source characterized by a voltage less than a ground voltage and based on coupling, during at least a latching operation, the first and second gut nodes to the ground voltage," as set forth in amended claim 1 and further clarified in amendments to claims 4 and 5. Therefore, Kim does not appear to anticipate each recitation of amended claim 1.”
The term “presense operation” based on the specification of the current invention is described as the presense stage during which the sense amplifier 110 may operate in a differential voltage amplifier configuration. The sense amplifier taught by Kim is a differential voltage sense amplifier (Fig. 3), and during the period between T1 and T2 the sense amplifier operate in a differential voltage amplifier configuration. Therefore, Kim teaches wherein the sense amplifier is configured to operate based on coupling, during a presense phase (between T1 and T2), the first and second gut nodes (D/D_) to a negative voltage source characterized by a voltage less than a ground voltage (-0.3V). During at least a latching operation (Fig. 5, after T2), the first and second gut nodes are coupled to the ground voltage. Similar to claim 1, Kim teaches the claimed features of claims 10 and 16 as described above.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAMDAN N ALROBAIE whose telephone number is (571)270-7099. The examiner can normally be reached Monday to Thursday (8AM till 6PM).
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/Khamdan N. Alrobaie/ Primary Examiner, Art Unit 2824