DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 18-26 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected process, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 7/15/2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 6-9, 14-15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2023/0083114 A1 (Hwang).
Re claim 1, Hwang teaches a semiconductor device (semiconductor device 100) comprising:
a lower semiconductor structure (first substrate structure S1) including a lower semiconductor substrate (substrate 201) including a first region (first region R1) and a second region (second region R2) adjacent to each other in a horizontal direction, a lower circuit structure (circuit lines within insulating layer 290) disposed in the first region over the lower semiconductor substrate, a lower bonding pad (first bonding metal layers 298) disposed over the lower circuit structure and connected to the lower circuit structure, and a dummy conductive pattern (cell interconnection lines connected to dummy contact structures 150D) disposed in the second region over the lower semiconductor substrate;
an upper semiconductor structure (second substrate structures S2) including an upper semiconductor substrate (plate layer 101 [0040]) disposed over the lower semiconductor structure and including the first region and the second region, an upper circuit structure (circuit lines within insulating layer 192) disposed in the first region under the upper semiconductor substrate, and an upper bonding pad (metal layers 198) disposed under the upper circuit structure and connected to the upper circuit structure while being bonded to the lower bonding pad (Fig. 2B);
a through electrode (substrate contact 165) passing through the upper semiconductor substrate and connected to the upper circuit structure; and
a dummy through electrode (dummy contact structures 150D/150) passing through the upper semiconductor structure and connected to the dummy conductive pattern, wherein the dummy through electrode and the dummy conductive pattern are electrically connected to the lower semiconductor substrate through the lower circuit structure (Fig. 2B).
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Re claim 6, Hwang teaches wherein the upper bonding pad and the lower bonding pad form a metal-to-metal bond ([0081]).
Re claim 7, Hwang teaches wherein the lower semiconductor structure further includes a lower insulating layer (insulating layer 290) filled between the lower bonding pad and another lower bonding pad, the upper semiconductor structure further includes an upper insulating layer (insulating layer 192) filled between the upper bonding pad and another upper bonding pad, and the lower insulating layer and the upper insulating layer form an insulator-to-insulator bond ([0081]).
Re claim 8, Hwang teaches wherein an upper surface of the dummy conductive pattern is in contact with the upper insulating layer (Fig. 2B).
Re claim 9, Hwang teaches wherein the lower circuit structure includes a lower conductive pad (first bonding metal layers 298) disposed over the lower semiconductor substrate and a lower conductive via (first bonding vias 295) disposed over the lower conductive pad and connected the lower conductive pad, the lower bonding pad is disposed over the lower conductive via and connected thereto, the upper circuit structure includes an upper conductive pad (second bonding layer 198) disposed under the upper semiconductor substrate and an upper conductive via (second bonding vias 195) disposed under the upper conductive pad and connected to the upper conductive pad, the upper bonding pad is disposed under the upper conductive via and connected to the upper conductive via, and the lower conductive pad, the lower conductive via, the upper conductive pad, and the upper conductive via are arranged to form a daisy chain (Fig. 2B).
Re claim 14, Hwang teaches wherein the upper circuit structure includes an upper conductive pad, and the through electrode contacts an upper surface of the upper conductive pad (Fig. 2B).
Re claim 15, Hwang teaches wherein a height of a portion of the upper surface of the upper conductive pad, which is in contact with the through electrode, is lower than a height of a remaining portion (a portion can be the top 25% of the pad and the remaining portion being the bottom 75% such that the height of 25% is lower than the height of 75% of a structure).
Allowable Subject Matter
Claims 2-5, 10-13, 16-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2023/0387053 A1 (Kim)
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Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIGITTE A PATERSON whose telephone number is (571)272-1752. The examiner can normally be reached Monday-Friday 9:00AM-5:00PM.
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BRIGITTE A. PATERSON
Primary Examiner
Art Unit 2896
/BRIGITTE A PATERSON/Primary Examiner, Art Unit 2896
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